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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam4l_pdca.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PDCA_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PDCA_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* PDCA channel offsets *****************************************************************/
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#define SAM_PDCA_CHAN_OFFSET(n) ((n) << 6)
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#define SAM_PDCA_CHAN0_OFFSET 0x0000
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#define SAM_PDCA_CHAN1_OFFSET 0x0040
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#define SAM_PDCA_CHAN2_OFFSET 0x0080
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#define SAM_PDCA_CHAN3_OFFSET 0x00c0
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#define SAM_PDCA_CHAN4_OFFSET 0x0100
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#define SAM_PDCA_CHAN5_OFFSET 0x0140
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#define SAM_PDCA_CHAN6_OFFSET 0x0180
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#define SAM_PDCA_CHAN7_OFFSET 0x01c0
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#define SAM_PDCA_CHAN8_OFFSET 0x0200
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#define SAM_PDCA_CHAN9_OFFSET 0x0240
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#define SAM_PDCA_CHAN10_OFFSET 0x0280
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#define SAM_PDCA_CHAN11_OFFSET 0x02c0
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#define SAM_PDCA_CHAN12_OFFSET 0x0300
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#define SAM_PDCA_CHAN13_OFFSET 0x0340
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#define SAM_PDCA_CHAN14_OFFSET 0x0380
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#define SAM_PDCA_CHAN15_OFFSET 0x03c0
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/* PDCA register offsets ****************************************************************/
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/* Channel register offsets */
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#define SAM_PDCA_MAR_OFFSET 0x0000 /* Memory Address Register */
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#define SAM_PDCA_PSR_OFFSET 0x0004 /* Peripheral Select Register */
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#define SAM_PDCA_TCR_OFFSET 0x0008 /* Transfer Counter Register */
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#define SAM_PDCA_MARR_OFFSET 0x000c /* Memory Address Reload Register */
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#define SAM_PDCA_TCRR_OFFSET 0x0010 /* Transfer Counter Reload Register */
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#define SAM_PDCA_CR_OFFSET 0x0014 /* Control Register */
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#define SAM_PDCA_MR_OFFSET 0x0018 /* Mode Register */
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#define SAM_PDCA_SR_OFFSET 0x001c /* Status Register */
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#define SAM_PDCA_IER_OFFSET 0x0020 /* Interrupt Enable Register */
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#define SAM_PDCA_IDR_OFFSET 0x0024 /* Interrupt Disable Register */
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#define SAM_PDCA_IMR_OFFSET 0x0028 /* Interrupt Mask Register */
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#define SAM_PDCA_ISR_OFFSET 0x002c /* Interrupt Status Register */
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/* Global register offsets */
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#define SAM_PDCA_VERSION_OFFSET 0x834 /* Version Register */
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/* PDCA channel adresses ****************************************************************/
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/* Channel register base addresses */
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#define SAM_PDCA_CHAN(n) (SAM_PDCA_BASE+SAM_PDCA_CHAN_OFFSET(n))
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#define SAM_PDCA_CHAN0 (SAM_PDCA_BASE+SAM_PDCA_CHAN0_OFFSET)
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#define SAM_PDCA_CHAN1 (SAM_PDCA_BASE+SAM_PDCA_CHAN1_OFFSET)
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#define SAM_PDCA_CHAN2 (SAM_PDCA_BASE+SAM_PDCA_CHAN2_OFFSET)
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#define SAM_PDCA_CHAN3 (SAM_PDCA_BASE+SAM_PDCA_CHAN3_OFFSET)
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#define SAM_PDCA_CHAN4 (SAM_PDCA_BASE+SAM_PDCA_CHAN4_OFFSET)
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#define SAM_PDCA_CHAN5 (SAM_PDCA_BASE+SAM_PDCA_CHAN5_OFFSET)
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#define SAM_PDCA_CHAN6 (SAM_PDCA_BASE+SAM_PDCA_CHAN6_OFFSET)
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#define SAM_PDCA_CHAN7 (SAM_PDCA_BASE+SAM_PDCA_CHAN7_OFFSET)
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#define SAM_PDCA_CHAN8 (SAM_PDCA_BASE+SAM_PDCA_CHAN8_OFFSET)
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#define SAM_PDCA_CHAN9 (SAM_PDCA_BASE+SAM_PDCA_CHAN9_OFFSET)
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#define SAM_PDCA_CHAN10 (SAM_PDCA_BASE+SAM_PDCA_CHAN10_OFFSET)
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#define SAM_PDCA_CHAN11 (SAM_PDCA_BASE+SAM_PDCA_CHAN11_OFFSET)
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#define SAM_PDCA_CHAN12 (SAM_PDCA_BASE+SAM_PDCA_CHAN12_OFFSET)
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#define SAM_PDCA_CHAN13 (SAM_PDCA_BASE+SAM_PDCA_CHAN13_OFFSET)
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#define SAM_PDCA_CHAN14 (SAM_PDCA_BASE+SAM_PDCA_CHAN14_OFFSET)
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#define SAM_PDCA_CHAN15 (SAM_PDCA_BASE+SAM_PDCA_CHAN15_OFFSET)
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/* PDCA register adresses ***************************************************************/
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/* Channel register addresses */
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#define SAM_PDCA_MAR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MAR_OFFSET)
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#define SAM_PDCA_PSR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_PSR_OFFSET)
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#define SAM_PDCA_TCR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_TCR_OFFSET)
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#define SAM_PDCA_MARR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MARR_OFFSET)
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#define SAM_PDCA_TCRR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_TCRR_OFFSET)
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#define SAM_PDCA_CR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_CR_OFFSET)
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#define SAM_PDCA_MR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MR_OFFSET)
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#define SAM_PDCA_SR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_SR_OFFSET)
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#define SAM_PDCA_IER(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_IER_OFFSET)
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#define SAM_PDCA_IDR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_IDR_OFFSET)
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#define SAM_PDCA_IMR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_IMR_OFFSET)
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#define SAM_PDCA_ISR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_ISR_OFFSET)
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/* Global register offsets */
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#define SAM_PDCA_VERSION (SAM_PDCA_BASE+SAM_PDCA_VERSION_OFFSET)
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/* PDCA register bit definitions ********************************************************/
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/* Memory Address Register (32-bit address) */
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/* Peripheral Select Register */
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#define PDCA_PSR_MASK 0xff /* Bit 0-7: Peripheral identifier */
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/* Transfer Counter Register */
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#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value
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/* Memory Address Reload Register (32-bit address) */
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/* Transfer Counter Reload Register */
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#define PDCA_TCRR_MASK 0xffff /* Bits 0-15: Transfer Counter Reload Value */
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/* Control Register */
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#define PDCA_CR_TEN (1 << 0) /* Bit 0: Transfer Enable */
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#define PDCA_CR_TDIS (1 << 1) /* Bit 1: Transfer Disable */
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#define PDCA_CR_ECLR (1 << 8) /* Bit 8: Transfer Error Clear */
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/* Mode Register */
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#define PDCA_MR_SIZE_SHIFT (0) /* Bits 0-1: Size of Transfer */
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#define PDCA_MR_SIZE_MASK (3 << PDCA_MR_SIZE_SHIFT)
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# define PDCA_MR_SIZE_BYTE (0 << PDCA_MR_SIZE_SHIFT)
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# define PDCA_MR_SIZE_HWORD (1 << PDCA_MR_SIZE_SHIFT)
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# define PDCA_MR_SIZE_WORD (2 << PDCA_MR_SIZE_SHIFT)
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#define PDCA_MR_ETRIG (1 << 2) /* Bit 2: Event Trigger */
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#define PDCA_MR_RING (1 << 3) /* Bit 3: Ring Buffer */
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/* Status Register */
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#define PDCA_SR_TEN (1 << 0) /* Bit 0: Transfer Enabled */
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/* Interrupt Enable Register */
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#define PDCA_IER_
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/* Interrupt Disable Register */
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/* Interrupt Mask Register */
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/* Interrupt Status Register */
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#define PDCA_INT_RCZ (1 << 2) /* Bit 0: Reload Counter Zero */
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#define PDCA_INT_TRC (1 << 2) /* Bit 1: Transfer Complete */
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#define PDCA_INT_TERR (1 << 2) /* Bit 2: Transfer Error */
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/* Global register offsets */
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/* Version Register */
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#define PDCA_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
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#define PDCA_VERSION_MASK (0xfff << PDCA_VERSION_VERSION_SHIFT)
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#define PDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
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#define PDCA_VARIANT_MASK (15 << PDCA_VARIANT_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PDCA_H */
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Gregory Nutt