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STM32 F7 Ethernet: Add logic to align all DMA memory to the D-Cache line size

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Gregory Nutt
2015-07-19 16:35:25 -06:00
parent c4d91c8c9f
commit 2ce3c75264
2 changed files with 235 additions and 145 deletions
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arch/arm/src/stm32f7/stm32_ethernet.c
+233 -143
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arch/arm/src/stm32f7/stm32_serial.c
+2 -2
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@@ -394,9 +394,9 @@ static const struct uart_ops_s g_uart_dma_ops =
/* DMA buffers. DMA buffers must:
*
* 1. Be a multiple of the I-Cache line size. This requirement is assured
* 1. Be a multiple of the D-Cache line size. This requirement is assured
* by the definition of RXDMA buffer size above.
* 2. Be aligned a I-Cache line boundaries, and
* 2. Be aligned a D-Cache line boundaries, and
* 3. Be positioned in DMA-able memory (*NOT* DTCM memory). This must
* be managed by logic in the linker script file.
*