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arch/arm/src/imxrt/imxrt_clockconfig.c and board.h: Allow clock setting for SPI and I2C from board.h.

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This commit is contained in:
David Sidrane
2019-12-12 08:33:05 -06:00
committed by Gregory Nutt
parent 42dfd18d7c
commit 2cbcb8fd00
4 changed files with 47 additions and 5 deletions
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arch/arm/src/imxrt/imxrt_clockconfig.c
+4 -4
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@@ -513,7 +513,7 @@ void imxrt_clockconfig(void)
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_PODF_MASK;
reg |= CCM_CSCDR1_UART_CLK_PODF(0);
reg |= CCM_CSCDR1_UART_CLK_PODF(CCM_PODF_FROM_DIVISOR(1));
putreg32(reg, IMXRT_CCM_CSCDR1);
#ifdef CONFIG_IMXRT_LPI2C
@@ -521,14 +521,14 @@ void imxrt_clockconfig(void)
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_SEL;
reg |= CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M;
reg |= IMXRT_LPI2C_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCDR2);
/* Set LPI2C divider to 5 for 12 Mhz */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5 - 1);
reg |= CCM_CSCDR2_LPI2C_CLK_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_LSI2C_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCDR2);
#endif
@@ -538,7 +538,7 @@ void imxrt_clockconfig(void)
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_CLK_SEL_MASK;
reg |= CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0;
reg |= IMXRT_LPSPI_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set LPSPI divider to IMXRT_LSPI_PODF_DIVIDER */
boards/arm/imxrt/imxrt1020-evk/include/board.h
+14 -1
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@@ -85,6 +85,14 @@
* Set USB1 PLL (PLL3) to fOut = (24Mhz * 20)
* 480Mhz = (24Mhz * 20)
*
* Set LPSPI PLL3 PFD0 to fOut = (480Mhz / 12 * 18)
* 720Mhz = (480Mhz / 12 * 18)
* 90Mhz = (720Mhz / LSPI_PODF_DIVIDER)
*
* Set LPI2C PLL3 / 8 to fOut = (480Mhz / 8)
* 60Mhz = (480Mhz / 8)
* 12Mhz = (60Mhz / LSPI_PODF_DIVIDER)
*
* These clock frequencies can be verified via the CCM_CLKO1 pin and sending
* the appropriate clock to it with something like;
*
@@ -103,11 +111,16 @@
#define IMXRT_PERCLK_CLK_SEL CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT
#define IMXRT_PERCLK_PODF_DIVIDER 2
#define IMXRT_SEMC_PODF_DIVIDER 4
#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0
#define IMXRT_LSPI_PODF_DIVIDER 8
#define IMXRT_LPI2C_CLK_SELECT CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M
#define IMXRT_LSI2C_PODF_DIVIDER 5
#define IMXRT_USDHC1_CLK_SELECT CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0
#define IMXRT_USDHC1_PODF_DIVIDER 1
#define IMXRT_USDHC1_CLK_SELECT CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0
#define IMXRT_USDHC2_CLK_SELECT CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0
#define IMXRT_USDHC2_PODF_DIVIDER 4
#define IMXRT_SYS_PLL_DIV_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22
boards/arm/imxrt/imxrt1050-evk/include/board.h
+15
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@@ -91,6 +91,14 @@
* Set USB1 PLL (PLL3) to fOut = (24Mhz * 20)
* 480Mhz = (24Mhz * 20)
*
* Set LPSPI PLL3 PFD0 to fOut = (480Mhz / 12 * 18)
* 720Mhz = (480Mhz / 12 * 18)
* 90Mhz = (720Mhz / LSPI_PODF_DIVIDER)
*
* Set LPI2C PLL3 / 8 to fOut = (480Mhz / 8)
* 60Mhz = (480Mhz / 8)
* 12Mhz = (60Mhz / LSPI_PODF_DIVIDER)
*
* These clock frequencies can be verified via the CCM_CLKO1 pin and sending
* the appropriate clock to it with something like;
*
@@ -110,6 +118,13 @@
#define IMXRT_SEMC_PODF_DIVIDER 8
#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0
#define IMXRT_LSPI_PODF_DIVIDER 8
#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0
#define IMXRT_LSPI_PODF_DIVIDER 8
#define IMXRT_LPI2C_CLK_SELECT CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M
#define IMXRT_LSI2C_PODF_DIVIDER 5
#define IMXRT_USDHC1_CLK_SELECT CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0
#define IMXRT_USDHC1_PODF_DIVIDER 2
boards/arm/imxrt/imxrt1060-evk/include/board.h
+14
View File
@@ -91,6 +91,14 @@
* Set USB1 PLL (PLL3) to fOut = (24Mhz * 20)
* 480Mhz = (24Mhz * 20)
*
* Set LPSPI PLL3 PFD0 to fOut = (480Mhz / 12 * 18)
* 720Mhz = (480Mhz / 12 * 18)
* 90Mhz = (720Mhz / LSPI_PODF_DIVIDER)
*
* Set LPI2C PLL3 / 8 to fOut = (480Mhz / 8)
* 60Mhz = (480Mhz / 8)
* 12Mhz = (60Mhz / LSPI_PODF_DIVIDER)
*
* These clock frequencies can be verified via the CCM_CLKO1 pin and sending
* the appropriate clock to it with something like;
*
@@ -109,6 +117,12 @@
#define IMXRT_PERCLK_PODF_DIVIDER 9
#define IMXRT_SEMC_PODF_DIVIDER 8
#define IMXRT_LPSPI_CLK_SELECT CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0
#define IMXRT_LSPI_PODF_DIVIDER 8
#define IMXRT_LPI2C_CLK_SELECT CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M
#define IMXRT_LSI2C_PODF_DIVIDER 5
#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22
#define BOARD_CPU_FREQUENCY \