mirror of
https://github.com/apache/nuttx.git
synced 2026-05-26 02:36:11 +08:00
Merged in raiden00/nuttx_h7 (pull request #837)
Initial OTG support for STM32H7 and some minor improvements arch/arm/src/stm32h7/stm32h7x3xx_rcc.c: add support for HSI48 clock configs/nucleo-f207zg: add support for USB and initialize CDCACM if configured configs/nucleo-h743zi: add support for USB and initialize CDCACM if configured drivers/usbdev/Kconfig: fix type for USBDEV_TRACE_INITIALIDSET configs/teensy-3.x/usbnsh/defconfig: update config according to change in USBDEV_TRACE_INITIALIDSET Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
Gregory Nutt
@@ -161,6 +161,40 @@ config STM32H7_BDMA
|
||||
select STM32H7_DMA
|
||||
select ARCH_DMA
|
||||
|
||||
config STM32H7_OTGFS
|
||||
bool "OTG FS"
|
||||
default n
|
||||
select USBHOST_HAVE_ASYNCH if USBHOST
|
||||
|
||||
config STM32H7_OTGHS
|
||||
bool "OTG HS"
|
||||
default n
|
||||
depends on EXPERIMENTAL
|
||||
select USBHOST_HAVE_ASYNCH if USBHOST
|
||||
|
||||
config STM32H7_OTG_SOFOUTPUT
|
||||
bool "OTG SOF output"
|
||||
default n
|
||||
|
||||
config STM32H7_OTG_USBREGEN
|
||||
bool "Enable USB voltage regulator"
|
||||
default n
|
||||
|
||||
config STM32H7_USBDEV_REGDEBUG
|
||||
bool "OTG USBDEV REGDEBUG"
|
||||
default n
|
||||
depends on USBDEV
|
||||
|
||||
config STM32H7_USBHOST_REGDEBUG
|
||||
bool "OTG USBHOST REGDEBUG"
|
||||
default n
|
||||
depends on USBHOST
|
||||
|
||||
config STM32H7_USBHOST_PKTDUMP
|
||||
bool "OTG USBHOST PKTDUMP"
|
||||
default n
|
||||
depends on USBHOST
|
||||
|
||||
menu "STM32H7 I2C Selection"
|
||||
|
||||
config STM32H7_I2C1
|
||||
@@ -229,6 +263,10 @@ config STM32H7_SPI6
|
||||
select SPI
|
||||
select STM32H7_SPI
|
||||
|
||||
config STM32H7_SYSCFG
|
||||
bool "SYSCFG"
|
||||
default y
|
||||
|
||||
endmenu # STM32H7 SPI Selection
|
||||
|
||||
menu "STM32H7 U[S]ART Selection"
|
||||
|
||||
@@ -125,3 +125,11 @@ endif
|
||||
ifeq ($(CONFIG_STM32H7_SPI),y)
|
||||
CHIP_CSRCS += stm32_spi.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USBDEV),y)
|
||||
CHIP_CSRCS += stm32_otgdev.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_USBHOST),y)
|
||||
CHIP_CSRCS += stm32_otghost.c
|
||||
endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -160,8 +160,8 @@
|
||||
#define STM32_DMAMUX1_BASE 0x40020800 /* 0x40020800-0x40020bff DMAMUX1 */
|
||||
#define STM32_ADC12_BASE 0x40022000 /* 0x40022000-0x400223ff ADC1-ADC2 */
|
||||
#define STM32_EMAC_BASE 0x40028000 /* 0x40028000-0x400293ff Ethernet MAC */
|
||||
#define STM32_USB1_BASE 0x40040000 /* 0x40040000-0x4007ffff USB1 OTG HS/FS */
|
||||
#define STM32_USB2_BASE 0x40080000 /* 0x40080000-0x400bffff USB2 OTG FS */
|
||||
#define STM32_OTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff USB1 OTG HS/FS */
|
||||
#define STM32_OTGFS_BASE 0x40080000 /* 0x40080000-0x400bffff USB2 OTG FS */
|
||||
|
||||
/* AHB2 Base Addresses **************************************************************/
|
||||
|
||||
|
||||
@@ -671,17 +671,17 @@
|
||||
|
||||
/* USB on-the-go full-speed (OTG_FS) */
|
||||
|
||||
#define GPIO_OTG_FS_DM (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTG_FS_DP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTG_FS_ID (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTG_FS_SOF (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
/* USB on-the-go high-speed (OTG_HS) */
|
||||
|
||||
#define GPIO_OTG_HS_DM (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTG_HS_DP (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTG_HS_ID (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTG_HS_SOF (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_OTGHS_ID (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#define GPIO_OTG_HS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_OTG_HS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
@@ -109,6 +109,17 @@
|
||||
|
||||
/* Power control register 3 (CR3) */
|
||||
|
||||
#define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */
|
||||
#define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */
|
||||
#define STM32_PWR_CR3_LDOESCUEN (1 << 2) /* Bit 2: Supply configuration update enable */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define STM32_PWR_CR3_VBE (1 << 8) /* Bit 8: VBAT charging enable */
|
||||
#define STM32_PWR_CR3_VBRS (1 << 9) /* Bit 9: VBAT charging resistor selection */
|
||||
/* Bits 10-23: Reserved */
|
||||
#define STM32_PWR_CR3_USB33DEN (1 << 24) /* Bit 24: VDD33USB voltage level detector enable */
|
||||
#define STM32_PWR_CR3_USBREGEN (1 << 25) /* Bit 25: USB regulator enable */
|
||||
#define STM32_PWR_CR3_USB33RDY (1 << 26) /* Bit 26: USB supply ready */
|
||||
|
||||
/* Power CPU control register (CPUCR) */
|
||||
|
||||
/* Power D3 domain control register (D3CR) */
|
||||
|
||||
@@ -583,16 +583,30 @@
|
||||
# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */
|
||||
# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 1 */
|
||||
|
||||
/* TODO: Bit definitions for RCC_D2CCIP2R reigster */
|
||||
/* Bit definitions for RCC_D2CCIP2R reigster */
|
||||
|
||||
/* ... */
|
||||
#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */
|
||||
#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */
|
||||
/* ... */
|
||||
#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */
|
||||
# define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT)
|
||||
#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */
|
||||
# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT)
|
||||
#define RCC_D2CCIP2R_RNGSEL_SHIFT (3) /* Bits 8-9 */
|
||||
# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT)
|
||||
#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */
|
||||
#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */
|
||||
# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */
|
||||
#define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */
|
||||
# define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_USBSEL_PLL1 (1 << RCC_D2CCIP2R_USBSEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_USBSEL_PLL3 (2 << RCC_D2CCIP2R_USBSEL_SHIFT)
|
||||
# define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT)
|
||||
#define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */
|
||||
# define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT)
|
||||
#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */
|
||||
# define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT)
|
||||
|
||||
/* TODO: Bit definitions for RCC_D3CCIPR reigster */
|
||||
|
||||
@@ -665,27 +679,18 @@
|
||||
|
||||
/* Bit definitions for RCC_CSR register */
|
||||
|
||||
#define RCC_CSR_LSION_SHIFT (0ul) /* RCC CSR: LSION (Bit 0) */
|
||||
#define RCC_CSR_LSION (0x1ul) /* RCC CSR: LSION (Bitfield-Mask: 0x01) */
|
||||
#define RCC_CSR_LSIRDY_SHIFT (1ul) /* RCC CSR: LSIRDY (Bit 1) */
|
||||
#define RCC_CSR_LSIRDY (0x2ul) /* RCC CSR: LSIRDY (Bitfield-Mask: 0x01) */
|
||||
#define RCC_CSR_LSION (1 << 0) /* RCC CSR: LSION */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* RCC CSR: LSIRDY */
|
||||
|
||||
/* AHB3 peripheral reset register */
|
||||
|
||||
#define RCC_AHB3RSTR_MDMARST_SHIFT (0ul) /* RCC AHB3RSTR: MDMARST (Bit 0) */
|
||||
#define RCC_AHB3RSTR_MDMARST (0x1ul) /* RCC AHB3RSTR: MDMARST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_DMA2DRST_SHIFT (4ul) /* RCC AHB3RSTR: DMA2DRST (Bit 4) */
|
||||
#define RCC_AHB3RSTR_DMA2DRST (0x10ul) /* RCC AHB3RSTR: DMA2DRST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_JPGDECRST_SHIFT (5ul) /* RCC AHB3RSTR: JPGDECRST (Bit 5) */
|
||||
#define RCC_AHB3RSTR_JPGDECRST (0x20ul) /* RCC AHB3RSTR: JPGDECRST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_FMCRST_SHIFT (12ul) /* RCC AHB3RSTR: FMCRST (Bit 12) */
|
||||
#define RCC_AHB3RSTR_FMCRST (0x1000ul) /* RCC AHB3RSTR: FMCRST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_QSPIRST_SHIFT (14ul) /* RCC AHB3RSTR: QSPIRST (Bit 14) */
|
||||
#define RCC_AHB3RSTR_QSPIRST (0x4000ul) /* RCC AHB3RSTR: QSPIRST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_SDMMC1RST_SHIFT (16ul) /* RCC AHB3RSTR: SDMMC1RST (Bit 16) */
|
||||
#define RCC_AHB3RSTR_SDMMC1RST (0x10000ul) /* RCC AHB3RSTR: SDMMC1RST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_CPURST_SHIFT (31ul) /* RCC AHB3RSTR: CPURST (Bit 31) */
|
||||
#define RCC_AHB3RSTR_CPURST (0x80000000ul) /* RCC AHB3RSTR: CPURST (Bitfield-Mask: 0x01) */
|
||||
#define RCC_AHB3RSTR_MDMARST (1 << 0) /* RCC AHB3RSTR: MDMARST */
|
||||
#define RCC_AHB3RSTR_DMA2DRST (1 << 4) /* RCC AHB3RSTR: DMA2DRST */
|
||||
#define RCC_AHB3RSTR_JPGDECRST (1 << 5) /* RCC AHB3RSTR: JPGDECRST */
|
||||
#define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */
|
||||
#define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */
|
||||
#define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */
|
||||
#define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */
|
||||
|
||||
/* AHB1 peripheral reset register */
|
||||
|
||||
@@ -695,9 +700,9 @@
|
||||
/* Bits 6-14: Reserved */
|
||||
#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */
|
||||
/* Bits 16-24: Reserved */
|
||||
#define RCC_AHB1RSTR_USB1OTGRST (1 << 25) /* RCC AHB1RSTR: USB1OTGRST */
|
||||
#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */
|
||||
/* Bit 26: Reserved */
|
||||
#define RCC_AHB1RSTR_USB2OTGRST (1 << 27) /* RCC AHB1RSTR: USB2OTGRST */
|
||||
#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */
|
||||
/* Bits 28-31: Reserved */
|
||||
|
||||
/* AHB2 peripheral reset register */
|
||||
@@ -837,10 +842,9 @@
|
||||
#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */
|
||||
#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */
|
||||
#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */
|
||||
#define RCC_AHB1ENR_USB1OTGEN (1 << 25) /* RCC AHB1ENR: USB1OTGEN */
|
||||
#define RCC_AHB1ENR_USB1ULPIEN (1 << 26) /* RCC AHB1ENR: USB1ULPIEN */
|
||||
#define RCC_AHB1ENR_USB2OTGEN (1 << 27) /* RCC AHB1ENR: USB2OTGEN */
|
||||
#define RCC_AHB1ENR_USB2ULPIEN (1 << 28) /* RCC AHB1ENR: USB2ULPIEN */
|
||||
#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */
|
||||
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */
|
||||
#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */
|
||||
|
||||
/* AHB2 Peripheral Clock enable register */
|
||||
|
||||
@@ -968,134 +972,133 @@
|
||||
|
||||
/* AHB3 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB3LPENR_MDMALPEN (0x1ul) /* RCC AHB3LPENR: MDMALPEN */
|
||||
#define RCC_AHB3LPENR_DMA2DLPEN (0x10ul) /* RCC AHB3LPENR: DMA2DLPEN */
|
||||
#define RCC_AHB3LPENR_JPGDECLPEN (0x20ul) /* RCC AHB3LPENR: JPGDECLPEN */
|
||||
#define RCC_AHB3LPENR_FLITFLPEN (0x100ul) /* RCC AHB3LPENR: FLITFLPEN */
|
||||
#define RCC_AHB3LPENR_FMCLPEN (0x1000ul) /* RCC AHB3LPENR: FMCLPEN */
|
||||
#define RCC_AHB3LPENR_QSPILPEN (0x4000ul) /* RCC AHB3LPENR: QSPILPEN */
|
||||
#define RCC_AHB3LPENR_SDMMC1LPEN (0x10000ul) /* RCC AHB3LPENR: SDMMC1LPEN */
|
||||
#define RCC_AHB3LPENR_D1DTCM1LPEN (0x10000000ul) /* RCC AHB3LPENR: D1DTCM1LPEN */
|
||||
#define RCC_AHB3LPENR_DTCM2LPEN (0x20000000ul) /* RCC AHB3LPENR: DTCM2LPEN */
|
||||
#define RCC_AHB3LPENR_ITCMLPEN (0x40000000ul) /* RCC AHB3LPENR: ITCMLPEN */
|
||||
#define RCC_AHB3LPENR_AXISRAMLPEN (0x80000000ul) /* RCC AHB3LPENR: AXISRAMLPEN */
|
||||
#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */
|
||||
#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */
|
||||
#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */
|
||||
#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */
|
||||
#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */
|
||||
#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */
|
||||
#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */
|
||||
#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */
|
||||
#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */
|
||||
#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */
|
||||
#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */
|
||||
|
||||
/* AHB1 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB1LPENR_DMA1LPEN (0x1ul) /* RCC AHB1LPENR: DMA1LPEN */
|
||||
#define RCC_AHB1LPENR_DMA2LPEN (0x2ul) /* RCC AHB1LPENR: DMA2LPEN */
|
||||
#define RCC_AHB1LPENR_ADC12LPEN (0x20ul) /* RCC AHB1LPENR: ADC12LPEN */
|
||||
#define RCC_AHB1LPENR_ETH1MACLPEN (0x8000ul) /* RCC AHB1LPENR: ETH1MACLPEN */
|
||||
#define RCC_AHB1LPENR_ETH1TXLPEN (0x10000ul) /* RCC AHB1LPENR: ETH1TXLPEN */
|
||||
#define RCC_AHB1LPENR_ETH1RXLPEN (0x20000ul) /* RCC AHB1LPENR: ETH1RXLPEN */
|
||||
#define RCC_AHB1LPENR_USB1OTGLPEN (0x2000000ul) /* RCC AHB1LPENR: USB1OTGLPEN */
|
||||
#define RCC_AHB1LPENR_USB1ULPILPEN (0x4000000ul) /* RCC AHB1LPENR: USB1ULPILPEN */
|
||||
#define RCC_AHB1LPENR_USB2OTGLPEN (0x8000000ul) /* RCC AHB1LPENR: USB2OTGLPEN */
|
||||
#define RCC_AHB1LPENR_USB2ULPILPEN (0x10000000ul) /* RCC AHB1LPENR: USB2ULPILPEN */
|
||||
#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */
|
||||
#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */
|
||||
#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */
|
||||
#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */
|
||||
#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */
|
||||
#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */
|
||||
#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */
|
||||
#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */
|
||||
#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */
|
||||
|
||||
|
||||
/* AHB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_AHB2LPENR_CAMITFLPEN (0x1ul) /* RCC AHB2LPENR: CAMITFLPEN */
|
||||
#define RCC_AHB2LPENR_CRYPTLPEN (0x10ul) /* RCC AHB2LPENR: CRYPTLPEN */
|
||||
#define RCC_AHB2LPENR_HASHLPEN (0x20ul) /* RCC AHB2LPENR: HASHLPEN */
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN (0x200ul) /* RCC AHB2LPENR: SDMMC2LPEN */
|
||||
#define RCC_AHB2LPENR_RNGLPEN (0x40ul) /* RCC AHB2LPENR: RNGLPEN */
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN (0x20000000ul) /* RCC AHB2LPENR: SRAM1LPEN */
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN (0x40000000ul) /* RCC AHB2LPENR: SRAM2LPEN */
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN (0x80000000ul) /* RCC AHB2LPENR: SRAM3LPEN */
|
||||
#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */
|
||||
#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */
|
||||
#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */
|
||||
#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */
|
||||
#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */
|
||||
#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */
|
||||
#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */
|
||||
#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */
|
||||
|
||||
/* AHB4 low power mode peripheral clock enable register*/
|
||||
|
||||
#define RCC_AHB4LPENR_GPIOALPEN (0x1ul) /* RCC AHB4LPENR: GPIOALPEN */
|
||||
#define RCC_AHB4LPENR_GPIOBLPEN (0x2ul) /* RCC AHB4LPENR: GPIOBLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOCLPEN (0x4ul) /* RCC AHB4LPENR: GPIOCLPEN */
|
||||
#define RCC_AHB4LPENR_GPIODLPEN (0x8ul) /* RCC AHB4LPENR: GPIODLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOELPEN (0x10ul) /* RCC AHB4LPENR: GPIOELPEN */
|
||||
#define RCC_AHB4LPENR_GPIOFLPEN (0x20ul) /* RCC AHB4LPENR: GPIOFLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOGLPEN (0x40ul) /* RCC AHB4LPENR: GPIOGLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOHLPEN (0x80ul) /* RCC AHB4LPENR: GPIOHLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOILPEN (0x100ul) /* RCC AHB4LPENR: GPIOILPEN */
|
||||
#define RCC_AHB4LPENR_GPIOJLPEN (0x200ul) /* RCC AHB4LPENR: GPIOJLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOKLPEN (0x400ul) /* RCC AHB4LPENR: GPIOKLPEN */
|
||||
#define RCC_AHB4LPENR_CRCLPEN (0x80000ul) /* RCC AHB4LPENR: CRCLPEN */
|
||||
#define RCC_AHB4LPENR_BDMALPEN (0x200000ul) /* RCC AHB4LPENR: BDMALPEN */
|
||||
#define RCC_AHB4LPENR_ADC3LPEN (0x1000000ul) /* RCC AHB4LPENR: ADC3LPEN */
|
||||
#define RCC_AHB4LPENR_BKPRAMLPEN (0x10000000ul) /* RCC AHB4LPENR: BKPRAMLPEN */
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN (0x20000000ul) /* RCC AHB4LPENR: SRAM4LPEN */
|
||||
#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */
|
||||
#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */
|
||||
#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */
|
||||
#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */
|
||||
#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */
|
||||
#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */
|
||||
#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */
|
||||
#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */
|
||||
#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */
|
||||
#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */
|
||||
#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */
|
||||
|
||||
/* APB3 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB3LPENR_LTDCLPEN (0x8ul) /* RCC APB3LPENR: LTDCLPEN */
|
||||
#define RCC_APB3LPENR_WWDG1LPEN (0x40ul) /* RCC APB3LPENR: WWDG1LPEN */
|
||||
#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */
|
||||
#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */
|
||||
|
||||
/* APB1 L low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB1LLPENR_TIM2LPEN (0x1ul) /* RCC APB1LLPENR: TIM2LPEN */
|
||||
#define RCC_APB1LLPENR_TIM3LPEN (0x2ul) /* RCC APB1LLPENR: TIM3LPEN */
|
||||
#define RCC_APB1LLPENR_TIM4LPEN (0x4ul) /* RCC APB1LLPENR: TIM4LPEN */
|
||||
#define RCC_APB1LLPENR_TIM5LPEN (0x8ul) /* RCC APB1LLPENR: TIM5LPEN */
|
||||
#define RCC_APB1LLPENR_TIM6LPEN (0x10ul) /* RCC APB1LLPENR: TIM6LPEN */
|
||||
#define RCC_APB1LLPENR_TIM7LPEN (0x20ul) /* RCC APB1LLPENR: TIM7LPEN */
|
||||
#define RCC_APB1LLPENR_TIM12LPEN (0x40ul) /* RCC APB1LLPENR: TIM12LPEN */
|
||||
#define RCC_APB1LLPENR_TIM13LPEN (0x80ul) /* RCC APB1LLPENR: TIM13LPEN */
|
||||
#define RCC_APB1LLPENR_TIM14LPEN (0x100ul) /* RCC APB1LLPENR: TIM14LPEN */
|
||||
#define RCC_APB1LLPENR_LPTIM1LPEN (0x200ul) /* RCC APB1LLPENR: LPTIM1LPEN */
|
||||
#define RCC_APB1LLPENR_SPI2LPEN (0x4000ul) /* RCC APB1LLPENR: SPI2LPEN */
|
||||
#define RCC_APB1LLPENR_SPI3LPEN (0x8000ul) /* RCC APB1LLPENR: SPI3LPEN */
|
||||
#define RCC_APB1LLPENR_SPDIFRXLPEN (0x10000ul) /* RCC APB1LLPENR: SPDIFRXLPEN */
|
||||
#define RCC_APB1LLPENR_USART2LPEN (0x20000ul) /* RCC APB1LLPENR: USART2LPEN */
|
||||
#define RCC_APB1LLPENR_USART3LPEN (0x40000ul) /* RCC APB1LLPENR: USART3LPEN */
|
||||
#define RCC_APB1LLPENR_UART4LPEN (0x80000ul) /* RCC APB1LLPENR: UART4LPEN */
|
||||
#define RCC_APB1LLPENR_UART5LPEN (0x100000ul) /* RCC APB1LLPENR: UART5LPEN */
|
||||
#define RCC_APB1LLPENR_I2C1LPEN (0x200000ul) /* RCC APB1LLPENR: I2C1LPEN */
|
||||
#define RCC_APB1LLPENR_I2C2LPEN (0x400000ul) /* RCC APB1LLPENR: I2C2LPEN */
|
||||
#define RCC_APB1LLPENR_I2C3LPEN (0x800000ul) /* RCC APB1LLPENR: I2C3LPEN */
|
||||
#define RCC_APB1LLPENR_HDMICECLPEN (0x8000000ul) /* RCC APB1LLPENR: HDMICECLPEN */
|
||||
#define RCC_APB1LLPENR_DAC1LPEN (0x20000000ul) /* RCC APB1LLPENR: DAC1LPEN */
|
||||
#define RCC_APB1LLPENR_USART7LPEN (0x40000000ul) /* RCC APB1LLPENR: USART7LPEN */
|
||||
#define RCC_APB1LLPENR_USART8LPEN (0x80000000ul) /* RCC APB1LLPENR: USART8LPEN */
|
||||
#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */
|
||||
#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */
|
||||
#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */
|
||||
#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */
|
||||
#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */
|
||||
#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */
|
||||
#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */
|
||||
#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */
|
||||
#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */
|
||||
#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */
|
||||
#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */
|
||||
#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */
|
||||
#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */
|
||||
#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */
|
||||
#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */
|
||||
#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */
|
||||
#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */
|
||||
#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */
|
||||
#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */
|
||||
#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */
|
||||
#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */
|
||||
#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */
|
||||
#define RCC_APB1LLPENR_USART7LPEN (1 << 30) /* RCC APB1LLPENR: USART7LPEN */
|
||||
#define RCC_APB1LLPENR_USART8LPEN (1 << 31) /* RCC APB1LLPENR: USART8LPEN */
|
||||
|
||||
|
||||
/* APB1 H low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB1HLPENR_CRSLPEN (0x2ul) /* RCC APB1HLPENR: CRSLPEN */
|
||||
#define RCC_APB1HLPENR_SWPLPEN (0x4ul) /* RCC APB1HLPENR: SWPLPEN */
|
||||
#define RCC_APB1HLPENR_OPAMPLPEN (0x10ul) /* RCC APB1HLPENR: OPAMPLPEN */
|
||||
#define RCC_APB1HLPENR_MDIOSLPEN (0x20ul) /* RCC APB1HLPENR: MDIOSLPEN */
|
||||
#define RCC_APB1HLPENR_FDCANLPEN (0x100ul) /* RCC APB1HLPENR: FDCANLPEN */
|
||||
#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */
|
||||
#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */
|
||||
#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */
|
||||
#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */
|
||||
#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */
|
||||
|
||||
/* APB2 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB2LPENR_TIM1LPEN (0x1ul) /* RCC APB2LPENR: TIM1LPEN */
|
||||
#define RCC_APB2LPENR_TIM8LPEN (0x2ul) /* RCC APB2LPENR: TIM8LPEN */
|
||||
#define RCC_APB2LPENR_USART1LPEN (0x10ul) /* RCC APB2LPENR: USART1LPEN */
|
||||
#define RCC_APB2LPENR_USART6LPEN (0x20ul) /* RCC APB2LPENR: USART6LPEN */
|
||||
#define RCC_APB2LPENR_SPI1LPEN (0x1000ul) /* RCC APB2LPENR: SPI1LPEN */
|
||||
#define RCC_APB2LPENR_SPI4LPEN (0x2000ul) /* RCC APB2LPENR: SPI4LPEN */
|
||||
#define RCC_APB2LPENR_TIM15LPEN (0x10000ul) /* RCC APB2LPENR: TIM15LPEN */
|
||||
#define RCC_APB2LPENR_TIM16LPEN (0x20000ul) /* RCC APB2LPENR: TIM16LPEN */
|
||||
#define RCC_APB2LPENR_TIM17LPEN (0x40000ul) /* RCC APB2LPENR: TIM17LPEN */
|
||||
#define RCC_APB2LPENR_SPI5LPEN (0x100000ul) /* RCC APB2LPENR: SPI5LPEN */
|
||||
#define RCC_APB2LPENR_SAI1LPEN (0x400000ul) /* RCC APB2LPENR: SAI1LPEN */
|
||||
#define RCC_APB2LPENR_SAI2LPEN (0x800000ul) /* RCC APB2LPENR: SAI2LPEN */
|
||||
#define RCC_APB2LPENR_SAI3LPEN (0x1000000ul) /* RCC APB2LPENR: SAI3LPEN */
|
||||
#define RCC_APB2LPENR_DFSDM1LPEN (0x10000000ul) /* RCC APB2LPENR: DFSDM1LPEN */
|
||||
#define RCC_APB2LPENR_HRTIMLPEN (0x20000000ul) /* RCC APB2LPENR: HRTIMLPEN */
|
||||
#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */
|
||||
#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */
|
||||
#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */
|
||||
#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */
|
||||
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */
|
||||
#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */
|
||||
#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */
|
||||
#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */
|
||||
#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */
|
||||
#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */
|
||||
#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */
|
||||
#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */
|
||||
#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */
|
||||
#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */
|
||||
#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */
|
||||
|
||||
/* APB4 low power mode peripheral clock enable register */
|
||||
|
||||
#define RCC_APB4LPENR_SYSCFGLPEN (0x2ul) /* RCC APB4LPENR: SYSCFGLPEN */
|
||||
#define RCC_APB4LPENR_LPUART1LPEN (0x8ul) /* RCC APB4LPENR: LPUART1LPEN */
|
||||
#define RCC_APB4LPENR_SPI6LPEN (0x20ul) /* RCC APB4LPENR: SPI6LPEN */
|
||||
#define RCC_APB4LPENR_I2C4LPEN (0x80ul) /* RCC APB4LPENR: I2C4LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM2LPEN (0x200ul) /* RCC APB4LPENR: LPTIM2LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM3LPEN (0x400ul) /* RCC APB4LPENR: LPTIM3LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM4LPEN (0x800ul) /* RCC APB4LPENR: LPTIM4LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM5LPEN (0x1000ul) /* RCC APB4LPENR: LPTIM5LPEN */
|
||||
#define RCC_APB4LPENR_COMP12LPEN (0x4000ul) /* RCC APB4LPENR: COMP12LPEN */
|
||||
#define RCC_APB4LPENR_VREFLPEN (0x8000ul) /* RCC APB4LPENR: VREFLPEN */
|
||||
#define RCC_APB4LPENR_RTCAPBLPEN (0x10000ul) /* RCC APB4LPENR: RTCAPBLPEN */
|
||||
#define RCC_APB4LPENR_SAI4LPEN (0x200000ul) /* RCC APB4LPENR: SAI4LPEN */
|
||||
#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */
|
||||
#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */
|
||||
#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */
|
||||
#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */
|
||||
#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */
|
||||
#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */
|
||||
#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */
|
||||
#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */
|
||||
#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_RCC_H */
|
||||
|
||||
@@ -0,0 +1,144 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_otg.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_OTG_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32_OTG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_otg.h"
|
||||
|
||||
#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32H7_OTGFS)
|
||||
# define STM32_IRQ_OTG STM32_IRQ_OTGFS
|
||||
# define STM32_OTG_BASE STM32_OTGFS_BASE /* OTG FS */
|
||||
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
|
||||
# define GPIO_OTG_DM GPIO_OTGFS_DM
|
||||
# define GPIO_OTG_DP GPIO_OTGFS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGFS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGFS_SOF
|
||||
# define STM32_OTG_FIFO_SIZE 4096
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H7_OTGHS)
|
||||
# define STM32_IRQ_OTG STM32_IRQ_OTGHS
|
||||
# define STM32_OTG_BASE STM32_OTGHS_BASE /* OTG HS/FS */
|
||||
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
|
||||
# define GPIO_OTG_DM GPIO_OTGHS_DM
|
||||
# define GPIO_OTG_DP GPIO_OTGHS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGHS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGHS_SOF
|
||||
# define STM32_OTG_FIFO_SIZE 4096
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_otgfshost_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize USB host device controller hardware.
|
||||
*
|
||||
* Input Parameters:
|
||||
* controller -- If the device supports more than USB host controller, then
|
||||
* this identifies which controller is being initializeed. Normally, this
|
||||
* is just zero.
|
||||
*
|
||||
* Returned Value:
|
||||
* And instance of the USB host interface. The controlling task should
|
||||
* use this interface to (1) call the wait() method to wait for a device
|
||||
* to be connected, and (2) call the enumerate() method to bind the device
|
||||
* to a class driver.
|
||||
*
|
||||
* Assumptions:
|
||||
* - This function should called in the initialization sequence in order
|
||||
* to initialize the USB device functionality.
|
||||
* - Class drivers should be initialized prior to calling this function.
|
||||
* Otherwise, there is a race condition if the device is already connected.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
struct usbhost_connection_s;
|
||||
FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver
|
||||
* is used. This function is called whenever the USB enters or leaves suspend
|
||||
* mode. This is an opportunity for the board logic to shutdown clocks, power,
|
||||
* etc. while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_STM32H7_OTGFS */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_OTG_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,202 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_usbhost.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H
|
||||
|
||||
/* STM32 USB OTG Host Driver Support
|
||||
*
|
||||
* Pre-requisites
|
||||
*
|
||||
* CONFIG_USBHOST - Enable general USB host support
|
||||
* CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block
|
||||
* or
|
||||
* CONFIG_STM32H7_OTGHS - Enable the STM32 USB OTG HS block
|
||||
* CONFIG_STM32H7_SYSCFG - Needed
|
||||
*
|
||||
* Options:
|
||||
*
|
||||
* CONFIG_STM32H7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
* Default 128 (512 bytes)
|
||||
* CONFIG_STM32H7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
* in 32-bit words. Default 96 (384 bytes)
|
||||
* CONFIG_STM32H7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
* words. Default 96 (384 bytes)
|
||||
* CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
* want to do that?
|
||||
*
|
||||
* CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
* debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
*/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#if (defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)) && \
|
||||
defined(CONFIG_USBHOST)
|
||||
|
||||
|
||||
#ifdef HAVE_USBHOST_TRACE
|
||||
enum usbhost_trace1codes_e
|
||||
{
|
||||
__TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */
|
||||
|
||||
OTG_TRACE1_DEVDISCONN, /* OTG ERROR: Host Port Device disconnected */
|
||||
OTG_TRACE1_IRQATTACH, /* OTG ERROR: Failed to attach IRQ */
|
||||
OTG_TRACE1_TRNSFRFAILED, /* OTG ERROR: Host Port Transfer Failed */
|
||||
OTG_TRACE1_SENDSETUP, /* OTG ERROR: sendsetup() failed with: */
|
||||
OTG_TRACE1_SENDDATA, /* OTG ERROR: senddata() failed with: */
|
||||
OTG_TRACE1_RECVDATA, /* OTG ERROR: recvdata() failed with: */
|
||||
|
||||
#ifdef HAVE_USBHOST_TRACE_VERBOSE
|
||||
|
||||
OTG_VTRACE1_CONNECTED, /* OTG Host Port connected */
|
||||
OTG_VTRACE1_DISCONNECTED, /* OTG Host Port disconnected */
|
||||
OTG_VTRACE1_GINT, /* OTG Handling Interrupt. Entry Point */
|
||||
OTG_VTRACE1_GINT_SOF, /* OTG Handle the start of frame interrupt */
|
||||
OTG_VTRACE1_GINT_RXFLVL, /* OTG Handle the RxFIFO non-empty interrupt */
|
||||
OTG_VTRACE1_GINT_NPTXFE, /* OTG Handle the non-periodic TxFIFO empty interrupt */
|
||||
OTG_VTRACE1_GINT_PTXFE, /* OTG Handle the periodic TxFIFO empty interrupt */
|
||||
OTG_VTRACE1_GINT_HC, /* OTG Handle the host channels interrupt */
|
||||
OTG_VTRACE1_GINT_HPRT, /* OTG Handle the host port interrupt */
|
||||
OTG_VTRACE1_GINT_HPRT_POCCHNG, /* OTG HPRT: Port Over-Current Change*/
|
||||
OTG_VTRACE1_GINT_HPRT_PCDET, /* OTG HPRT: Port Connect Detect */
|
||||
OTG_VTRACE1_GINT_HPRT_PENCHNG, /* OTG HPRT: Port Enable Changed */
|
||||
OTG_VTRACE1_GINT_HPRT_LSDEV, /* OTG HPRT: Low Speed Device Connected */
|
||||
OTG_VTRACE1_GINT_HPRT_FSDEV, /* OTG HPRT: Full Speed Device Connected */
|
||||
OTG_VTRACE1_GINT_HPRT_LSFSSW, /* OTG HPRT: Host Switch: LS -> FS */
|
||||
OTG_VTRACE1_GINT_HPRT_FSLSSW, /* OTG HPRT: Host Switch: FS -> LS */
|
||||
OTG_VTRACE1_GINT_DISC, /* OTG Handle the disconnect detected interrupt */
|
||||
OTG_VTRACE1_GINT_IPXFR, /* OTG Handle the incomplete periodic transfer */
|
||||
|
||||
#endif
|
||||
|
||||
__TRACE1_NSTRINGS, /* Separates the format 1 from the format 2 strings */
|
||||
|
||||
OTG_TRACE2_CLIP, /* OTG CLIP: chidx: buflen: */
|
||||
|
||||
#ifdef HAVE_USBHOST_TRACE_VERBOSE
|
||||
|
||||
OTG_VTRACE2_CHANWAKEUP_IN, /* OTG IN Channel wake up with result */
|
||||
OTG_VTRACE2_CHANWAKEUP_OUT, /* OTG OUT Channel wake up with result */
|
||||
OTG_VTRACE2_CTRLIN, /* OTG CTRLIN */
|
||||
OTG_VTRACE2_CTRLOUT, /* OTG CTRLOUT */
|
||||
OTG_VTRACE2_INTRIN, /* OTG INTRIN */
|
||||
OTG_VTRACE2_INTROUT, /* OTG INTROUT */
|
||||
OTG_VTRACE2_BULKIN, /* OTG BULKIN */
|
||||
OTG_VTRACE2_BULKOUT, /* OTG BULKOUT */
|
||||
OTG_VTRACE2_ISOCIN, /* OTG ISOCIN */
|
||||
OTG_VTRACE2_ISOCOUT, /* OTG ISOCOUT */
|
||||
OTG_VTRACE2_STARTTRANSFER, /* OTG EP buflen */
|
||||
OTG_VTRACE2_CHANCONF_CTRL_IN,
|
||||
OTG_VTRACE2_CHANCONF_CTRL_OUT,
|
||||
OTG_VTRACE2_CHANCONF_INTR_IN,
|
||||
OTG_VTRACE2_CHANCONF_INTR_OUT,
|
||||
OTG_VTRACE2_CHANCONF_BULK_IN,
|
||||
OTG_VTRACE2_CHANCONF_BULK_OUT,
|
||||
OTG_VTRACE2_CHANCONF_ISOC_IN,
|
||||
OTG_VTRACE2_CHANCONF_ISOC_OUT,
|
||||
OTG_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */
|
||||
|
||||
#endif
|
||||
|
||||
__TRACE2_NSTRINGS /* Total number of enumeration values */
|
||||
};
|
||||
|
||||
# define TRACE1_FIRST ((int)__TRACE1_BASEVALUE + 1)
|
||||
# define TRACE1_INDEX(id) ((int)(id) - TRACE1_FIRST)
|
||||
# define TRACE1_NSTRINGS TRACE1_INDEX(__TRACE1_NSTRINGS)
|
||||
|
||||
# define TRACE2_FIRST ((int)__TRACE1_NSTRINGS + 1)
|
||||
# define TRACE2_INDEX(id) ((int)(id) - TRACE2_FIRST)
|
||||
# define TRACE2_NSTRINGS TRACE2_INDEX(__TRACE2_NSTRINGS)
|
||||
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/***********************************************************************************
|
||||
* Name: stm32_usbhost_vbusdrive
|
||||
*
|
||||
* Description:
|
||||
* Enable/disable driving of VBUS 5V output. This function must be provided be
|
||||
* each platform that implements the STM32 OTG FS host interface
|
||||
*
|
||||
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
|
||||
* or, if 5 V are available on the application board, a basic power switch, must
|
||||
* be added externally to drive the 5 V VBUS line. The external charge pump can
|
||||
* be driven by any GPIO output. When the application decides to power on VBUS
|
||||
* using the chosen GPIO, it must also set the port power bit in the host port
|
||||
* control and status register (PPWR bit in OTG_FS_HPRT).
|
||||
*
|
||||
* "The application uses this field to control power to this port, and the core
|
||||
* clears this bit on an overcurrent condition."
|
||||
*
|
||||
* Input Parameters:
|
||||
* iface - For future growth to handle multiple USB host interface. Should be zero.
|
||||
* enable - true: enable VBUS power; false: disable VBUS power
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
***********************************************************************************/
|
||||
|
||||
void stm32_usbhost_vbusdrive(int iface, bool enable);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* (CONFIG_STM32H7_OTGFS || CONFIG_STM32H7_OTGHS) && CONFIG_USBHOST */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H */
|
||||
@@ -152,6 +152,24 @@ static inline void rcc_enableahb1(void)
|
||||
regval |= RCC_AHB1ENR_DMA2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_OTGFS
|
||||
/* USB OTG FS clock enable */
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGFSEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_OTGHS
|
||||
#ifdef BOARD_ENABLE_USBOTG_HSULPI
|
||||
/* Enable clocking for USB OTG HS and external PHY */
|
||||
|
||||
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
|
||||
#else
|
||||
/* Enable only clocking for USB OTG HS */
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
@@ -424,9 +442,11 @@ static inline void rcc_enableapb4(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB4ENR);
|
||||
|
||||
#ifdef CONFIG_STM32H7_SYSCFG
|
||||
/* System configuration controller clock enable */
|
||||
|
||||
regval |= RCC_APB4ENR_SYSCFGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_I2C4
|
||||
/* I2C4 clock enable */
|
||||
@@ -509,6 +529,21 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#define CONFIG_STM32H7_HSI48
|
||||
#ifdef CONFIG_STM32H7_HSI48
|
||||
/* Enable HSI48 */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSI48ON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI48 is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSI48RDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check for a timeout. If this timeout occurs, then we are hosed. We
|
||||
* have no real back-up plan, although the following logic makes it look
|
||||
* as though we do.
|
||||
@@ -693,6 +728,15 @@ static void stm32_stdclockconfig(void)
|
||||
putreg32(regval, STM32_RCC_D3CCIPR);
|
||||
#endif
|
||||
|
||||
/* Configure USB source clock */
|
||||
|
||||
#if defined(STM32_RCC_D2CCIP2R_USBSRC)
|
||||
regval = getreg32(STM32_RCC_D2CCIP2R);
|
||||
regval &= ~RCC_D2CCIP2R_USBSEL_MASK;
|
||||
regval |= STM32_RCC_D2CCIP2R_USBSRC;
|
||||
putreg32(regval, STM32_RCC_D2CCIP2R);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
|
||||
@@ -48,6 +48,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += stm32_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32_OTGFS),y)
|
||||
CSRCS += stm32_usb.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += stm32_appinitialize.c
|
||||
endif
|
||||
|
||||
@@ -84,6 +84,29 @@
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
|
||||
|
||||
/* USB OTG FS
|
||||
*
|
||||
* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
|
||||
* PG6 OTG_FS_PowerSwitchOn
|
||||
* PG7 OTG_FS_Overcurrent
|
||||
*/
|
||||
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
|
||||
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
|
||||
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
|
||||
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \
|
||||
GPIO_SPEED_100MHz|GPIO_PUSHPULL| \
|
||||
GPIO_PORTG|GPIO_PIN7)
|
||||
|
||||
#else
|
||||
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
|
||||
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
/* PWM */
|
||||
|
||||
#define NUCLEOF207ZG_PWMTIMER 1
|
||||
|
||||
@@ -69,6 +69,12 @@ void stm32_boardinitialize(void)
|
||||
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST)
|
||||
/* Initialize USB */
|
||||
|
||||
stm32_usbinitialize();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@@ -92,6 +92,18 @@ int stm32_bringup(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE)
|
||||
/* Initialize CDCACM */
|
||||
|
||||
syslog(LOG_INFO, "Initialize CDCACM device\n");
|
||||
|
||||
ret = cdcacm_initialize(0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,331 @@
|
||||
/************************************************************************************
|
||||
* configs/nucleo-f207zg/src/stm32_usb.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <sched.h>
|
||||
#include <errno.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/kthread.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <nuttx/usb/usbhost.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_otgfs.h"
|
||||
#include "nucleo-f207zg.h"
|
||||
|
||||
#ifdef CONFIG_STM32_OTGFS
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
|
||||
# define HAVE_USB 1
|
||||
#else
|
||||
# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
|
||||
# undef HAVE_USB
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_NUCLEOF207ZG_USBHOST_PRIO
|
||||
# define CONFIG_NUCLEOF207ZG_USBHOST_PRIO 100
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE
|
||||
# define CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE 1024
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
static struct usbhost_connection_s *g_usbconn;
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: usbhost_waiter
|
||||
*
|
||||
* Description:
|
||||
* Wait for USB devices to be connected.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
static int usbhost_waiter(int argc, char *argv[])
|
||||
{
|
||||
struct usbhost_hubport_s *hport;
|
||||
|
||||
uinfo("Running\n");
|
||||
for (;;)
|
||||
{
|
||||
/* Wait for the device to change state */
|
||||
|
||||
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
|
||||
uinfo("%s\n", hport->connected ? "connected" : "disconnected");
|
||||
|
||||
/* Did we just become connected? */
|
||||
|
||||
if (hport->connected)
|
||||
{
|
||||
/* Yes.. enumerate the newly connected device */
|
||||
|
||||
(void)CONN_ENUMERATE(g_usbconn, hport);
|
||||
}
|
||||
}
|
||||
|
||||
/* Keep the compiler from complaining */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_usbinitialize very early in inialization to setup USB-related
|
||||
* GPIO pins for the nucleo-144 board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_usbinitialize(void)
|
||||
{
|
||||
/* The OTG FS has an internal soft pull-up. No GPIO configuration is required */
|
||||
|
||||
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
|
||||
|
||||
#ifdef CONFIG_STM32_OTGFS
|
||||
stm32_configgpio(GPIO_OTGFS_VBUS);
|
||||
stm32_configgpio(GPIO_OTGFS_PWRON);
|
||||
stm32_configgpio(GPIO_OTGFS_OVER);
|
||||
#endif
|
||||
}
|
||||
|
||||
/***********************************************************************************
|
||||
* Name: stm32_usbhost_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called at application startup time to initialize the USB host functionality.
|
||||
* This function will start a thread that will monitor for device
|
||||
* connection/disconnection events.
|
||||
*
|
||||
***********************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
int stm32_usbhost_initialize(void)
|
||||
{
|
||||
int pid;
|
||||
#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \
|
||||
defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE)
|
||||
int ret;
|
||||
#endif
|
||||
|
||||
/* First, register all of the class drivers needed to support the drivers
|
||||
* that we care about:
|
||||
*/
|
||||
|
||||
uinfo("Register class drivers\n");
|
||||
|
||||
#ifdef CONFIG_USBHOST_HUB
|
||||
/* Initialize USB hub class support */
|
||||
|
||||
ret = usbhost_hub_initialize();
|
||||
if (ret < 0)
|
||||
{
|
||||
uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_MSC
|
||||
/* Register the USB mass storage class class */
|
||||
|
||||
ret = usbhost_msc_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_CDCACM
|
||||
/* Register the CDC/ACM serial class */
|
||||
|
||||
ret = usbhost_cdcacm_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_HIDKBD
|
||||
/* Initialize the HID keyboard class */
|
||||
|
||||
ret = usbhost_kbdinit();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the HID keyboard class\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_HIDMOUSE
|
||||
/* Initialize the HID mouse class */
|
||||
|
||||
ret = usbhost_mouse_init();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the HID mouse class\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Then get an instance of the USB host interface */
|
||||
|
||||
uinfo("Initialize USB host\n");
|
||||
g_usbconn = stm32_otgfshost_initialize(0);
|
||||
if (g_usbconn)
|
||||
{
|
||||
/* Start a thread to handle device connection. */
|
||||
|
||||
uinfo("Start usbhost_waiter\n");
|
||||
|
||||
pid = kthread_create("usbhost", CONFIG_NUCLEOF207ZG_USBHOST_PRIO,
|
||||
CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE,
|
||||
(main_t)usbhost_waiter, (FAR char * const *)NULL);
|
||||
return pid < 0 ? -ENOEXEC : OK;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************************
|
||||
* Name: stm32_usbhost_vbusdrive
|
||||
*
|
||||
* Description:
|
||||
* Enable/disable driving of VBUS 5V output. This function must be provided be
|
||||
* each platform that implements the STM32 OTG FS host interface
|
||||
*
|
||||
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
|
||||
* or, if 5 V are available on the application board, a basic power switch, must
|
||||
* be added externally to drive the 5 V VBUS line. The external charge pump can
|
||||
* be driven by any GPIO output. When the application decides to power on VBUS
|
||||
* using the chosen GPIO, it must also set the port power bit in the host port
|
||||
* control and status register (PPWR bit in OTG_FS_HPRT).
|
||||
*
|
||||
* "The application uses this field to control power to this port, and the core
|
||||
* clears this bit on an overcurrent condition."
|
||||
*
|
||||
* Input Parameters:
|
||||
* iface - For future growth to handle multiple USB host interface. Should be zero.
|
||||
* enable - true: enable VBUS power; false: disable VBUS power
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
***********************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
void stm32_usbhost_vbusdrive(int iface, bool enable)
|
||||
{
|
||||
DEBUGASSERT(iface == 0);
|
||||
|
||||
/* Set the Power Switch by driving the active low enable pin */
|
||||
|
||||
stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_setup_overcurrent
|
||||
*
|
||||
* Description:
|
||||
* Setup to receive an interrupt-level callback if an overcurrent condition is
|
||||
* detected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* handler - New overcurrent interrupt handler
|
||||
* arg - The argument provided for the interrupt handler
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
|
||||
* to indicate the nature of the failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
int stm32_setup_overcurrent(xcpt_t handler, void *arg)
|
||||
{
|
||||
return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
|
||||
* used. This function is called whenever the USB enters or leaves suspend mode.
|
||||
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
||||
* while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_OTGFS */
|
||||
@@ -111,9 +111,9 @@
|
||||
*
|
||||
* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
|
||||
*
|
||||
* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
|
||||
* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
|
||||
* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
|
||||
* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
|
||||
* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
|
||||
* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
|
||||
@@ -212,7 +212,7 @@
|
||||
|
||||
#define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI
|
||||
|
||||
/* SPI123 clock source - PLL1 */
|
||||
/* SPI123 clock source - PLL1Q */
|
||||
|
||||
#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
|
||||
|
||||
@@ -224,6 +224,10 @@
|
||||
|
||||
#define STM32_RCC_D3CCIP1R_SPI6SRC RCC_D3CCIP1R_SPI6SEL_PCLK4
|
||||
|
||||
/* USB 1 and 2 clock source - HSI48 */
|
||||
|
||||
#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
* ------------ ---------- -----------
|
||||
|
||||
@@ -52,6 +52,10 @@ ifeq ($(CONFIG_STM32H7_SPI),y)
|
||||
CSRCS += stm32_spi.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STM32H7_OTGFS),y)
|
||||
CSRCS += stm32_usb.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SENSORS_LSM6DSL),y)
|
||||
CSRCS += stm32_lsm6dsl.c
|
||||
endif
|
||||
|
||||
@@ -49,6 +49,16 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* procfs File System */
|
||||
|
||||
#ifdef CONFIG_FS_PROCFS
|
||||
# ifdef CONFIG_NSH_PROC_MOUNTPOINT
|
||||
# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
|
||||
# else
|
||||
# define STM32_PROCFS_MOUNTPOINT "/proc"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* LED
|
||||
*
|
||||
@@ -82,6 +92,29 @@
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
/* USB OTG FS
|
||||
*
|
||||
* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
|
||||
* PG6 OTG_FS_PowerSwitchOn
|
||||
* PG7 OTG_FS_Overcurrent
|
||||
*/
|
||||
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
|
||||
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
|
||||
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
|
||||
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \
|
||||
GPIO_SPEED_100MHz|GPIO_PUSHPULL| \
|
||||
GPIO_PORTG|GPIO_PIN7)
|
||||
|
||||
#else
|
||||
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
|
||||
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
/* X-NUCLEO IKS01A2 */
|
||||
|
||||
#define GPIO_LPS22HB_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN10)
|
||||
@@ -146,6 +179,18 @@ void stm32_spidev_initialize(void);
|
||||
int stm32_adc_setup(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_usbinitialize very early in inialization to setup USB-related
|
||||
* GPIO pins for the nucleo-144 board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H7_OTGFS
|
||||
void stm32_usbinitialize(void);
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: stm32_lsm6dsl_initialize
|
||||
|
||||
@@ -70,6 +70,12 @@ void stm32_boardinitialize(void)
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST)
|
||||
/* Initialize USB */
|
||||
|
||||
stm32_usbinitialize();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SPI
|
||||
/* Configure SPI chip selects */
|
||||
|
||||
|
||||
@@ -138,5 +138,17 @@ int stm32_bringup(void)
|
||||
}
|
||||
#endif /* CONFIG_WL_NRF24L01 */
|
||||
|
||||
#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE)
|
||||
/* Initialize CDCACM */
|
||||
|
||||
syslog(LOG_INFO, "Initialize CDCACM device\n");
|
||||
|
||||
ret = cdcacm_initialize(0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret);
|
||||
}
|
||||
#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,331 @@
|
||||
/************************************************************************************
|
||||
* configs/nucleo-h743zi/src/stm32_usb.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <sched.h>
|
||||
#include <errno.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/kthread.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <nuttx/usb/usbhost.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_otg.h"
|
||||
#include "nucleo-h743zi.h"
|
||||
|
||||
#ifdef CONFIG_STM32H7_OTGFS
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
|
||||
# define HAVE_USB 1
|
||||
#else
|
||||
# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
|
||||
# undef HAVE_USB
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_NUCLEOH743ZI_USBHOST_PRIO
|
||||
# define CONFIG_NUCLEOH743ZI_USBHOST_PRIO 100
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_NUCLEOH743ZI_USBHOST_STACKSIZE
|
||||
# define CONFIG_NUCLEOH743ZI_USBHOST_STACKSIZE 1024
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
static struct usbhost_connection_s *g_usbconn;
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: usbhost_waiter
|
||||
*
|
||||
* Description:
|
||||
* Wait for USB devices to be connected.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
static int usbhost_waiter(int argc, char *argv[])
|
||||
{
|
||||
struct usbhost_hubport_s *hport;
|
||||
|
||||
uinfo("Running\n");
|
||||
for (;;)
|
||||
{
|
||||
/* Wait for the device to change state */
|
||||
|
||||
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
|
||||
uinfo("%s\n", hport->connected ? "connected" : "disconnected");
|
||||
|
||||
/* Did we just become connected? */
|
||||
|
||||
if (hport->connected)
|
||||
{
|
||||
/* Yes.. enumerate the newly connected device */
|
||||
|
||||
(void)CONN_ENUMERATE(g_usbconn, hport);
|
||||
}
|
||||
}
|
||||
|
||||
/* Keep the compiler from complaining */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_usbinitialize very early in inialization to setup USB-related
|
||||
* GPIO pins for the nucleo-144 board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_usbinitialize(void)
|
||||
{
|
||||
/* The OTG FS has an internal soft pull-up. No GPIO configuration is required */
|
||||
|
||||
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
|
||||
|
||||
#ifdef CONFIG_STM32H7_OTGFS
|
||||
stm32_configgpio(GPIO_OTGFS_VBUS);
|
||||
stm32_configgpio(GPIO_OTGFS_PWRON);
|
||||
stm32_configgpio(GPIO_OTGFS_OVER);
|
||||
#endif
|
||||
}
|
||||
|
||||
/***********************************************************************************
|
||||
* Name: stm32_usbhost_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called at application startup time to initialize the USB host functionality.
|
||||
* This function will start a thread that will monitor for device
|
||||
* connection/disconnection events.
|
||||
*
|
||||
***********************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
int stm32_usbhost_initialize(void)
|
||||
{
|
||||
int pid;
|
||||
#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \
|
||||
defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE)
|
||||
int ret;
|
||||
#endif
|
||||
|
||||
/* First, register all of the class drivers needed to support the drivers
|
||||
* that we care about:
|
||||
*/
|
||||
|
||||
uinfo("Register class drivers\n");
|
||||
|
||||
#ifdef CONFIG_USBHOST_HUB
|
||||
/* Initialize USB hub class support */
|
||||
|
||||
ret = usbhost_hub_initialize();
|
||||
if (ret < 0)
|
||||
{
|
||||
uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_MSC
|
||||
/* Register the USB mass storage class class */
|
||||
|
||||
ret = usbhost_msc_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_CDCACM
|
||||
/* Register the CDC/ACM serial class */
|
||||
|
||||
ret = usbhost_cdcacm_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_HIDKBD
|
||||
/* Initialize the HID keyboard class */
|
||||
|
||||
ret = usbhost_kbdinit();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the HID keyboard class\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_HIDMOUSE
|
||||
/* Initialize the HID mouse class */
|
||||
|
||||
ret = usbhost_mouse_init();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the HID mouse class\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Then get an instance of the USB host interface */
|
||||
|
||||
uinfo("Initialize USB host\n");
|
||||
g_usbconn = stm32_otgfshost_initialize(0);
|
||||
if (g_usbconn)
|
||||
{
|
||||
/* Start a thread to handle device connection. */
|
||||
|
||||
uinfo("Start usbhost_waiter\n");
|
||||
|
||||
pid = kthread_create("usbhost", CONFIG_NUCLEOH743ZI_USBHOST_PRIO,
|
||||
CONFIG_NUCLEOH743ZI_USBHOST_STACKSIZE,
|
||||
(main_t)usbhost_waiter, (FAR char * const *)NULL);
|
||||
return pid < 0 ? -ENOEXEC : OK;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***********************************************************************************
|
||||
* Name: stm32_usbhost_vbusdrive
|
||||
*
|
||||
* Description:
|
||||
* Enable/disable driving of VBUS 5V output. This function must be provided be
|
||||
* each platform that implements the STM32 OTG FS host interface
|
||||
*
|
||||
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
|
||||
* or, if 5 V are available on the application board, a basic power switch, must
|
||||
* be added externally to drive the 5 V VBUS line. The external charge pump can
|
||||
* be driven by any GPIO output. When the application decides to power on VBUS
|
||||
* using the chosen GPIO, it must also set the port power bit in the host port
|
||||
* control and status register (PPWR bit in OTG_FS_HPRT).
|
||||
*
|
||||
* "The application uses this field to control power to this port, and the core
|
||||
* clears this bit on an overcurrent condition."
|
||||
*
|
||||
* Input Parameters:
|
||||
* iface - For future growth to handle multiple USB host interface. Should be zero.
|
||||
* enable - true: enable VBUS power; false: disable VBUS power
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
***********************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
void stm32_usbhost_vbusdrive(int iface, bool enable)
|
||||
{
|
||||
DEBUGASSERT(iface == 0);
|
||||
|
||||
/* Set the Power Switch by driving the active low enable pin */
|
||||
|
||||
stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_setup_overcurrent
|
||||
*
|
||||
* Description:
|
||||
* Setup to receive an interrupt-level callback if an overcurrent condition is
|
||||
* detected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* handler - New overcurrent interrupt handler
|
||||
* arg - The argument provided for the interrupt handler
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
|
||||
* to indicate the nature of the failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
int stm32_setup_overcurrent(xcpt_t handler, void *arg)
|
||||
{
|
||||
return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
|
||||
* used. This function is called whenever the USB enters or leaves suspend mode.
|
||||
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
||||
* while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_OTGFS */
|
||||
@@ -62,7 +62,7 @@ CONFIG_UART0_SERIAL_CONSOLE=y
|
||||
CONFIG_USBDEV=y
|
||||
CONFIG_USBDEV_BUSPOWERED=y
|
||||
CONFIG_USBDEV_TRACE=y
|
||||
CONFIG_USBDEV_TRACE_INITIALIDSET=y
|
||||
CONFIG_USBDEV_TRACE_INITIALIDSET=0xff
|
||||
CONFIG_USBMONITOR=y
|
||||
CONFIG_USBMONITOR_TRACECLASS=y
|
||||
CONFIG_USBMONITOR_TRACECONTROLLER=y
|
||||
|
||||
@@ -119,7 +119,7 @@ config USBDEV_TRACE_STRINGS
|
||||
#endif
|
||||
|
||||
config USBDEV_TRACE_INITIALIDSET
|
||||
bool "Initial enable bits"
|
||||
int "Initial enable bits"
|
||||
default 0
|
||||
---help---
|
||||
This is the set of initial USB features that are enabled at boot
|
||||
|
||||
Reference in New Issue
Block a user