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lpc2378 port contributed by Rommel Marcelo

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2579 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2010-04-09 01:14:24 +00:00
parent 9c671715e2
commit 2bd1d18f1a
19 changed files with 5021 additions and 2 deletions
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ChangeLog
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@@ -1082,4 +1082,7 @@
* arch/arm/src/sam3u/sam3u_hsmci.c - SD memory card support for AT90SAM3U
(incomplete on initial checkin).
* drivers/usbdev - Several important fixes to the USB mass storage driver
submitted by David Hewson.
submitted by David Hewson.
* configs/olimex-lpc2378, arch/arm/include/lpc2378, and arch/arm/src/lpc2378 -
Basic port of the NXP 2378 on the Olimex board contributed by
Rommel Marcelo.
Documentation/NuttX.html
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<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: April 4, 2010</p>
<p>Last Updated: April 8, 2010</p>
</td>
</tr>
</table>
@@ -1664,6 +1664,10 @@ nuttx-5.3 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
* arch/arm/src/sam3u/sam3u_hsmci.c - SD memory card support for AT90SAM3U
(incomplete on initial checkin).
* drivers/usbdev - Several important fixes to the USB mass storage driver
submitted by David Hewson.
* configs/olimex-lpc2378, arch/arm/include/lpc2378, and arch/arm/src/lpc2378 -
Basic port of the NXP 2378 on the Olimex board contributed by
Rommel Marcelo.
pascal-2.1 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
arch/arm/src/lpc2378/Make.defs
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##############################################################################
# lpc23xx/Make.defs
#
# Copyright (C) 2010 Rommel Marcelo. All rights reserved.
# Author: Rommel Marcelo
#
# This file is part of the NuttX RTOS and based on the lpc2148 port:
#
# Copyright (C) 2010 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
##############################################################################
HEAD_ASRC = lpc23xx_head.S
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c \
up_exit.c up_idle.c up_initialize.c up_initialstate.c \
up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
up_releasestack.c up_reprioritizertr.c up_syscall.c up_unblocktask.c \
up_undefinedinsn.c up_usestack.c up_lowputs.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
endif
CHIP_ASRCS = lpc23xx_lowputc.S
CHIP_CSRCS = lpc23xx_pllsetup.c lpc23xx_decodeirq.c lpc23xx_irq.c lpc23xx_timerisr.c \
lpc23xx_serial.c lpc23xx_io.c
ifeq ($(CONFIG_USBDEV),y)
#CHIP_CSRCS += lpc23xx_usbdev.c
endif
arch/arm/src/lpc2378/chip.h
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arch/arm/src/lpc2378/internal.h
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/****************************************************************************************************
* arch/arm/src/lpc2378/chip.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_INTERNAL_H
#define _ARCH_ARM_SRC_LPC2378_INTERNAL_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include "up_internal.h"
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
//~ #define CONFIG_VECTORED_INTERRUPTS
/****************************************************************************************************
* Global Function Prototypes
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_LEDS
extern void up_statledoff(void);
extern void up_statledon(void);
#endif
#endif
#endif /* _ARCH_ARM_SRC_LPC2378_INTERNAL_H */
arch/arm/src/lpc2378/lpc23xx_decodeirq.c
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/********************************************************************************
* arch/arm/src/lpc2378/lpc23xx_decodeirq.c
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************/
/********************************************************************************
* Included Files
********************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "os_internal.h"
#include "internal.h"
#include "lpc23xx_vic.h"
/********************************************************************************
* Definitions
********************************************************************************/
/********************************************************************************
* Private Types
********************************************************************************/
/********************************************************************************
* Public Data
********************************************************************************/
/********************************************************************************
* Private Data
********************************************************************************/
/********************************************************************************
* Private Functions
********************************************************************************/
/********************************************************************************
* Public Funstions
********************************************************************************/
/********************************************************************************
* up_decodeirq() and/or lpc23xx_decodeirq()
*
* Description:
* The vectored interrupt controller (VIC) takes 32 interrupt request inputs
* and programmatically assigns them into 2 categories: FIQ, vectored IRQ.
*
* - FIQs have the highest priority. There is a single FIQ vector, but multiple
* interrupt sources can be ORed to this FIQ vector.
*
* - Vectored IRQs have the middle priority. Any of the 32 interrupt sources
* can be assigned to vectored IRQs.
*
* - Non-vectored IRQs have the lowest priority.
*
* The general flow of IRQ processing is to simply read the VICAddress
* and jump to the address of the vector provided in the register. The VIC will
* provide the address of the highest priority vectored IRQ. If a non-vectored
* IRQ is requesting, the address of a default handler is provided.
*
********************************************************************************/
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
#else
static void lpc23xx_decodeirq( uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
lib_lowprintf("Unexpected IRQ\n");
current_regs = regs;
PANIC(OSERR_ERREXCEPTION);
#else
/* Check which IRQ fires */
uint32_t irqbits = vic_getreg(VIC_IRQSTATUS_OFFSET) & 0xFFFFFFFF;
unsigned int irq;
for (irq = 0; irq < NR_IRQS; irq++)
{
if( irqbits & (uint32_t)(1<<irq) ) break;
}
/* Verify that the resulting IRQ number is valid */
if (irq < NR_IRQS) /* redundant check ?? */
{
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
*/
DEBUGASSERT(current_regs == NULL);
current_regs = regs;
/* Mask and acknowledge the interrupt */
up_maskack_irq(irq);
/* Deliver the IRQ */
irq_dispatch(irq, regs);
/* Indicate that we are no longer in an interrupt handler */
current_regs = NULL;
}
#endif
}
#ifdef CONFIG_VECTORED_INTERRUPTS
void up_decodeirq(uint32_t *regs)
{
vic_vector_t vector = (vic_vector_t)vic_getreg(VIC_ADDRESS_OFFSET);
/* Mask and acknowledge the interrupt */
up_maskack_irq(irq);
/* Valid Interrupt */
if(vector != NULL)
(vector)(regs);
}
#endif
arch/arm/src/lpc2378/lpc23xx_gpio.h
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/************************************************************************************
* arch/arm/src/lpc2378/lpc231x_gpio.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#define _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include "chip.h"
/************************************************************************************
* Definitions
************************************************************************************/
#define io_getreg8(o) getreg8(LPC23XX_FIO_BASE+(o))
#define io_getreg(r) getreg32(LPC23XX_FIO_BASE+ (r))
#define dir_getreg8(o) getreg8(LPC23XX_FIO_BASE+(o))
#define dir_getreg(r) getreg32(LPC23XX_FIO_BASE+ (r))
#define dir_putreg8(v,o) putreg8((v), LPC23XX_FIO_BASE+(o))
#define dir_putreg(v,r) putreg32((v),LPC23XX_FIO_BASE+ (r))
#define fio_putreg8(v,o) putreg8((v), LPC23XX_FIO_BASE+(o))
#define fio_getreg8(o) getreg8(LPC23XX_FIO_BASE+(o))
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
arch/arm/src/lpc2378/lpc23xx_head.S
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/****************************************************************************
* arch/arm/src/arm/lpc2378/lpc23xx_head.S
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "arm.h"
#include "internal.h"
#include "up_arch.h"
#include "lpc23xx_uart.h"
#include "lpc23xx_scb.h"
#include "lpc23xx_pinsel.h"
/****************************************************************************
* Macros
****************************************************************************/
/* Print a character on the UART to show boot status. This macro will
* modify r0, r1, r2 and r14
*/
#ifdef CONFIG_DEBUG
.macro showprogress, code
mov r0, #\code
bl up_lowputc
.endm
#else
.macro showprogress, code
.endm
#endif
/*****************************************************************************
* Text
*****************************************************************************/
.text
/*****************************************************************************
* Name: _vector_table
*
* Description:
* Interrrupt vector table. This must be located at the beginning
* of the memory space (at CONFIG_CODE_BASE). The first entry in
* the vector table is the reset vector and this is the code that
* will execute whn the processor is reset.
*
*****************************************************************************/
.globl _vector_table
.type _vector_table, %function
_vector_table:
ldr pc, .Lresethandler /* 0x00: Reset */
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
ldr pc, .Lswihandler /* 0x08: Software interrupt */
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
.long 0xB8A06F58 /* 0x14: Vector checksum */
ldr pc, .Lirqhandler /* 0x18: IRQ */
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
.globl __start
.globl up_vectorundefinsn
.globl up_vectorswi
.globl up_vectorprefetch
.globl up_vectordata
.globl up_vectorirq
.globl up_vectorfiq
.Lresethandler:
.long __start
.Lundefinedhandler:
.long up_vectorundefinsn
.Lswihandler:
.long up_vectorswi
.Lprefetchaborthandler:
.long up_vectorprefetch
.Ldataaborthandler:
.long up_vectordata
.Lirqhandler:
.long up_vectorirq
.Lfiqhandler:
.long up_vectorfiq
.size _vector_table, . - _vector_table
/****************************************************************************
* OS Entry Point
****************************************************************************/
/* We assume the bootloader has already initialized most of the h/w for
* us and that only leaves us having to do some os specific things
* below.
*/
.text
.globl __start
.type __start, #function
__start:
/* Call lowlevel init C-function */
.extern ConfigurePLL
ldr r0, =ConfigurePLL
mov lr, pc
bx r0
/* First, setup initial processor mode */
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Configure the uart so that we can get debug output as soon
* as possible. Modifies r0, r1, r2, and r14.
*/
bl up_lowsetup
showprogress 'A'
/* Setup system stack (and get the BSS range) */
adr r0, LC0
ldmia r0, {r4, r5, sp}
/* Clear system BSS section (Initialize with 0) */
mov r0, #0
1: cmp r4, r5
strcc r0, [r4], #4
bcc 1b
showprogress 'B'
/* Copy system .data sections to new home in RAM. */
adr r3, LC2
ldmia r3, {r0, r1, r2}
2: ldmia r0!, {r3 - r10}
stmia r1!, {r3 - r10}
cmp r1, r2
blt 2b
/* Perform early serial initialization */
mov fp, #0
#ifdef CONFIG_USE_EARLYSERIALINIT
bl up_earlyserialinit
showprogress 'S'
#endif
showprogress 'C'
showprogress '\n'
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl up_ledinit
#endif
/* Then jump to OS entry */
b os_start
/* Variables:
* _sbss is the start of the BSS region (see ld.script)
* _ebss is the end of the BSS regsion (see ld.script)
* The idle task stack starts at the end of BSS and is
* of size CONFIG_IDLETHREAD_STACKSIZE. The heap continues
* from there until the end of memory. See g_heapbase
* below.
*/
LC0: .long _sbss
.long _ebss
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
LC2: .long _eronly /* Where .data defaults are stored in FLASH */
.long _sdata /* Where .data needs to reside in SDRAM */
.long _edata
.size __start, .-__start
/* This global variable is unsigned long g_heapbase and is
* exported from here only because of its coupling to LCO
* above.
*/
.data
.align 4
.globl g_heapbase
.type g_heapbase, object
g_heapbase:
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE
.size g_heapbase, .-g_heapbase
.end
arch/arm/src/lpc2378/lpc23xx_io.c
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/***********************************************************************
* arch/arm/src/arm/lpc2378/lpc23xx_head.S
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***********************************************************************/
/***********************************************************************
* Included files
***********************************************************************/
#include "up_arch.h"
#include <sys/types.h>
#include "lpc23xx_scb.h"
#include "lpc23xx_pinsel.h"
#include "lpc23xx_uart.h"
#include "lpc23xx_gpio.h"
/***********************************************************************
* Definitions
***********************************************************************/
/******************************************************************************
* Name: IO_Init()
*
* Descriptions: Initialize the target board before running the main()
*
******************************************************************************/
void IO_Init( void )
{
uint32_t regval;
/* Reset all GPIO pins to default */
pinsel_putreg(0, PINSEL0_OFFSET);
pinsel_putreg(0, PINSEL1_OFFSET);
pinsel_putreg(0, PINSEL2_OFFSET);
pinsel_putreg(0, PINSEL3_OFFSET);
pinsel_putreg(0, PINSEL4_OFFSET);
pinsel_putreg(0, PINSEL5_OFFSET);
pinsel_putreg(0, PINSEL6_OFFSET);
pinsel_putreg(0, PINSEL7_OFFSET);
pinsel_putreg(0, PINSEL8_OFFSET);
pinsel_putreg(0, PINSEL9_OFFSET);
pinsel_putreg(0, PINSEL10_OFFSET);
/*
regval = scb_getreg(SCB_PCONP_OFFSET) & \
~(PCSDC | PCUART1 | PCI2C0 | PCSSP1 | PCEMC | );
scb_getreg( regval, SCB_PCONP_OFFSET );
*/
/* Turn off all peripheral power */
scb_putreg( 0, SCB_PCONP_OFFSET );
/* Turn on UART0/2 / Timer0 */
//~ regval = PCUART0 | PCUART2 | PCTIM0 | PCRTC ;
regval = PCUART0 | PCUART2 | PCTIM0 ;
scb_putreg( regval , SCB_PCONP_OFFSET );
/* Status LED P1.19 */
dir_putreg8((1 << 3), FIO1DIR2_OFFSET);
/* other io setup here */
return;
}
arch/arm/src/lpc2378/lpc23xx_irq.c
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/****************************************************************************
* arch/arm/src/lpc2378/lpc23xx_irq.c
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm.h"
#include "chip.h"
#include "up_arch.h"
#include "os_internal.h"
#include "internal.h"
#include "lpc23xx_vic.h"
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
uint32_t *current_regs;
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
int reg;
/* Disable all interrupts. We do this by writing ones to the IntClearEnable
* register.
*/
vic_putreg(0xffffffff, VIC_INTENCLEAR_OFFSET);
/* Select all IRQs, FIQs are not used */
vic_putreg(0, VIC_INTSELECT_OFFSET);
/* Clear priority interrupts */
for (reg = 0; reg < NR_IRQS; reg++)
{
vic_putreg(0, VIC_VECTADDR0_OFFSET + (reg << 2));
vic_putreg(0x0F, VIC_VECTPRIORITY0_OFFSET + (reg << 2));
}
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Enable global ARM interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}
/***********************************************************************
* Name: up_enable_irq_protect
* VIC registers can be accessed in User or privileged mode
***********************************************************************/
static void up_enable_irq_protect(void)
{
//~ uint32_t reg32 = vic_getreg(VIC_PROTECTION_OFFSET);
//~ reg32 &= ~(0xFFFFFFFF);
vic_putreg(0x01, VIC_PROTECTION_OFFSET);
}
/***********************************************************************
* Name: up_disable_irq_protect
* VIC registers can only be accessed in privileged mode
***********************************************************************/
static void up_disable_irq_protect(void)
{
vic_putreg(0, VIC_PROTECTION_OFFSET);
}
/***********************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
***********************************************************************/
void up_disable_irq(int irq)
{
/* Verify that the IRQ number is within range */
if (irq < NR_IRQS)
{
/* Disable the irq by setting the corresponding bit in the VIC
* Interrupt Enable Clear register.
*/
vic_putreg((1 << irq), VIC_INTENCLEAR_OFFSET);
}
}
/***********************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
***********************************************************************/
void up_enable_irq(int irq)
{
/* Verify that the IRQ number is within range */
if (irq < NR_IRQS)
{
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Enable the irq by setting the corresponding bit in the VIC
* Interrupt Enable register.
*/
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}
/****************************************************************************
* Name: up_maskack_irq
*
* Description:
* Mask the IRQ and acknowledge it
*
****************************************************************************/
void up_maskack_irq(int irq)
{
uint32_t reg32;
if ((unsigned)irq < NR_IRQS)
{
/* Mask the IRQ by clearing the associated bit in Software Priority Mask register */
reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
reg32 &= ~(1 << irq);
vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
}
/* Clear interrupt */
vic_putreg((1<<irq), VIC_SOFTINTCLEAR_OFFSET);
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
#endif
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* set interrupt priority
* MOD
****************************************************************************/
int up_prioritize_irq(int irq, int priority)
{
/* The default priority on reset is 16 */
if (irq < NR_IRQS && priority > 0 && priority < 16)
{
int offset = irq << 2;
vic_putreg( priority, VIC_VECTPRIORITY0_OFFSET + offset );
return OK;
}
return -EINVAL;
}
/****************************************************************************
* Name: up_attach_vector
*
* Description:
* Attach a user-supplied handler to a vectored interrupt
*
****************************************************************************/
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_attach_vector(int irq, int vector, vic_vector_t handler)
{
/* Verify that the IRQ number and vector number are within range */
if (irq < NR_IRQS && vector < 32 && handler)
{
int offset = vector << 2;
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Save the vector address */
vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset);
/* Set the interrupt priority */
up_prioritize_irq(irq, vector);
/* Enable the vectored interrupt */
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}
#endif
/****************************************************************************
* Name: up_detach_vector
*
* Description:
* Detach a user-supplied handler from a vectored interrupt
*
****************************************************************************/
#ifdef CONFIG_VECTORED_INTERRUPTS
void up_detach_vector(int vector)
{
/* Verify that the vector number is within range */
if (vector < 32)
{
/* Disable the vectored interrupt */
int offset = vector << 2;
vic_putreg(0, (VIC_VECTADDR0_OFFSET + offset));
}
}
#endif
arch/arm/src/lpc2378/lpc23xx_lowputc.S
Executable
+262
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@@ -0,0 +1,262 @@
/**************************************************************************
* arch/arm/src/lpc2378/lpc23xx_lowputc.S
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/**************************************************************************
* Included Files
**************************************************************************/
#include <nuttx/config.h>
#include "up_internal.h"
#include "up_arch.h"
#include "lpc23xx_pinsel.h"
#include "lpc23xx_scb.h"
#include "lpc23xx_uart.h"
/**************************************************************************
* Private Definitions
**************************************************************************/
@ //-- Pins
@ PINSEL0 |= (0x01<<4) | //-- P0.2 TXD0
@ (0x01<<6); //-- P0.3 RXD0
@PCLKSEL0 |= (0x01 << 6); //-- bit 7:6 =01-> Clock div = 1 for UART0
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define UARTxBASE UART0_BASE_ADDR
# define PINSELECT LPC23XX_PINSEL0
# define UARTxPCLKSEL 0xE01FC1A8
# define PCLKSEL_MASK U0_PCLKSEL_MASK
# define UARTxPINSEL UART0_PINSEL
# define UARTxPINMASK UART0_PINMASK
# define UARTxBAUD CONFIG_UART0_BAUD
# define UARTxBITS CONFIG_UART0_BITS
# define UARTxPARITY CONFIG_UART0_PARITY
# define UARTx2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define UARTxBASE UART1_BASE_ADDR
/* # define PINSELECT LPC23XX_PINSEL1 only Uart0/Uart2 share same Pinsel */
# define UARTxPCLKSEL 0xE01FC1A8
# define PCLKSEL_MASK U1_PCLKSEL_MASK
# define UARTxPINSEL UART1_PINSEL
# define UARTxPINMASK UART1_PINMASK
# define UARTxBAUD CONFIG_UART1_BAUD
# define UARTxBITS CONFIG_UART1_BITS
# define UARTxPARITY CONFIG_UART1_PARITY
# define UARTx2STOP CONFIG_UART1_2STOP
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define UARTxBASE UART2_BASE_ADDR
# define PINSELECT LPC23XX_PINSEL0
# define UARTxPCLKSEL 0xE01FC1AC
# define PCLKSEL_MASK U2_PCLKSEL_MASK
# define UARTxPINSEL UART2_PINSEL
# define UARTxPINMASK UART2_PINMASK
# define UARTxBAUD CONFIG_UART2_BAUD
# define UARTxBITS CONFIG_UART2_BITS
# define UARTxPARITY CONFIG_UART2_PARITY
# define UARTx2STOP CONFIG_UART2_2STOP
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
# define PINSELECT LPC23XX_PINSEL0
# define UARTxBASE UART3_BASE_ADDR
# define UARTxPCLKSEL 0xE01FC1AC
# define PCLKSEL_MASK U2_PCLKSEL_MASK
# define UARTxPINSEL UART3_PINSEL
# define UARTxPINMASK UART3_PINMASK
# define UARTxBAUD CONFIG_UART3_BAUD
# define UARTxBITS CONFIG_UART3_BITS
# define UARTxPARITY CONFIG_UART3_PARITY
# define UARTx2STOP CONFIG_UART3_2STOP
#else
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
#endif
#if UARTxBITS == 5
# define LCR_CHAR LCR_CHAR_5
#elif UARTxBITS == 6
# define LCR_CHAR LCR_CHAR_6
#elif UARTxBITS == 7
# define LCR_CHAR LCR_CHAR_7
#elif UARTxBITS == 8
# define LCR_CHAR LCR_CHAR_8
#else
# error "No CONFIG_UARTn_BITS Setting"
#endif
#if UARTxPARITY == 0
# define LCR_PAR LCR_PAR_NONE
#elif UARTxPARITY == 1
# define LCR_PAR LCR_PAR_ODD
#elif UARTxPARITY == 2
# define LCR_PAR LCR_PAR_EVEN
#elif UARTxPARITY == 3
# define LCR_PAR LCR_PAR_MARK
#elif UARTxPARITY == 4
# define LCR_PAR LCR_PAR_SPACE
#else
# error "No CONFIG_UARTn_PARITY Setting"
#endif
#if UARTx2STOP != 0
# define LCR_STOP LCR_STOP_2
#else
# define LCR_STOP LCR_STOP_1
#endif
#define LCR_VALUE (LCR_CHAR | LCR_PAR | LCR_STOP)
#define FCR_VALUE (FCR_FIFO_TRIG8 | FCR_TX_FIFO_RESET | \
FCR_RX_FIFO_RESET | FCR_FIFO_ENABLE)
@#define MULVAL (12 << 4)
@#define DIVADDVAL 3
/**************************************************************************
* Private Types
**************************************************************************/
/**************************************************************************
* Private Function Prototypes
**************************************************************************/
/**************************************************************************
* Global Variables
**************************************************************************/
/**************************************************************************
* Private Variables
**************************************************************************/
/**************************************************************************
* Private Functions
**************************************************************************/
/**************************************************************************
* Public Functions
**************************************************************************/
/**************************************************************************
* Name: up_lowputc
**************************************************************************/
/* This assembly language version has the advantage that it does not
* require a C stack and uses only r0-r1. Hence it can be used during
* early boot phases.
*/
.text
.global up_lowputc
.type up_lowputc, function
up_lowputc:
/* On entry, r0 holds the character to be printed */
ldr r1, =UARTxBASE
strb r0, [r1, #UART_THR_OFFSET]
/* Wait for the byte to be transferred */
1: ldr r0, [r1, #UART_LSR_OFFSET]
ands r0, #LSR_TEMT /* Transmitter empty */
beq 1b
/* And return */
mov pc, lr
.size up_lowputc, . - up_lowputc
/* This performs basic initialization of the UART. This can be called very
* early in initialization because it does not depend on having a stack. It
* modifies r0-r2 and r14.
*/
.text
.globl up_lowsetup
.type up_lowsetup, function
up_lowsetup:
/* Configure PINSEL0 */
ldr r0, =PINSELECT /* TODO: generalize this for different uart pins */
ldr r1, [r0]
ldr r2, =(~UARTxPINMASK)
and r1, r2
ldr r2, =(UARTxPINSEL)
orr r1, r2
str r1, [r0]
/* Power Up Uart0 */
ldr r0, =UARTxPCLKSEL /* PCLKSEL0 address */
ldr r1, [r0]
ldr r2, =(~PCLKSEL_MASK)
and r1, r2
ldr r2, =(U0_PCLKSEL)
orr r1, r2
str r1, [r0]
/* Configure parity, data bits, stop bits and set DLAB=1 */
ldr r0, =UARTxBASE
mov r1, #(LCR_VALUE | LCR_DLAB_ENABLE)
strb r1, [r0, #UART_LCR_OFFSET]
/* Set the BAUD divisor */
mov r1, #((MULVAL << 4) | DIVADDVAL)
strb r1, [r0, #UART_FDR_OFFSET]
mov r1, #DLMVAL
strb r1, [r0, #UART_DLM_OFFSET]
mov r1, #DLLVAL
strb r1, [r0, #UART_DLL_OFFSET]
/* Clear DLAB and Set format 8N1 */
mov r1, #LCR_VALUE
strb r1, [r0, #UART_LCR_OFFSET]
/* Configure the FIFOs */
mov r1, #FCR_VALUE
strb r1, [r0, #UART_FCR_OFFSET]
mov r1, #LCR_VALUE
strb r1, [r0, #UART_LCR_OFFSET]
/* And return */
mov pc, lr
.size up_lowsetup, . - up_lowsetup
.end
arch/arm/src/lpc2378/lpc23xx_pinsel.h
Executable
+792
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File diff suppressed because it is too large Load Diff
arch/arm/src/lpc2378/lpc23xx_pllsetup.c
Executable
+238
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/****************************************************************************
* arch/arm/src/lpc2378/lpc23xx_irq.c
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file holds the NuttX start logic that runs when the LPC2378
* is reset. This logic must be located at address 0x0000:0000 in
* flash but may be linked to run at different locations based on
* the selected mode:
*
* default: Executes from 0x0000:0000. In non-default modes, the
* MEMAP register is set override the settings of the CPU configuration
* pins.
*
* CONFIG_EXTMEM_MODE: Code executes from external memory starting at
* address 0x8000:0000.
*
* CONFIG_RAM_MODE: Code executes from on-chip RAM at address
* 0x4000:0000.
*
* Starupt Code must be linked to run at the correct address
* corresponding to the selected mode.
*/
/***********************************************************************
* Included Files
**********************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include <sys/types.h>
#include "arm.h"
#include "up_arch.h"
#include "internal.h"
#include "lpc23xx_pinsel.h"
#include "lpc23xx_scb.h"
extern void IO_Init(void);
/***********************************************************************
* Definitions
**********************************************************************/
#if ((FOSC < 32000) || (FOSC > 50000000))
# error Fosc out of range (32KHz-50MHz)
# error correct and recompile
#endif
#if ((CCLK < 10000000) || (CCLK > 72000000))
# error cclk out of range (10MHz-72MHz)
# error correct PLL MULTIPLIER and recompile
#endif
#if ((FCCO < 275000000) || (FCCO > 550000000))
# error Fcco out of range (275MHz-550MHz)
# error internal algorithm error
#endif
/* Phase Locked Loop (PLL) initialization values
*
* Bit 0:14 MSEL: PLL Multiplier "M" Value
* CCLK = 57 600 000 Hz
* Bit 16:23 NSEL: PLL Divider "N" Value
* Fcco = (2 * M * F_in) / N
* 275MHz <= Fcco <= 550MHz
*
* PLL clock sources:
* Internal RC 0 default on reset
* Main Oscillator 1
* RTC 2
*/
#ifdef CONFIG_PLL_CLKSRC
# if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
# error "PLL clock source not valid, check configuration "
# endif
#else
# error "PLL clock source not defined, check configuration file"
#endif
/* PLL provides CCLK and must always be configured */
#define PLL ( PLL_M | (PLL_N << 16) )
/* Memory Accelerator Module (MAM) initialization values
*
* MAM Control Register
* Bit 0:1 Mode
* 0 = Disabled
* 1 = Partially Enabled
* 2 = Fully Enabled
* MAM Timing Register
* Bit 0:2 Fetch Cycles
* 0 = Reserved
* 1 = 1 CCLK
* 2 = 2 CCLK
* 3 = 3 CCLK
* 4 = 4 CCLK
* 5 = 5 CCLK
* 6 = 6 CCLK
* 7 = 7 CCLK
*/
/* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
#ifdef CONFIG_MAM_SETUP
# ifndef CONFIG_MAMCR_VALUE /* Can be selected from config file */
# define CONFIG_MAMCR_VALUE (MAMCR_PART)
# endif
# ifndef CONFIG_MAMTIM_VALUE /* Can be selected from config file */
# define CONFIG_MAMTIM_VALUE (0x00000003)
# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_scbpllfeed
****************************************************************************/
static inline void up_scbpllfeed(void)
{
SCB_PLLFEED = 0xAA;
SCB_PLLFEED = 0x55;
}
/****************************************************************************
* Name: ConfigurePLL
****************************************************************************/
void ConfigurePLL ( void )
{
uint32_t MSel, NSel;
/* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
SCB_PCONP |= PCENET;
/* Vectors are remapped to Flash */
SCB_MEMMAP = MEMMAP2FLASH;
/* Enable PLL, disconnected */
if(SCB_PLLSTAT & (1 << 25))
{
SCB_PLLCON = 0x01;
up_scbpllfeed();
}
/* Disable PLL, disconnected */
SCB_PLLCON = 0;
up_scbpllfeed();
/* Enable main OSC */
SCB_SCS |= 0x20;
/* Wait until main OSC is usable */
while( !(SCB_SCS & 0x40) );
/* select main OSC, 12MHz, as the PLL clock source */
SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
/* Reconfigure PLL */
SCB_PLLCFG = PLL;
up_scbpllfeed();
/* Enable PLL */
SCB_PLLCON = 0x01;
up_scbpllfeed();
/* Set clock divider */
SCB_CCLKCFG = CCLK_DIV;
#ifdef CONFIG_USBDEV
/* usbclk = 288 MHz/6 = 48 MHz */
SCB_USBCLKCFG = USBCLK_DIV;
/* Turn On USB PCLK */
SCB_PCONP |= PCUSB;
#endif
/* Wait for PLL to lock */
while( ( SCB_PLLSTAT & (1 << 26) ) == 0);
MSel = SCB_PLLSTAT & 0x00007FFF;
NSel = ( SCB_PLLSTAT & 0x00FF0000 ) >> 16;
while( (MSel != PLL_M) && (NSel != PLL_N) );
/* Enable and connect */
SCB_PLLCON = 0x03;
up_scbpllfeed();
/* Check connect bit status */
while( ( SCB_PLLSTAT & ( 1 << 25 ) ) == 0 );
/* Set memory accelerater module*/
SCB_MAMCR = 0;
SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
SCB_MAMCR = CONFIG_MAMCR_VALUE;
/* Enable FastIO on P0:P1 */
SCB_SCS |= 0x01;
IO_Init();
return;
}
arch/arm/src/lpc2378/lpc23xx_scb.h
Executable
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/****************************************************************************************************
* arch/arm/src/lpc2378/lpc23xx_scb.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_SCB_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_SCB_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <chip.h>
#include "lpc23xx_vic.h"
/****************************************************************************************************
* Definitions
****************************************************************************************************/
#define scb_getreg(o) getreg32(LPC23XX_SCB_BASE + (o))
#define scb_putreg(v,o) putreg32((v),LPC23XX_SCB_BASE + (o))
/* Memory Accelerator Mode */
#define MAMCR_OFF 0
#define MAMCR_PART 1
#define MAMCR_FULL 2
/* Memory Mapping */
#define MEMMAP2BBLK 0 /* Interrupt Vectors in Boot Block */
#define MEMMAP2FLASH 1 /* Interrupt Vectors in FLASH */
#define MEMMAP2SRAM 2 /* Interrupt Vectors in RAM */
/* Register bit settings */
/* PLL Control Register Bit Settings */
#define PLLCON_PLLE (1 << 0) /* PLL Enable */
#define PLLCON_PLLC (1 << 1) /* PLL Connect */
/* PLL Configuration Register Bit Settings */
#define PLLCFG_MSEL (0x0000FFFF << 0) /* PLL Multiplier (minus 1) */
#define PLLCFG_NSEL (0x000000FF << 16) /* PLL Divider */
/* PLL Status Register Bit Settings */
#define PLLSTAT_MSEL (0x7FFF << 0) /* PLL Multiplier Readback */
#define PLLSTAT_NSEL (0xFF << 16) /* PLL Divider Readback */
#define PLLSTAT_PLLE (1 << 24) /* PLL Enable Readback */
#define PLLSTAT_PLLC (1 << 25) /* PLL Connect Readback */
#define PLLSTAT_PLOCK (1 << 26) /* PLL Lock Status */
/* PLL Feed Register values */
#define PLLFEED1 0xaa
#define PLLFEED2 0x55
/* Peripheral Power Control (PCONP) Register 0xE01FC0C4 */
#define PCTIM0 (1 << 1) /* Timer/Counter 0 */
#define PCTIM1 (1 << 2) /* Timer/Counter 1 */
#define PCUART0 (1 << 3) /* UART0 power/clock */
#define PCUART1 (1 << 4) /* UART1 power/clock */
#define PCPWM1 (1 << 5) /* Unused, always 0 */
#define PWM1 (1 << 6) /* Pulse Width Modulation 1 */
#define PCI2C0 (1 << 7) /* I2C0 interface */
#define PCSPI (1 << 8) /* SPI */
#define PCRTC (1 << 9) /* Real Time Clock*/
#define PCSSP1 (1 << 10) /* SSP1 */
#define PCEMC (1 << 11) /* External Memory Controller */
#define PCAD (1 << 12) /* A/D converter (ADC) Note: Clear the PDN bit in the AD0CR before
clearing this bit, and set this bit before setting PDN */
#define PCAN1 (1 << 13) /* CAN Controller 1 */
#define PCAN2 (1 << 14) /* CAN Controller 2 */
#define PCI2C1 (1 << 19) /* The I2C1 interface power/clock control bit */
#define PCSSP0 (1 << 21) /* The SSP0 interface power/clock control bit */
#define PCTIM2 (1 << 22) /* Timer 2 */
#define PCTIM3 (1 << 23) /* Timer 3 */
#define PCUART2 (1 << 24) /* UART 2 */
#define PCUART3 (1 << 25) /* UART 3 */
#define PCI2C2 (1 << 26) /* I2C interface 2 */
#define PCI2S (1 << 27) /* I2S interface */
#define PCSDC (1 << 28) /* SD card interface */
#define PCGPDMA (1 << 29) /* GP DMA function */
#define PCENET (1 << 30) /* Ethernet block */
#define PCUSB (1 << 31) /* USB interface */
/****************************************************************************************************
* Inline Functions
****************************************************************************************************/
/****************************************************************************************************
* Global Function Prototypes
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_SCB_H */
arch/arm/src/lpc2378/lpc23xx_serial.c
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arch/arm/src/lpc2378/lpc23xx_timer.h
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/************************************************************************************
* arch/arm/src/lpc2378/lpc23xx_timer.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_TIMER_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
#define tmr_getreg8(o) getreg8(LPC23XX_TMR0_BASE+(o))
#define tmr_getreg16(o) getreg16(LPC23XX_TMR0_BASE+(o))
#define tmr_getreg32(o) getreg32(LPC23XX_TMR0_BASE+(o))
#define tmr_putreg8(v,o) putreg8((v), LPC23XX_TMR0_BASE+(o))
#define tmr_putreg16(v,o) putreg16((v), LPC23XX_TMR0_BASE+(o))
#define tmr_putreg32(v,o) putreg32((v), LPC23XX_TMR0_BASE+(o))
/* Timer registers are 8, 16-bit and 32-bits wide */
/* Timer Interrupt Register Bit Definitions (8-bit) */
#define TMR_IR_MR0I (1 << 0) /* Interrupt flag for match channel 0 */
#define TMR_IR_MR1I (1 << 1) /* Interrupt flag for match channel 1 */
#define TMR_IR_MR2I (1 << 2) /* Interrupt flag for match channel 2 */
#define TMR_IR_MR3I (1 << 3) /* Interrupt flag for match channel 3 */
#define TMR_IR_CR0I (1 << 4) /* Interrupt flag for capture channel 0 event */
#define TMR_IR_CR1I (1 << 5) /* Interrupt flag for capture channel 1 event */
#define TMR_IR_CR2I (1 << 6) /* Interrupt flag for capture channel 2 event */
#define TMR_IR_CR3I (1 << 7) /* Interrupt flag for capture channel 3 event */
#define TMR_IR_ALLI (0xff) /* All timer interrupts */
/* Timer Control Register Bit Definitions (8-bits) */
#define TMR_CR_ENABLE (1 << 0) /* Counter Enable */
#define TMR_CR_RESET (1 << 1) /* Countger Reset */
/* Timer Counter (32-bits, no bit fields) */
/* Timer Prescale Register Bit Definitions (32-bits, no bit fields) */
/* Timer Prescale Counter Register Bit Definitions */
/* Timer Match Control Register Bit Definitions (16-bit) */
#define TMR_MCR_MR0I (1 << 0) /* Enable Interrupt when MR0 matches TC */
#define TMR_MCR_MR0R (1 << 1) /* Enable Reset of TC upon MR0 match */
#define TMR_MCR_MR0S (1 << 2) /* Enable Stop of TC upon MR0 match */
#define TMR_MCR_MR1I (1 << 3) /* Enable Interrupt when MR1 matches TC */
#define TMR_MCR_MR1R (1 << 4) /* Enable Reset of TC upon MR1 match */
#define TMR_MCR_MR1S (1 << 5) /* Enable Stop of TC upon MR1 match */
#define TMR_MCR_MR2I (1 << 6) /* Enable Interrupt when MR2 matches TC */
#define TMR_MCR_MR2R (1 << 7) /* Enable Reset of TC upon MR2 match */
#define TMR_MCR_MR2S (1 << 8) /* Enable Stop of TC upon MR2 match */
#define TMR_MCR_MR3I (1 << 9) /* Enable Interrupt when MR3 matches TC */
#define TMR_MCR_MR3R (1 << 10) /* Enable Reset of TC upon MR3 match */
#define TMR_MCR_MR3S (1 << 11) /* Enable Stop of TC upon MR3 match */
/* Timer Match Register 0/1/2/3 (32-bits, no bit fields) */
/* Timer Capture Control Register Bit Definitions */
#define TMR_CCR_CAP0RE (1 << 0) /* Enable Rising edge on CAPn.0 will load TC to CR0 */
#define TMR_CCR_CAP0FE (1 << 1) /* Enable Falling edge on CAPn.0 will load TC to CR0 */
#define TMR_CCR_CAP0I (1 << 2) /* Enable Interrupt on load of CR0 */
#define TMR_CCR_CAP1RE (1 << 3) /* Enable Rising edge on CAPn.1 will load TC to CR1 */
#define TMR_CCR_CAP1FE (1 << 4) /* Enable Falling edge on CAPn.1 will load TC to CR1 */
#define TMR_CCR_CAP1I (1 << 5) /* Enable Interrupt on load of CR1 */
//~ #define TMR_CCR_CAP2RE (1 << 6) /* Enable Rising edge on CAPn.2 will load TC to CR2 */
//~ #define TMR_CCR_CAP2FE (1 << 7) /* Enable Falling edge on CAPn.2 will load TC to CR2 */
//~ #define TMR_CCR_CAP2I (1 << 8) /* Enable Interrupt on load of CR2 */
//~ #define TMR_CCR_CAP3RE (1 << 9) /* Enable Rising edge on CAPn.3 will load TC to CR3 */
//~ #define TMR_CCR_CAP3FE (1 << 10) /* Enable Falling edge on CAPn.3 will load TC to CR3 */
//~ #define TMR_CCR_CAP3I (1 << 11) /* Enable Interrupt on load of CR3 */
/* Timer Capture Register 0/1/2/3 (32-bits, no bit fields) */
/* Timer External Match Register Bit Definitions */
#define TMR_EMR_EM0 (1 << 0) /* External Match 0 */
#define TMR_EMR_EM1 (1 << 1) /* External Match 1 */
#define TMR_EMR_EM2 (1 << 2) /* External Match 2 */
#define TMR_EMR_EM3 (1 << 3) /* External Match 3 */
#define TMR_EMR_EMC0(b) ((b) << 4) /* External match control 0 (see below) */
#define TMR_EMR_EMC1(b) ((b) << 6) /* External match control 1 (see below) */
#define TMR_EMR_EMC2(b) ((b) << 8) /* External match control 2 (see below) */
#define TMR_EMR_EMC3(b) ((b) << 10) /* External match control 3 (see below) */
/* EMR External Match Control (EMCn) Field Falues */
#define TMR_EMR_MASK (3) /* Mask for all bits */
#define TMR_EMR_NOOP (0) /* Do nothing */
#define TMR_EMR_CLEAR (1) /* Clear corresponding EMn bit/output to 0 */
#define TMR_EMR_SET (2) /* Set corresponding EMn bit/output to 1 */
#define TMR_EMR_TOGGLE (3) /* Toggle corresponding EMn bit/output */
/* Timer Count Control Register Bit Definitions (8-bit) */
#define TMR_CTCR_MODE_MASK (3 << 0) /* Counter/Timer Mode */
#define TMR_CTCR_PCLK (0 << 0) /* Rising edge of PCLK */
#define TMR_CTCR_RISING (1 << 0) /* Rising edge of CAP input */
#define TMR_CTDR_FALLING (2 << 0) /* Failing edge of CAP input */
#define TMR_CTCR_BOTH (3 << 0) /* Both edges of CAP input */
#define TMR_CTCR_INPUT_MASK (3 << 2) /* Counter Input Select */
#define TMR_CTCR_CR0 (0 << 2) /* CAPn.0 */
#define TMR_CTCR_CR1 (1 << 2) /* CAPn.1 */
#define TMR_CTCR_CR2 (2 << 2) /* CAPn.2 */
#define TMR_CTCR_CR3 (3 << 2) /* CAPn.3 */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_TIMER_H */
arch/arm/src/lpc2378/lpc23xx_timerisr.c
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/****************************************************************************
* arch/arm/src/lpc2378/lpc23xx_timerisr.c
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "clock_internal.h"
#include "internal.h"
#include "up_arch.h"
#include "lpc23xx_scb.h"
#include "lpc23xx_vic.h"
#include "lpc23xx_timer.h"
/****************************************************************************
* Definitions
****************************************************************************/
/* T0_PCLKDIV valid values are 1,2,4 */
#define T0_PCLK_DIV 1
/* PCKLSEL0 bits 3:2, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef T0_PCLK_DIV
# if T0_PCLK_DIV == 1
# define TIMER0_PCLKSEL (0x00000004)
# elif T0_PCLK_DIV == 2
# define TIMER0_PCLKSEL (0x00000008)
# elif T0_PCLK_DIV == 4
# define TIMER0_PCLKSEL (0x00000000)
# endif
#endif
#define T0_PCLKSEL_MASK (0x0000000C)
#define T0_TICKS_COUNT ( (CCLK / T0_PCLK_DIV ) / TICK_PER_SEC )
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Global Functions
****************************************************************************/
/****************************************************************************
* Function: up_timerisr
*
* Description:
* The timer ISR will perform a variety of services for
* various portions of the systems.
*
****************************************************************************/
#ifdef CONFIG_VECTORED_INTERRUPTS
int up_timerisr(uint32_t *regs)
#else
int up_timerisr(int irq, uint32_t *regs)
#endif
{
static uint32_t tick;
/* Process timer interrupt */
sched_process_timer();
/* Clear the MR0 match interrupt */
tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
/* write any value to VICAddress to acknowledge the interrupt */
vic_putreg(0, VIC_ADDRESS_OFFSET);
#endif
if(tick++ > 100){
tick =0;
up_statledoff();
}else up_statledon();
return 0;
}
/****************************************************************************
* Function: up_timerinit
*
* Description:
* This function is called during start-up to initialize
* the system timer interrupt.
*
****************************************************************************/
void up_timerinit(void)
{
uint16_t mcr;
/* Power up Timer0 */
SCB_PCONP |= PCTIM0;
/* Timer0 clock input frequency = CCLK / TO_PCLKDIV */
SCB_PCLKSEL0 = (SCB_PCLKSEL0 & ~T0_PCLKSEL_MASK) | TIMER0_PCLKSEL;
/* Clear all match and capture event interrupts */
tmr_putreg8(TMR_IR_ALLI, TMR_IR_OFFSET);
/* Clear the timer counter */
tmr_putreg32(0, TMR_TC_OFFSET);
/* No pre-scaler */
tmr_putreg32(0, TMR_PR_OFFSET);
tmr_putreg32(0, TMR_PC_OFFSET);
/* Set timer match registger to get a TICK_PER_SEC rate
* See arch/board.h and sched/os_internal.h
*/
tmr_putreg32( T0_TICKS_COUNT, TMR_MR0_OFFSET ); /* 10ms Intterrupt */
/* Reset timer counter register and interrupt on match */
mcr = tmr_getreg16(TMR_MCR_OFFSET);
mcr &= ~TMR_MCR_MR1I;
mcr |= (TMR_MCR_MR0I | TMR_MCR_MR0R);
tmr_putreg16(mcr, TMR_MCR_OFFSET);//-- bit 0=1 -int on MR0, bit 1=1 - Reset on MR0
/* Enable counting */
//~ tmr_putreg32(1, TMR_TCR_OFFSET);
tmr_putreg8(TMR_CR_ENABLE, TMR_TCR_OFFSET);
/* Attach the timer interrupt vector */
#ifdef CONFIG_VECTORED_INTERRUPTS
up_attach_vector(IRQ_SYSTIMER, PRIORITY_HIGHEST, (vic_vector_t)up_timerisr);
#else
(void)irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST);
#endif
/* And enable the system timer interrupt */
up_enable_irq(IRQ_SYSTIMER);
}
arch/arm/src/lpc2378/lpc23xx_uart.h
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/************************************************************************************
* arch/arm/src/lpc2378/lpc2378/uart.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <arch/board/board.h> /* For clock settings */
/************************************************************************************
* Definitions
************************************************************************************/
/* Derive baud divisor setting from clock settings (see board.h) */
//--F_in = 57 600 000 Hz U0DLM=0, U0DLL=25, DIVADDVAL=3, MULVAL=12, baudrate=115200, err = 0.000000 %
//--F_in = 57 600 000 Hz U0DLM=1, U0DLL=119, DIVADDVAL=0, MULVAL=1, baudrate=9600, err = 0.000000 %
/* Used only if CONFIG_UART_MULVAL is not defined */
#define DIVADDVAL 0
#define MULVAL 1
#define DLMVAL 1
#define DLLVAL 119
/* UARTx PCLK divider valid values are 1,2,4 */
#define U0_PCLKDIV 1
//~ #define U1_PCLKDIV 1
#define U2_PCLKDIV 1
//~ #define U3_PCLKDIV 1
#define U0_PCLK (CCLK / U0_PCLKDIV)
//~ #define U1_PCLK (CCLK / U1_PCLKDIV)
#define U2_PCLK (CCLK / U2_PCLKDIV)
//~ #define U3_PCLK (CCLK / U3_PCLKDIV)
#define U0_PCLKSEL_MASK (0x000000C0)
#define U2_PCLKSEL_MASK (0x00030000)
/* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef U0_PCLKDIV
# if U0_PCLKDIV == 1
# define U0_PCLKSEL (0x00000040)
# elif U0_PCLKDIV == 2
# define U0_PCLKSEL (0x00000080)
# elif U0_PCLKDIV == 4
# define U0_PCLKSEL (0x00000000)
# endif
#else
# error "UART0 PCLK divider not set"
#endif
/* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef U2_PCLKDIV
# if U2_PCLKDIV == 1
# define U2_PCLKSEL (0x00010000)
# elif U2_PCLKDIV == 2
# define U2_PCLKSEL (0x00020000)
# elif U2_PCLKDIV == 4
# define U2_PCLKSEL (0x00000000)
# endif
#else
# error "UART2 PCLK divider not set"
#endif
/* Universal Asynchronous Receiver Transmitter Base Addresses */
#define UART0_BASE_ADDR 0xE000C000
#define UART1_BASE_ADDR 0xE0010000
#define UART2_BASE_ADDR 0xE0078000
#define UART3_BASE_ADDR 0xE007C000
/* UART 0/1/2/3 Register Offsets */
#define UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */
#define UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */
#define UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */
#define UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */
#define UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */
#define UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */
#define UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */
#define UART_LCR_OFFSET 0x0c /* RW: Line Control Register */
#define UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */
#define UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */
#define UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */
#define UART_SCR_OFFSET 0x1c /* RW: Line Status Register */
#define UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */
#define UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */
#define UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */
/* PINSEL0 bit definitions for UART0/2 */
#define UART0_PINSEL 0x00000050 /* PINSEL0 value for UART0 */
#define UART0_PINMASK 0x000000F0 /* PINSEL0 mask for UART0 */
#define UART1_TX_PINSEL 0x40000000 /* PINSEL0 value for UART1 Tx */
#define UART1_TXPINMASK 0xC0000000 /* PINSEL0 mask for UART1 Tx */
#define UART1_RX_PINSEL 0x00000001 /* PINSEL1 value for UART1 Rx */
#define UART1_RX_PINMASK 0x00000003 /* PINSEL1 mask for UART1 Rx */
#define UART1_MODEM_PINSEL 0x00001555 /* PINSEL1 mask for UART1 Modem Interface */
#define UART1_CTS_PINMASK 0x00003FFF /* PINSEL1 mask for UART1 Modem Interface */
//~ #define UART1_CTS_PINSEL 0x00000004 /* PINSEL1 mask for UART1 CTS */
//~ #define UART1_CTS_PINMASK 0x0000000C /* PINSEL1 mask for UART1 CTS */
//~ #define UART1_CTS_PINSEL 0x00000010 /* PINSEL1 mask for UART1 Rx */
//~ #define UART1_CTS_PINMASK 0x00000030 /* PINSEL1 mask for UART1 Rx */
#define UART2_PINSEL 0x00500000 /* PINSEL0 value for UART2 */
#define UART2_PINMASK 0x00F00000 /* PINSEL0 mask for UART2 */
#define UART3_PINSEL 0x0F000000 /* PINSEL9 value for UART3 */
#define UART3_PINMASK 0x0F000000 /* PINSEL9 mask for UART3 */
/* Interrupt Enable Register (IER) bit definitions */
#define IER_ERBFI (1 << 0) /* Enable receive data available int */
#define IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */
#define IER_ELSI (1 << 2) /* Enable receive line status int */
#define IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */
#define IER_ALLIE 0x0f /* All interrupts */
/* Interrupt ID Register(IIR) bit definitions */
#define IIR_NO_INT (1 << 0) /* No interrupts pending */
#define IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */
#define IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */
#define IIR_RDA_INT (2 << 1) /* Receive Data Available */
#define IIR_RLS_INT (3 << 1) /* Receive Line Status */
#define IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */
#define IIR_MASK 0x0e
/* FIFO Control Register (FCR) bit definitions */
#define FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */
#define FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */
#define FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */
#define FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */
#define FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */
#define FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */
#define FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */
/* Line Control Register (LCR) bit definitions */
#define LCR_CHAR_5 (0 << 0) /* 5-bit character length */
#define LCR_CHAR_6 (1 << 0) /* 6-bit character length */
#define LCR_CHAR_7 (2 << 0) /* 7-bit character length */
#define LCR_CHAR_8 (3 << 0) /* 8-bit character length */
#define LCR_STOP_1 (0 << 2) /* 1 stop bit */
#define LCR_STOP_2 (1 << 2) /* 2 stop bits */
#define LCR_PAR_NONE (0 << 3) /* No parity */
#define LCR_PAR_ODD (1 << 3) /* Odd parity */
#define LCR_PAR_EVEN (3 << 3) /* Even parity */
#define LCR_PAR_MARK (5 << 3) /* Mark "1" parity */
#define LCR_PAR_SPACE (7 << 3) /* Space "0" parity */
#define LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */
#define LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */
/* Modem Control Register (MCR) bit definitions */
#define MCR_DTR (1 << 0) /* Data terminal ready */
#define MCR_RTS (1 << 1) /* Request to send */
#define MCR_LB (1 << 4) /* Loopback */
/* Line Status Register (LSR) bit definitions */
#define LSR_RDR (1 << 0) /* Receive data ready */
#define LSR_OE (1 << 1) /* Overrun error */
#define LSR_PE (1 << 2) /* Parity error */
#define LSR_FE (1 << 3) /* Framing error */
#define LSR_BI (1 << 4) /* Break interrupt */
#define LSR_THRE (1 << 5) /* THR empty */
#define LSR_TEMT (1 << 6) /* Transmitter empty */
#define LSR_RXFE (1 << 7) /* Error in receive FIFO */
#define LSR_ERR_MASK 0x1e
/* Modem Status Register (MSR) bit definitions */
#define MSR_DCTS (1 << 0) /* Delta clear to send */
#define MSR_DDSR (1 << 1) /* Delta data set ready */
#define MSR_TERI (1 << 2) /* Trailing edge ring indicator */
#define MSR_DDCD (1 << 3) /* Delta data carrier detect */
#define MSR_CTS (1 << 4) /* Clear to send */
#define MSR_DSR (1 << 5) /* Data set ready */
#define MSR_RI (1 << 6) /* Ring indicator */
#define MSR_DCD (1 << 7) /* Data carrier detect */
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Global Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H */
arch/arm/src/lpc2378/lpc23xx_vic.h
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/************************************************************************************
* arch/arm/src/lpc2378/lpc23xx_vic.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_VIC_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_VIC_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* All VIC registers are 32-bits wide */
#define vic_getreg(o) getreg32(LPC23XX_VIC_BASE + (o))
#define vic_putreg(v,o) putreg32((v),LPC23XX_VIC_BASE + (o))
/* Vector Control Register bit definitions */
//~ #define LPC23XX_VECTPRIORITY_IRQMASK (0x0000001f)
//~ #define VECTPRIORITY_IRQMASK (0x0000FFFF)
//~ #define LPC23XX_VECTPRIORITY_IRQSHIFT (0)
//~ #define LPC23XX_VECTPRIORITY_ENABLE (1 << 5)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_VIC_H */