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arch/arm, board/arm: Rename all up_* functions to arm_*

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Summary

The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private functions begin with the name of the architecture, not up_.

This PR addresses only these name changes for the ARM-private functions prototyped in arm_internal.h

This change to the files only modifies the name of called functions.  nxstyle fixes were made for all core architecture files.  However, there are well over 5000 additional complaints from MCU drivers and board logic that are unrelated to to this change but were affected by the name change.  It is not humanly possible to fix all of these.   I ask that this change be treated like other cosmetic changes that we have done which do not require full nxstyle compliance.

Impact

There should be not impact of this change (other that one step toward more consistent naming).
Testing

stm32f4discovery:netnsh
This commit is contained in:
Gregory Nutt
2020-05-01 08:50:23 -06:00
committed by Abdelatif Guettouche
parent c1beda50f8
commit 2aa85fd17e
338 changed files with 1401 additions and 1506 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/a1x/a1x_boot.c
+1 -1
View File
@@ -342,7 +342,7 @@ void arm_boot(void)
* driver.
*/
up_earlyserialinit();
arm_earlyserialinit();
#endif
/* Perform board-specific initialization, This must include:
arch/arm/src/a1x/a1x_lowputc.c
+2 -2
View File
@@ -191,14 +191,14 @@
****************************************************************************/
/****************************************************************************
* Name: up_lowputc
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
void arm_lowputc(char ch)
{
#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE
/* Wait for the transmitter to be available */
arch/arm/src/a1x/a1x_serial.c
+10 -10
View File
@@ -1452,19 +1452,19 @@ static bool up_txempty(struct uart_dev_s *dev)
#ifdef USE_EARLYSERIALINIT
/****************************************************************************
* Name: up_earlyserialinit
* Name: arm_earlyserialinit
*
* Description:
* Performs the low level UART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before up_serialinit.
* before arm_serialinit.
*
* NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
* very early in the boot sequence.
*
****************************************************************************/
void up_earlyserialinit(void)
void arm_earlyserialinit(void)
{
/* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
@@ -1535,15 +1535,15 @@ void up_earlyserialinit(void)
#endif
/****************************************************************************
* Name: up_serialinit
* Name: arm_serialinit
*
* Description:
* Register serial console and serial ports. This assumes that
* up_earlyserialinit was called previously.
* arm_earlyserialinit was called previously.
*
****************************************************************************/
void up_serialinit(void)
void arm_serialinit(void)
{
#ifdef CONSOLE_DEV
uart_register("/dev/console", &CONSOLE_DEV);
@@ -1596,10 +1596,10 @@ int up_putc(int ch)
{
/* Add CR */
up_lowputc('\r');
arm_lowputc('\r');
}
up_lowputc(ch);
arm_lowputc(ch);
#ifdef HAVE_SERIAL_CONSOLE
up_restoreuartint(priv, ier);
#endif
@@ -1626,10 +1626,10 @@ int up_putc(int ch)
{
/* Add CR */
up_lowputc('\r');
arm_lowputc('\r');
}
up_lowputc(ch);
arm_lowputc(ch);
#endif
return ch;
}
arch/arm/src/am335x/am335x_boot.c
+2 -2
View File
@@ -82,7 +82,7 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
@@ -464,7 +464,7 @@ void arm_boot(void)
* driver.
*/
up_earlyserialinit();
arm_earlyserialinit();
#endif
/* Perform board-specific initialization, This must include:
arch/arm/src/am335x/am335x_lowputc.c
+2 -2
View File
@@ -161,14 +161,14 @@
****************************************************************************/
/****************************************************************************
* Name: up_lowputc
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void up_lowputc(char ch)
void arm_lowputc(char ch)
{
#if defined(HAVE_UART_DEVICE) && defined(HAVE_SERIAL_CONSOLE)
/* Wait for the transmitter to be available */
arch/arm/src/am335x/am335x_serial.c
+10 -10
View File
@@ -1269,19 +1269,19 @@ static bool up_txempty(struct uart_dev_s *dev)
#ifdef USE_EARLYSERIALINIT
/****************************************************************************
* Name: up_earlyserialinit
* Name: arm_earlyserialinit
*
* Description:
* Performs the low level UART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before up_serialinit.
* before arm_serialinit.
*
* NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
* very early in the boot sequence.
*
****************************************************************************/
void up_earlyserialinit(void)
void arm_earlyserialinit(void)
{
/* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
@@ -1338,15 +1338,15 @@ void up_earlyserialinit(void)
#endif
/****************************************************************************
* Name: up_serialinit
* Name: arm_serialinit
*
* Description:
* Register serial console and serial ports. This assumes that
* up_earlyserialinit was called previously.
* arm_earlyserialinit was called previously.
*
****************************************************************************/
void up_serialinit(void)
void arm_serialinit(void)
{
#ifdef CONSOLE_DEV
uart_register("/dev/console", &CONSOLE_DEV);
@@ -1393,10 +1393,10 @@ int up_putc(int ch)
{
/* Add CR */
up_lowputc('\r');
arm_lowputc('\r');
}
up_lowputc(ch);
arm_lowputc(ch);
#ifdef HAVE_SERIAL_CONSOLE
up_restoreuartint(priv, ier);
#endif
@@ -1423,10 +1423,10 @@ int up_putc(int ch)
{
/* Add CR */
up_lowputc('\r');
arm_lowputc('\r');
}
up_lowputc(ch);
arm_lowputc(ch);
#endif
return ch;
}
arch/arm/src/arm/arm_allocpage.c
+2 -2
View File
@@ -203,7 +203,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
*/
uintptr_t oldvaddr = PG_POOL_NDX2VA(g_ptemap[pgndx]);
pte = up_va2pte(oldvaddr);
pte = arm_va2pte(oldvaddr);
*pte = 0;
/* Invalidate instruction TLB corresponding to the virtual address */
@@ -227,7 +227,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
* non-cached (MMU_L2_ALLOCFLAGS).
*/
pte = up_va2pte(vaddr);
pte = arm_va2pte(vaddr);
*pte = (paddr | MMU_L2_ALLOCFLAGS);
/* And save the new L1 index */
arch/arm/src/arm/arm_checkmapping.c
+1 -1
View File
@@ -98,7 +98,7 @@ bool up_checkmapping(FAR struct tcb_s *tcb)
/* Get the PTE associated with this virtual address */
pte = up_va2pte(vaddr);
pte = arm_va2pte(vaddr);
/* Return true if this virtual address is mapped. */
arch/arm/src/arm/arm_dataabort.c
+3 -3
View File
@@ -42,7 +42,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_dataabort
* Name: arm_dataabort
*
* Input Parameters:
* regs - The standard, ARM register save array.
@@ -64,7 +64,7 @@
****************************************************************************/
#ifdef CONFIG_PAGING
void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
{
struct tcb_s *tcb = this_task();
#ifdef CONFIG_PAGING
@@ -148,7 +148,7 @@ segfault:
#else /* CONFIG_PAGING */
void up_dataabort(uint32_t *regs)
void arm_dataabort(uint32_t *regs)
{
/* Save the saved processor context in CURRENT_REGS where it can be
* accessed for register dumps and possibly context switching.
arch/arm/src/arm/arm_doirq.c
+3 -3
View File
@@ -57,7 +57,7 @@
* Public Functions
****************************************************************************/
void up_doirq(int irq, uint32_t *regs)
void arm_doirq(int irq, uint32_t *regs)
{
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
@@ -75,7 +75,7 @@ void up_doirq(int irq, uint32_t *regs)
/* Acknowledge the interrupt */
up_ack_irq(irq);
arm_ack_irq(irq);
/* Deliver the IRQ */
@@ -94,7 +94,7 @@ void up_doirq(int irq, uint32_t *regs)
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
up_restorefpu((uint32_t *)CURRENT_REGS);
arm_restorefpu((uint32_t *)CURRENT_REGS);
#endif
#ifdef CONFIG_ARCH_ADDRENV
arch/arm/src/arm/arm_head.S
+1 -1
View File
@@ -211,7 +211,7 @@
#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
bl arm_lowputc
.endm
#else
.macro showprogress, code
arch/arm/src/arm/arm_nommuhead.S
+2 -2
View File
@@ -52,7 +52,7 @@
#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
bl arm_lowputc
.endm
#else
.macro showprogress, code
@@ -112,7 +112,7 @@ __start:
mov fp, #0
#ifdef USE_EARLYSERIALINIT
bl up_earlyserialinit
bl arm_earlyserialinit
#endif
#ifdef CONFIG_DEBUG_FEATURES
arch/arm/src/arm/arm_pginitialize.c
+3 -3
View File
@@ -51,7 +51,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_pginitialize()
* Name: arm_pginitialize()
*
* Description:
* Initialize the MMU for on-demand paging support..
@@ -69,10 +69,10 @@
*
****************************************************************************/
void up_pginitialize(void)
void arm_pginitialize(void)
{
/* None needed at present. This file is just retained in case the need
* arises in the future. Nothing calls up_pginitialize() now. If needed,
* arises in the future. Nothing calls arm_pginitialize() now. If needed,
* if should be called early in arm_boot.c to assure that all paging is
* ready.
*/
arch/arm/src/arm/arm_prefetchabort.c
+2 -2
View File
@@ -52,7 +52,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_prefetchabort
* Name: arm_prefetchabort
*
* Description:
* This is the prefetch abort exception handler. The ARM prefetch abort
@@ -61,7 +61,7 @@
*
****************************************************************************/
void up_prefetchabort(uint32_t *regs)
void arm_prefetchabort(uint32_t *regs)
{
#ifdef CONFIG_PAGING
uint32_t *savestate;
arch/arm/src/arm/arm_schedulesigaction.c
+2 -2
View File
@@ -148,7 +148,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* disabled
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
/* And make sure that the saved context in the TCB
@@ -180,7 +180,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* disabled
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
}
}
arch/arm/src/arm/arm_sigdeliver.c
+2 -2
View File
@@ -58,7 +58,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_sigdeliver
* Name: arm_sigdeliver
*
* Description:
* This is the a signal handling trampoline. When a signal action was
@@ -67,7 +67,7 @@
*
****************************************************************************/
void up_sigdeliver(void)
void arm_sigdeliver(void)
{
struct tcb_s *rtcb = this_task();
uint32_t regs[XCPTCONTEXT_REGS];
arch/arm/src/arm/arm_syscall.c
+2 -2
View File
@@ -52,7 +52,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_syscall
* Name: arm_syscall
*
* Description:
* SWI interrupts will vector here with insn=the SWI instruction and
@@ -64,7 +64,7 @@
*
****************************************************************************/
void up_syscall(uint32_t *regs)
void arm_syscall(uint32_t *regs)
{
_alert("Syscall from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
arch/arm/src/arm/arm_undefinedinsn.c
+2 -2
View File
@@ -52,10 +52,10 @@
****************************************************************************/
/****************************************************************************
* Name: up_undefinedinsn
* Name: arm_undefinedinsn
****************************************************************************/
void up_undefinedinsn(uint32_t *regs)
void arm_undefinedinsn(uint32_t *regs)
{
_alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
arch/arm/src/arm/arm_va2pte.c
+2 -2
View File
@@ -69,7 +69,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_va2pte()
* Name: arm_va2pte()
*
* Description:
* Convert a virtual address within the paged text region into a pointer to
@@ -89,7 +89,7 @@
*
****************************************************************************/
uint32_t *up_va2pte(uintptr_t vaddr)
uint32_t *arm_va2pte(uintptr_t vaddr)
{
uint32_t L1;
uint32_t *L2;
arch/arm/src/arm/arm_vectoraddrexcptn.S
+5 -5
View File
@@ -75,9 +75,9 @@
*
************************************************************************************/
.globl up_vectoraddrexcptn
.type up_vectoraddrexcptn, %function
up_vectoraddrexcptn:
b up_vectoraddrexcptn
.size up_vectoraddrexcptn, . - up_vectoraddrexcptn
.globl arm_vectoraddrexcptn
.type arm_vectoraddrexcptn, %function
arm_vectoraddrexcptn:
b arm_vectoraddrexcptn
.size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn
.end
arch/arm/src/arm/arm_vectors.S
+40 -40
View File
@@ -79,16 +79,16 @@ g_aborttmp:
.text
/************************************************************************************
* Name: up_vectorirq
* Name: arm_vectorirq
*
* Description:
* Interrupt exception. Entered in IRQ mode with spsr = SVC CPSR, lr = SVC PC
*
************************************************************************************/
.globl up_vectorirq
.type up_vectorirq, %function
up_vectorirq:
.globl arm_vectorirq
.type arm_vectorirq, %function
arm_vectorirq:
/* On entry, we are in IRQ mode. We are free to use
* the IRQ mode r13 and r14.
*/
@@ -133,10 +133,10 @@ up_vectorirq:
#if CONFIG_ARCH_INTERRUPTSTACK > 3
ldr sp, .Lirqstackbase /* SP = interrupt stack base */
str r0, [sp] /* Save the user stack pointer */
bl up_decodeirq /* Call the handler */
bl arm_decodeirq /* Call the handler */
ldr sp, [sp] /* Restore the user stack pointer */
#else
bl up_decodeirq /* Call the handler */
bl arm_decodeirq /* Call the handler */
#endif
/* Restore the CPSR, SVC mode registers and return */
@@ -151,20 +151,20 @@ up_vectorirq:
.Lirqstackbase:
.word g_intstackbase
#endif
.size up_vectorirq, . - up_vectorirq
.size arm_vectorirq, . - arm_vectorirq
.align 5
/************************************************************************************
* Function: up_vectorswi
* Function: arm_vectorswi
*
* Description:
* SWI interrupt. We enter the SWI in SVC mode.
*
************************************************************************************/
.globl up_vectorswi
.type up_vectorswi, %function
up_vectorswi:
.globl arm_vectorswi
.type arm_vectorswi, %function
arm_vectorswi:
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
@@ -185,24 +185,24 @@ up_vectorswi:
stmia r0, {r1-r4}
/* Then call the SWI handler with interrupts disabled.
* void up_syscall(struct xcptcontext *xcp)
* void arm_syscall(struct xcptcontext *xcp)
*/
mov fp, #0 /* Init frame pointer */
mov r0, sp /* Get r0=xcp */
bl up_syscall /* Call the handler */
bl arm_syscall /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
msr spsr, r0
ldmia sp, {r0-r15}^ /* Return */
.size up_vectorswi, . - up_vectorswi
.size arm_vectorswi, . - arm_vectorswi
.align 5
/************************************************************************************
* Name: up_vectordata
* Name: arm_vectordata
*
* Description:
* This is the data abort exception dispatcher. The ARM data abort exception occurs
@@ -212,9 +212,9 @@ up_vectorswi:
*
************************************************************************************/
.globl up_vectordata
.type up_vectordata, %function
up_vectordata:
.globl arm_vectordata
.type arm_vectordata, %function
arm_vectordata:
/* On entry we are free to use the ABORT mode registers
* r13 and r14
*/
@@ -252,7 +252,7 @@ up_vectordata:
stmia r0, {r1-r4}
/* Then call the data abort handler with interrupts disabled.
* void up_dataabort(struct xcptcontext *xcp)
* void arm_dataabort(struct xcptcontext *xcp)
*/
mov fp, #0 /* Init frame pointer */
@@ -261,7 +261,7 @@ up_vectordata:
mrc p15, 0, r2, c5, c0, 0 /* Get r2=FSR */
mrc p15, 0, r1, c6, c0, 0 /* Get R1=FAR */
#endif
bl up_dataabort /* Call the handler */
bl arm_dataabort /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
@@ -271,12 +271,12 @@ up_vectordata:
.Ldaborttmp:
.word g_aborttmp
.size up_vectordata, . - up_vectordata
.size arm_vectordata, . - arm_vectordata
.align 5
/************************************************************************************
* Name: up_vectorprefetch
* Name: arm_vectorprefetch
*
* Description:
* This is the prefetch abort exception dispatcher. The ARM prefetch abort exception
@@ -286,9 +286,9 @@ up_vectordata:
*
************************************************************************************/
.globl up_vectorprefetch
.type up_vectorprefetch, %function
up_vectorprefetch:
.globl arm_vectorprefetch
.type arm_vectorprefetch, %function
arm_vectorprefetch:
/* On entry we are free to use the ABORT mode registers
* r13 and r14
*/
@@ -326,12 +326,12 @@ up_vectorprefetch:
stmia r0, {r1-r4}
/* Then call the prefetch abort handler with interrupts disabled.
* void up_prefetchabort(struct xcptcontext *xcp)
* void arm_prefetchabort(struct xcptcontext *xcp)
*/
mov fp, #0 /* Init frame pointer */
mov r0, sp /* Get r0=xcp */
bl up_prefetchabort /* Call the handler */
bl arm_prefetchabort /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
@@ -341,12 +341,12 @@ up_vectorprefetch:
.Lpaborttmp:
.word g_aborttmp
.size up_vectorprefetch, . - up_vectorprefetch
.size arm_vectorprefetch, . - arm_vectorprefetch
.align 5
/************************************************************************************
* Name: up_vectorundefinsn
* Name: arm_vectorundefinsn
*
* Description:
* Undefined instruction entry exception. Entered in UND mode, spsr = SVC CPSR,
@@ -354,9 +354,9 @@ up_vectorprefetch:
*
************************************************************************************/
.globl up_vectorundefinsn
.type up_vectorundefinsn, %function
up_vectorundefinsn:
.globl arm_vectorundefinsn
.type arm_vectorundefinsn, %function
arm_vectorundefinsn:
/* On entry we are free to use the UND mode registers
* r13 and r14
*/
@@ -393,12 +393,12 @@ up_vectorundefinsn:
stmia r0, {r1-r4}
/* Then call the undef insn handler with interrupts disabled.
* void up_undefinedinsn(struct xcptcontext *xcp)
* void arm_undefinedinsn(struct xcptcontext *xcp)
*/
mov fp, #0 /* Init frame pointer */
mov r0, sp /* Get r0=xcp */
bl up_undefinedinsn /* Call the handler */
bl arm_undefinedinsn /* Call the handler */
/* Restore the CPSR, SVC mode registers and return */
@@ -408,23 +408,23 @@ up_vectorundefinsn:
.Lundeftmp:
.word g_undeftmp
.size up_vectorundefinsn, . - up_vectorundefinsn
.size arm_vectorundefinsn, . - arm_vectorundefinsn
.align 5
/************************************************************************************
* Name: up_vectorfiq
* Name: arm_vectorfiq
*
* Description:
* Shouldn't happen
*
************************************************************************************/
.globl up_vectorfiq
.type up_vectorfiq, %function
up_vectorfiq:
.globl arm_vectorfiq
.type arm_vectorfiq, %function
arm_vectorfiq:
subs pc, lr, #4
.size up_vectorfiq, . - up_vectorfiq
.size arm_vectorfiq, . - arm_vectorfiq
/************************************************************************************
* Name: g_intstackalloc/g_intstackbase
arch/arm/src/arm/arm_vectortab.S
+14 -14
View File
@@ -73,30 +73,30 @@ _vector_start:
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
.globl __start
.globl up_vectorundefinsn
.globl up_vectorswi
.globl up_vectorprefetch
.globl up_vectordata
.globl up_vectoraddrexcptn
.globl up_vectorirq
.globl up_vectorfiq
.globl arm_vectorundefinsn
.globl arm_vectorswi
.globl arm_vectorprefetch
.globl arm_vectordata
.globl arm_vectoraddrexcptn
.globl arm_vectorirq
.globl arm_vectorfiq
.Lresethandler:
.long __start
.Lundefinedhandler:
.long up_vectorundefinsn
.long arm_vectorundefinsn
.Lswihandler:
.long up_vectorswi
.long arm_vectorswi
.Lprefetchaborthandler:
.long up_vectorprefetch
.long arm_vectorprefetch
.Ldataaborthandler:
.long up_vectordata
.long arm_vectordata
.Laddrexcptnhandler:
.long up_vectoraddrexcptn
.long arm_vectoraddrexcptn
.Lirqhandler:
.long up_vectorirq
.long arm_vectorirq
.Lfiqhandler:
.long up_vectorfiq
.long arm_vectorfiq
.globl _vector_end
_vector_end:
arch/arm/src/armv6-m/arm_doirq.c
+2 -2
View File
@@ -55,7 +55,7 @@
* Public Functions
****************************************************************************/
uint32_t *up_doirq(int irq, uint32_t *regs)
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
@@ -80,7 +80,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
/* Acknowledge the interrupt */
up_ack_irq(irq);
arm_ack_irq(irq);
/* Deliver the IRQ */
arch/arm/src/armv6-m/arm_exception.S
+4 -4
View File
@@ -141,7 +141,7 @@ exception_common:
mrs r0, ipsr /* R0=exception number */
/* Disable interrupts, select the stack to use for interrupt handling
* and call up_doirq to handle the interrupt
* and call arm_doirq to handle the interrupt
*/
cpsid i /* Disable further interrupts */
@@ -155,15 +155,15 @@ exception_common:
ldr r7, =g_intstackbase /* R7=Base of the interrupt stack */
mov sp, r7 /* Set the new stack point */
push {r1} /* Save the MSP on the interrupt stack */
bl up_doirq /* R0=IRQ, R1=register save area on stack */
bl arm_doirq /* R0=IRQ, R1=register save area on stack */
pop {r1} /* Recover R1=main stack pointer */
#else
msr msp, r1 /* We are using the main stack pointer */
bl up_doirq /* R0=IRQ, R1=register save area on stack */
bl arm_doirq /* R0=IRQ, R1=register save area on stack */
mrs r1, msp /* Recover R1=main stack pointer */
#endif
/* On return from up_doirq, r0 will hold a pointer to register context
/* On return from arm_doirq, r0 will hold a pointer to register context
* array to use for the interrupt return. If that return value is the same
* as current stack pointer, then things are relatively easy.
*/
arch/arm/src/armv6-m/arm_hardfault.c
+3 -3
View File
@@ -73,7 +73,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_hardfault
* Name: arm_hardfault
*
* Description:
* This is Hard Fault exception handler. It also catches SVC call
@@ -81,7 +81,7 @@
*
****************************************************************************/
int up_hardfault(int irq, FAR void *context, FAR void *arg)
int arm_hardfault(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
@@ -121,7 +121,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
if (insn == INSN_SVC0)
{
hfinfo("Forward SVCall\n");
return up_svcall(irq, context, NULL);
return arm_svcall(irq, context, NULL);
}
}
arch/arm/src/armv6-m/arm_schedulesigaction.c
+2 -2
View File
@@ -147,7 +147,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* privileged thread mode.
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_PRIMASK] = 1;
CURRENT_REGS[REG_XPSR] = ARMV6M_XPSR_T;
#ifdef CONFIG_BUILD_PROTECTED
@@ -186,7 +186,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* here.
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_PRIMASK] = 1;
tcb->xcp.regs[REG_XPSR] = ARMV6M_XPSR_T;
#ifdef CONFIG_BUILD_PROTECTED
arch/arm/src/armv6-m/arm_sigdeliver.c
+2 -2
View File
@@ -57,7 +57,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_sigdeliver
* Name: arm_sigdeliver
*
* Description:
* This is the a signal handling trampoline. When a signal action was
@@ -66,7 +66,7 @@
*
****************************************************************************/
void up_sigdeliver(void)
void arm_sigdeliver(void)
{
/* NOTE the "magic" guard space added to regs. This is a little kludge
* because arm_fullcontextrestore (called below) will do a stack-to-stack
arch/arm/src/armv6-m/arm_svcall.c
+3 -3
View File
@@ -109,14 +109,14 @@ static void dispatch_syscall(void)
****************************************************************************/
/****************************************************************************
* Name: up_svcall
* Name: arm_svcall
*
* Description:
* This is SVCall exception handler that performs context switching
*
****************************************************************************/
int up_svcall(int irq, FAR void *context, FAR void *arg)
int arm_svcall(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
@@ -223,7 +223,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
/* R0=SYS_syscall_return: This a syscall return command:
*
* void up_syscall_return(void);
* void arm_syscall_return(void);
*
* At this point, the following values are saved in context:
*
arch/arm/src/armv6-m/svcall.h
+1 -1
View File
@@ -84,7 +84,7 @@
#ifdef CONFIG_LIB_SYSCALL
/* SYS call 3:
*
* void up_syscall_return(void);
* void arm_syscall_return(void);
*/
#define SYS_syscall_return (3)
arch/arm/src/armv7-a/arm_copyarmstate.c
+1 -1
View File
@@ -75,7 +75,7 @@ void arm_copyarmstate(uint32_t *dest, uint32_t *src)
* registers at indices ARM_CONTEXT_REGS through (XCPTCONTEXT_REGS-1)
*/
up_savefpu(dest);
arm_savefpu(dest);
/* Then copy all of the ARM registers (omitting the floating point
* registers). Indices: 0 through (ARM_CONTEXT_REGS-1).
arch/arm/src/armv7-a/arm_doirq.c
+1 -1
View File
@@ -108,7 +108,7 @@ static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
up_restorefpu((uint32_t *)CURRENT_REGS);
arm_restorefpu((uint32_t *)CURRENT_REGS);
#endif
#ifdef CONFIG_ARCH_ADDRENV
arch/arm/src/armv7-a/arm_head.S
+1 -1
View File
@@ -174,7 +174,7 @@
#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
bl arm_lowputc
.endm
#else
.macro showprogress, code
arch/arm/src/armv7-a/arm_l2cc_pl310.c
+2 -2
View File
@@ -293,7 +293,7 @@ static void pl310_flush_all(void)
****************************************************************************/
/****************************************************************************
* Name: up_l2ccinitialize
* Name: arm_l2ccinitialize
*
* Description:
* One time configuration of the L2 cache. The L2 cache will be enabled
@@ -308,7 +308,7 @@ static void pl310_flush_all(void)
*
****************************************************************************/
void up_l2ccinitialize(void)
void arm_l2ccinitialize(void)
{
uint32_t regval;
int i;
arch/arm/src/armv7-a/arm_pghead.S
+1 -1
View File
@@ -198,7 +198,7 @@
#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
bl arm_lowputc
.endm
#else
.macro showprogress, code
arch/arm/src/armv7-a/arm_pginitialize.c
+3 -3
View File
@@ -54,7 +54,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_pginitialize()
* Name: arm_pginitialize()
*
* Description:
* Initialize the MMU for on-demand paging support..
@@ -72,10 +72,10 @@
*
****************************************************************************/
void up_pginitialize(void)
void arm_pginitialize(void)
{
/* None needed at present. This file is just retained in case the need
* arises in the future. Nothing calls up_pginitialize() now. If needed,
* arises in the future. Nothing calls arm_pginitialize() now. If needed,
* if should be called early in arm_boot.c to assure that all paging is
* ready.
*/
arch/arm/src/armv7-a/arm_restorefpu.S
+7 -7
View File
@@ -49,7 +49,7 @@
* Public Symbols
************************************************************************************/
.globl up_restorefpu
.globl arm_restorefpu
/************************************************************************************
* Public Functions
@@ -58,14 +58,14 @@
.text
/************************************************************************************
* Name: up_restorefpu
* Name: arm_restorefpu
*
* Description:
* Given the pointer to a register save area (in R0), restore the state of the
* floating point registers.
*
* C Function Prototype:
* void up_restorefpu(const uint32_t *regs);
* void arm_restorefpu(const uint32_t *regs);
*
* Input Parameters:
* regs - A pointer to the register save area containing the floating point
@@ -77,10 +77,10 @@
*
************************************************************************************/
.globl up_restorefpu
.type up_restorefpu, function
.globl arm_restorefpu
.type arm_restorefpu, function
up_restorefpu:
arm_restorefpu:
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
@@ -98,6 +98,6 @@ up_restorefpu:
vmsr fpscr, r2 /* Restore the FPCSR */
bx lr
.size up_restorefpu, .-up_restorefpu
.size arm_restorefpu, .-arm_restorefpu
#endif /* CONFIG_ARCH_FPU */
.end
arch/arm/src/armv7-a/arm_savefpu.S
+7 -7
View File
@@ -53,7 +53,7 @@
* Public Symbols
************************************************************************************/
.globl up_savefpu
.globl arm_savefpu
/************************************************************************************
* Public Functions
@@ -62,14 +62,14 @@
.text
/************************************************************************************
* Name: up_savefpu
* Name: arm_savefpu
*
* Description:
* Given the pointer to a register save area (in R0), save the state of the
* floating point registers.
*
* C Function Prototype:
* void up_savefpu(uint32_t *regs);
* void arm_savefpu(uint32_t *regs);
*
* Input Parameters:
* regs - A pointer to the register save area in which to save the floating point
@@ -80,10 +80,10 @@
*
************************************************************************************/
.globl up_savefpu
.type up_savefpu, function
.globl arm_savefpu
.type arm_savefpu, function
up_savefpu:
arm_savefpu:
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
@@ -101,6 +101,6 @@ up_savefpu:
str r2, [r1], #4 /* Save the floating point control and status register */
bx lr
.size up_savefpu, .-up_savefpu
.size arm_savefpu, .-arm_savefpu
#endif /* CONFIG_ARCH_FPU */
.end
arch/arm/src/armv7-a/arm_schedulesigaction.c
+6 -6
View File
@@ -153,7 +153,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* disabled
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
CURRENT_REGS[REG_CPSR] |= PSR_T_BIT;
@@ -187,7 +187,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* disabled
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
@@ -280,7 +280,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* disabled
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
@@ -305,7 +305,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* privileged thread mode.
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
CURRENT_REGS[REG_CPSR] |= PSR_T_BIT;
@@ -329,7 +329,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* involves spinlocks that are configured per the TCB irqcount
* field. This is logically equivalent to enter_critical_section().
* The matching call to leave_critical_section() will be
* performed in up_sigdeliver().
* performed in arm_sigdeliver().
*/
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
@@ -371,7 +371,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* disabled
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
#ifdef CONFIG_ARM_THUMB
tcb->xcp.regs[REG_CPSR] |= PSR_T_BIT;
arch/arm/src/armv7-a/arm_sigdeliver.c
+2 -2
View File
@@ -58,7 +58,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_sigdeliver
* Name: arm_sigdeliver
*
* Description:
* This is the a signal handling trampoline. When a signal action was
@@ -67,7 +67,7 @@
*
****************************************************************************/
void up_sigdeliver(void)
void arm_sigdeliver(void)
{
struct tcb_s *rtcb = this_task();
uint32_t regs[XCPTCONTEXT_REGS];
arch/arm/src/armv7-a/arm_syscall.c
+1 -1
View File
@@ -157,7 +157,7 @@ uint32_t *arm_syscall(uint32_t *regs)
{
/* R0=SYS_syscall_return: This a SYSCALL return command:
*
* void up_syscall_return(void);
* void arm_syscall_return(void);
*
* At this point, the following values are saved in context:
*
arch/arm/src/armv7-a/l2cc.h
+2 -2
View File
@@ -66,7 +66,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: up_l2ccinitialize
* Name: arm_l2ccinitialize
*
* Description:
* One time configuration of the L2 cache. The L2 cache will be enabled
@@ -82,7 +82,7 @@ extern "C"
****************************************************************************/
#if 0 /* Prototyped in arm_internal.h */
void up_l2ccinitialize(void);
void arm_l2ccinitialize(void);
#endif
/****************************************************************************
arch/arm/src/armv7-a/svcall.h
+1 -1
View File
@@ -62,7 +62,7 @@
/* SYS call 0:
*
* void up_syscall_return(void);
* void arm_syscall_return(void);
*/
#define SYS_syscall_return (0)
arch/arm/src/armv7-m/arm_copyarmstate.c
+1 -1
View File
@@ -60,7 +60,7 @@ void arm_copyarmstate(uint32_t *dest, uint32_t *src)
* registers at indices SW_INT_REGS through (SW_INT_REGS+SW_FPU_REGS-1)
*/
up_savefpu(dest);
arm_savefpu(dest);
/* Save the block of ARM registers that were saved by the interrupt
* handling logic. Indices: 0 through (SW_INT_REGS-1).
arch/arm/src/armv7-m/arm_doirq.c
+2 -2
View File
@@ -39,7 +39,7 @@
* Public Functions
****************************************************************************/
uint32_t *up_doirq(int irq, uint32_t *regs)
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
@@ -64,7 +64,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
/* Acknowledge the interrupt */
up_ack_irq(irq);
arm_ack_irq(irq);
/* Deliver the IRQ */
arch/arm/src/armv7-m/arm_hardfault.c
+3 -3
View File
@@ -63,7 +63,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_hardfault
* Name: arm_hardfault
*
* Description:
* This is Hard Fault exception handler. It also catches SVC call
@@ -71,7 +71,7 @@
*
****************************************************************************/
int up_hardfault(int irq, FAR void *context, FAR void *arg)
int arm_hardfault(int irq, FAR void *context, FAR void *arg)
{
/* Get the value of the program counter where the fault occurred */
@@ -112,7 +112,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
if (insn == INSN_SVC0)
{
hfinfo("Forward SVCall\n");
return up_svcall(irq, context, arg);
return arm_svcall(irq, context, arg);
}
}
#endif
arch/arm/src/armv7-m/arm_memfault.c
+2 -2
View File
@@ -50,7 +50,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_memfault
* Name: arm_memfault
*
* Description:
* This is Memory Management Fault exception handler. Normally we get
@@ -60,7 +60,7 @@
*
****************************************************************************/
int up_memfault(int irq, FAR void *context, FAR void *arg)
int arm_memfault(int irq, FAR void *context, FAR void *arg)
{
/* Dump some memory management fault info */
arch/arm/src/armv7-m/arm_schedulesigaction.c
+6 -6
View File
@@ -144,7 +144,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* privileged thread mode.
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
#ifdef CONFIG_ARMV7M_USEBASEPRI
CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
#else
@@ -191,7 +191,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* here.
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
#ifdef CONFIG_ARMV7M_USEBASEPRI
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
#else
@@ -299,7 +299,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to be here.
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
#ifdef CONFIG_ARMV7M_USEBASEPRI
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
#else
@@ -337,7 +337,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* privileged thread mode.
*/
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
#ifdef CONFIG_ARMV7M_USEBASEPRI
CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
#else
@@ -367,7 +367,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* field. This is logically equivalent to
* enter_critical_section(). The matching call to
* leave_critical_section() will be performed in
* up_sigdeliver().
* arm_sigdeliver().
*/
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
@@ -417,7 +417,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* here.
*/
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
#ifdef CONFIG_ARMV7M_USEBASEPRI
tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
#else
arch/arm/src/armv7-m/arm_sigdeliver.c
+2 -2
View File
@@ -42,7 +42,7 @@
****************************************************************************/
/****************************************************************************
* Name: up_sigdeliver
* Name: arm_sigdeliver
*
* Description:
* This is the a signal handling trampoline. When a signal action was
@@ -51,7 +51,7 @@
*
****************************************************************************/
void up_sigdeliver(void)
void arm_sigdeliver(void)
{
struct tcb_s *rtcb = this_task();
uint32_t regs[XCPTCONTEXT_REGS];
arch/arm/src/armv7-m/arm_svcall.c
+5 -5
View File
@@ -117,14 +117,14 @@ static void dispatch_syscall(void)
****************************************************************************/
/****************************************************************************
* Name: up_svcall
* Name: arm_svcall
*
* Description:
* This is SVCall exception handler that performs context switching
*
****************************************************************************/
int up_svcall(int irq, FAR void *context, FAR void *arg)
int arm_svcall(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
@@ -179,7 +179,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
DEBUGASSERT(regs[REG_R1] != 0);
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
up_savefpu((uint32_t *)regs[REG_R1]);
arm_savefpu((uint32_t *)regs[REG_R1]);
#endif
}
break;
@@ -229,7 +229,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0);
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
up_savefpu((uint32_t *)regs[REG_R1]);
arm_savefpu((uint32_t *)regs[REG_R1]);
#endif
CURRENT_REGS = (uint32_t *)regs[REG_R2];
}
@@ -237,7 +237,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
/* R0=SYS_syscall_return: This a syscall return command:
*
* void up_syscall_return(void);
* void arm_syscall_return(void);
*
* At this point, the following values are saved in context:
*
arch/arm/src/armv7-m/gnu/arm_exception.S
+4 -4
View File
@@ -165,7 +165,7 @@ exception_common:
/* Save the non-volatile FP registers here.
*
* This routine is the only point where we can save these registers; either before
* or after calling up_doirq. The compiler is free to use them at any time as long
* or after calling arm_doirq. The compiler is free to use them at any time as long
* as they are restored before returning, so we can't assume that we can get at the
* true values of these registers in any routine called from here.
*
@@ -179,7 +179,7 @@ exception_common:
stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP/PRIMASK values */
/* There are two arguments to up_doirq:
/* There are two arguments to arm_doirq:
*
* R0 = The IRQ number
* R1 = The top of the stack points to the saved state
@@ -210,10 +210,10 @@ exception_common:
#endif
bl up_doirq /* R0=IRQ, R1=register save (msp) */
bl arm_doirq /* R0=IRQ, R1=register save (msp) */
mov r1, r4 /* Recover R1=main stack pointer */
/* On return from up_doirq, R0 will hold a pointer to register context
/* On return from arm_doirq, R0 will hold a pointer to register context
* array to use for the interrupt return. If that return value is the same
* as current stack pointer, then things are relatively easy.
*/

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