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Costmetic changes from last merge to better conform to the coding standard

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This commit is contained in:
Gregory Nutt
2015-09-29 09:06:16 -06:00
parent daa4d4b422
commit 2a6c71e850
6 changed files with 436 additions and 264 deletions
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arch/arm/src/lpc43xx/chip/lpc43_usb0.h
+3 -3
View File
@@ -565,9 +565,9 @@
#define USBHOST_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBHOST_USBMODE_CM_MASK (3 << USBHOST_USBMODE_CM_SHIFT)
#define USBHOST_USBMODE_CM_IDLE (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */
#define USBHOST_USBMODE_CM_DEVICE (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */
#define USBHOST_USBMODE_CM_HOST (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */
# define USBHOST_USBMODE_CM_IDLE (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */
# define USBHOST_USBMODE_CM_DEVICE (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */
# define USBHOST_USBMODE_CM_HOST (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */
#define USBHOST_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
/* Bit 3: Not used in host mode */
#define USBHOST_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
arch/arm/src/lpc43xx/lpc43_cgu.c
+25 -29
View File
@@ -428,14 +428,14 @@ static inline void lpc43_m4clkselect(uint32_t clksel)
void lpc43_pll0usbconfig(void)
{
//power down, no bypass, direct i-o,
putreg32( (PLL0USB_CTRL_PD | PLL0USB_CTRL_DIRECTI | PLL0USB_CTRL_DIRECTO | PLL0USB_CTRL_CLKEN | PLL0USB_CTRL_AUTOBLOCK | BOARD_USB0_CLKSRC), LPC43_PLL0USB_CTRL);
/* Power down, no bypass, direct i-o, */
putreg32((PLL0USB_CTRL_PD | PLL0USB_CTRL_DIRECTI | PLL0USB_CTRL_DIRECTO | PLL0USB_CTRL_CLKEN | PLL0USB_CTRL_AUTOBLOCK | BOARD_USB0_CLKSRC), LPC43_PLL0USB_CTRL);
putreg32(BOARD_USB0_MDIV, LPC43_PLL0USB_MDIV);
putreg32(BOARD_USB0_NP_DIV, LPC43_PLL0USB_NP_DIV);
}
/****************************************************************************
* Name: lpc43_pll0usbenable
*
@@ -467,7 +467,6 @@ void lpc43_pll0usbenable(void)
while ((getreg32(LPC43_PLL0USB_STAT) & PLL0USB_STAT_LOCK) == 0);
}
/****************************************************************************
* Name: lpc43_pll0usbdisable
*
@@ -489,17 +488,17 @@ void lpc43_pll0usbdisable(void)
putreg32(regval, LPC43_PLL0USB_CTRL);
}
#if defined(BOARD_IDIVA_DIVIDER) && defined(BOARD_IDIVA_CLKSRC )
#if defined(BOARD_IDIVA_DIVIDER) && defined(BOARD_IDIVA_CLKSRC)
void lpc43_idiva(void)
{
uint32_t regval;
//set clock source, divider
/* Set clock source, divider */
regval = getreg32(LPC43_IDIVA_CTRL);
regval &= ~( IDIVA_CTRL_CLKSEL_MASK | IDIVA_CTRL_IDIV_MASK );
regval &= ~(IDIVA_CTRL_CLKSEL_MASK | IDIVA_CTRL_IDIV_MASK);
regval |= BOARD_IDIVA_CLKSRC | IDIVA_CTRL_AUTOBLOCK | IDIVA_CTRL_IDIV(BOARD_IDIVA_DIVIDER);
putreg32(regval, LPC43_IDIVA_CTRL);
}
#endif
@@ -508,12 +507,12 @@ void lpc43_idivb(void)
{
uint32_t regval;
//set clock source, divider
/* Set clock source, divider */
regval = getreg32(LPC43_IDIVB_CTRL);
regval &= ~( IDIVBCD_CTRL_CLKSEL_MASK | IDIVBCD_CTRL_IDIV_MASK );
regval &= ~(IDIVBCD_CTRL_CLKSEL_MASK | IDIVBCD_CTRL_IDIV_MASK);
regval |= BOARD_IDIVB_CLKSRC | IDIVBCD_CTRL_AUTOBLOCK | IDIVBCD_CTRL_IDIV(BOARD_IDIVB_DIVIDER);
putreg32(regval, LPC43_IDIVB_CTRL);
}
#endif
@@ -522,12 +521,12 @@ void lpc43_idivc(void)
{
uint32_t regval;
//set clock source, divider
/* Set clock source, divider */
regval = getreg32(LPC43_IDIVC_CTRL);
regval &= ~( IDIVBCD_CTRL_CLKSEL_MASK | IDIVBCD_CTRL_IDIV_MASK );
regval &= ~(IDIVBCD_CTRL_CLKSEL_MASK | IDIVBCD_CTRL_IDIV_MASK);
regval |= BOARD_IDIVC_CLKSRC | IDIVBCD_CTRL_AUTOBLOCK | IDIVBCD_CTRL_IDIV(BOARD_IDIVC_DIVIDER);
putreg32(regval, LPC43_IDIVC_CTRL);
}
#endif
@@ -536,12 +535,12 @@ void lpc43_idivd(void)
{
uint32_t regval;
//set clock source, divider
/* Set clock source, divider */
regval = getreg32(LPC43_IDIVD_CTRL);
regval &= ~( IDIVBCD_CTRL_CLKSEL_MASK | IDIVBCD_CTRL_IDIV_MASK );
regval &= ~(IDIVBCD_CTRL_CLKSEL_MASK | IDIVBCD_CTRL_IDIV_MASK);
regval |= BOARD_IDIVD_CLKSRC | IDIVBCD_CTRL_AUTOBLOCK | IDIVBCD_CTRL_IDIV(BOARD_IDIVD_DIVIDER);
putreg32(regval, LPC43_IDIVD_CTRL);
}
#endif
@@ -550,27 +549,26 @@ void lpc43_idive(void)
{
uint32_t regval;
//set clock source, divider
/* Set clock source, divider */
regval = getreg32(LPC43_IDIVE_CTRL);
regval &= ~( IDIVE_CTRL_CLKSEL_MASK | IDIVE_CTRL_IDIV_MASK );
regval &= ~(IDIVE_CTRL_CLKSEL_MASK | IDIVE_CTRL_IDIV_MASK);
regval |= BOARD_IDIVE_CLKSRC | IDIVE_CTRL_AUTOBLOCK | IDIVE_CTRL_IDIV(BOARD_IDIVE_DIVIDER);
putreg32(regval, LPC43_IDIVE_CTRL);
}
#endif
#if defined(BOARD_ABP1_CLKSRC)
void lpc43_abp1(void)
{
uint32_t regval;
//set clock source
/* Set clock source */
regval = getreg32(LPC43_BASE_APB1_CLK);
regval &= ~BASE_APB1_CLK_CLKSEL_MASK;
regval |= BOARD_ABP1_CLKSRC | BASE_APB1_CLK_AUTOBLOCK;
putreg32(regval, LPC43_BASE_APB1_CLK);
}
#endif
@@ -579,12 +577,12 @@ void lpc43_abp3(void)
{
uint32_t regval;
//set clock source
/* Set clock source */
regval = getreg32(LPC43_BASE_APB3_CLK);
regval &= ~BASE_APB3_CLK_CLKSEL_MASK;
regval |= BOARD_ABP3_CLKSRC | BASE_APB3_CLK_AUTOBLOCK;
putreg32(regval, LPC43_BASE_APB3_CLK);
}
#endif
@@ -652,7 +650,7 @@ void lpc43_clockconfig(void)
lpc43_pll1config(PLL_CONTROLS);
#endif
//configure idivs
/* Configure idivs */
#if defined(BOARD_IDIVA_DIVIDER) && defined(BOARD_IDIVA_CLKSRC)
lpc43_idiva();
@@ -674,7 +672,7 @@ void lpc43_clockconfig(void)
lpc43_idive();
#endif
//configure abpXs
/* Configure abpXs */
#if defined(BOARD_ABP1_CLKSRC)
lpc43_abp1();
@@ -683,6 +681,4 @@ void lpc43_clockconfig(void)
#if defined(BOARD_ABP3_CLKSRC)
lpc43_abp3();
#endif
}
arch/arm/src/lpc43xx/lpc43_i2c.c
+86 -75
View File
@@ -94,15 +94,15 @@ struct lpc43_i2cdev_s
struct i2c_msg_s msg; /* a single message for legacy read/write */
unsigned int base; /* Base address of registers */
uint16_t irqid; /* IRQ for this device */
uint32_t baseFreq; /* branch frequency */
uint32_t baseFreq; /* branch frequency */
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* watchdog to timeout when bus hung */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
unsigned int nmsg; /* number of transfer remaining */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
unsigned int nmsg; /* number of transfer remaining */
uint16_t wrcnt; /* number of bytes sent to tx fifo */
uint16_t rdcnt; /* number of bytes read from rx fifo */
@@ -152,8 +152,6 @@ struct i2c_ops_s lpc43_i2c_ops =
#endif
};
/*******************************************************************************
* Name: lpc43_i2c_setfrequency
*
@@ -166,23 +164,23 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *) dev;
if (frequency > 100000)
{
/* asymetric per 400Khz I2C spec */
{
/* asymetric per 400Khz I2C spec */
putreg32(priv->baseFreq / (83 + 47) * 47 / frequency, priv->base + LPC43_I2C_SCLH_OFFSET);
putreg32(priv->baseFreq / (83 + 47) * 83 / frequency, priv->base + LPC43_I2C_SCLL_OFFSET);
}
else
{
/* 50/50 mark space ratio */
putreg32(priv->baseFreq / (83 + 47) * 47 / frequency, priv->base + LPC43_I2C_SCLH_OFFSET);
putreg32(priv->baseFreq / (83 + 47) * 83 / frequency, priv->base + LPC43_I2C_SCLL_OFFSET);
}
else
{
/* 50/50 mark space ratio */
putreg32(priv->baseFreq / 100 * 50 / frequency, priv->base + LPC43_I2C_SCLH_OFFSET);
putreg32(priv->baseFreq / 100 * 50 / frequency, priv->base + LPC43_I2C_SCLL_OFFSET);
}
putreg32(priv->baseFreq / 100 * 50 / frequency, priv->base + LPC43_I2C_SCLH_OFFSET);
putreg32(priv->baseFreq / 100 * 50 / frequency, priv->base + LPC43_I2C_SCLL_OFFSET);
}
/* FIXME: This function should return the actual selected frequency */
return (frequency);
return frequency;
}
/*******************************************************************************
@@ -232,9 +230,10 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer,
priv->nmsg = 1;
priv->msgs = &(priv->msg);
if ( buflen>0 ) {
ret = i2c_start(priv);
}
if (buflen > 0)
{
ret = i2c_start(priv);
}
return (ret == 0 ? 0 : -ETIMEDOUT);
}
@@ -255,8 +254,8 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
DEBUGASSERT(dev != NULL);
priv->wrcnt=0;
priv->rdcnt=0;
priv->wrcnt = 0;
priv->rdcnt = 0;
priv->msg.addr |= 0x01;
priv->msg.buffer = buffer;
priv->msg.length = buflen;
@@ -264,9 +263,10 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
priv->nmsg = 1;
priv->msgs = &(priv->msg);
if ( buflen>0 ) {
ret = i2c_start(priv);
}
if (buflen > 0)
{
ret = i2c_start(priv);
}
return (ret == 0 ? 0 : -ETIMEDOUT);
}
@@ -297,7 +297,7 @@ static int i2c_start(struct lpc43_i2cdev_s *priv)
sem_post(&priv->mutex);
return (ret);
return ret;
}
/*******************************************************************************
@@ -358,19 +358,22 @@ static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, i
ret = count - i2c_start(priv);
return (ret);
return ret;
}
void startStopNextMessage(struct lpc43_i2cdev_s *priv) {
priv->nmsg--;
void startStopNextMessage(struct lpc43_i2cdev_s *priv)
{
priv->nmsg--;
if( priv->nmsg > 0 ) {
priv->msgs++;
putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET);
} else {
i2c_stop(priv);
}
if(priv->nmsg > 0)
{
priv->msgs++;
putreg32(I2C_CONSET_STA,priv->base+LPC43_I2C_CONSET_OFFSET);
}
else
{
i2c_stop(priv);
}
}
/*******************************************************************************
@@ -406,57 +409,60 @@ static int i2c_interrupt(int irq, FAR void *context)
}
/* Reference UM10360 19.10.5 */
state = getreg32(priv->base+LPC43_I2C_STAT_OFFSET);
msg = priv->msgs;
priv->state = state;
state &= 0xf8; //state mask, only 0xX8 is possible
state &= 0xf8; /* state mask, only 0xX8 is possible */
switch (state)
{
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
putreg32(msg->addr, priv->base + LPC43_I2C_DAT_OFFSET); //set address
putreg32(I2C_CONCLR_STAC, priv->base + LPC43_I2C_CONCLR_OFFSET); //clear start bit
putreg32(msg->addr, priv->base + LPC43_I2C_DAT_OFFSET); /* set address */
putreg32(I2C_CONCLR_STAC, priv->base + LPC43_I2C_CONCLR_OFFSET); /* clear start bit */
break;
//write cases
case 0x18: //SLA+W has been transmitted; ACK has been received
/* Write cases */
case 0x18: /* SLA+W has been transmitted; ACK has been received */
priv->wrcnt=0;
putreg32(msg->buffer[0], priv->base + LPC43_I2C_DAT_OFFSET); //put first byte
putreg32(msg->buffer[0], priv->base + LPC43_I2C_DAT_OFFSET); /* put first byte */
break;
case 0x28: //Data byte in DAT has been transmitted; ACK has been received.
case 0x28: /* Data byte in DAT has been transmitted; ACK has been received. */
priv->wrcnt++;
if (priv->wrcnt < msg->length) {
putreg32(msg->buffer[priv->wrcnt],priv->base+LPC43_I2C_DAT_OFFSET); //put next byte
putreg32(msg->buffer[priv->wrcnt],priv->base+LPC43_I2C_DAT_OFFSET); /* Put next byte */
} else {
startStopNextMessage(priv);
startStopNextMessage(priv);
}
break;
//read cases
case 0x40: //SLA+R has been transmitted; ACK has been received
/* Read cases */
case 0x40: /* SLA+R has been transmitted; ACK has been received */
priv->rdcnt = 0;
if ( msg->length > 1 ) {
putreg32(I2C_CONSET_AA, priv->base + LPC43_I2C_CONSET_OFFSET); // set ACK next read
if (msg->length > 1) {
putreg32(I2C_CONSET_AA, priv->base + LPC43_I2C_CONSET_OFFSET); /* Set ACK next read */
} else {
putreg32(I2C_CONCLR_AAC,priv->base + LPC43_I2C_CONCLR_OFFSET); // do not ACK because only one byte
putreg32(I2C_CONCLR_AAC,priv->base + LPC43_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */
}
break;
case 0x50: //Data byte has been received; ACK has been returned.
case 0x50: /* Data byte has been received; ACK has been returned. */
priv->rdcnt++;
msg->buffer[priv->rdcnt-1 ] = getreg32(priv->base+LPC43_I2C_BUFR_OFFSET);
if ( priv->rdcnt >= (msg->length - 1) ) {
putreg32(I2C_CONCLR_AAC,priv->base+LPC43_I2C_CONCLR_OFFSET); // do not ACK any more
if (priv->rdcnt >= (msg->length - 1)) {
putreg32(I2C_CONCLR_AAC,priv->base+LPC43_I2C_CONCLR_OFFSET); /* Do not ACK any more */
}
break;
case 0x58: //Data byte has been received; NACK has been returned.
case 0x58: /* Data byte has been received; NACK has been returned. */
msg->buffer[priv->rdcnt ] = getreg32(priv->base+LPC43_I2C_BUFR_OFFSET);
startStopNextMessage(priv);
break;
@@ -466,13 +472,11 @@ static int i2c_interrupt(int irq, FAR void *context)
break;
}
putreg32(I2C_CONCLR_SIC, priv->base + LPC43_I2C_CONCLR_OFFSET); //clear interrupt
putreg32(I2C_CONCLR_SIC, priv->base + LPC43_I2C_CONCLR_OFFSET); /* clear interrupt */
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -489,7 +493,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
{
struct lpc43_i2cdev_s *priv;
if (port>1)
if (port > 1)
{
dbg("lpc I2C Only support 0,1\n");
return NULL;
@@ -503,27 +507,33 @@ struct i2c_dev_s *up_i2cinitialize(int port)
#ifdef CONFIG_LPC43_I2C0
if (port == 0)
{
priv = &g_i2c0dev;
priv->base = LPC43_I2C0_BASE;
priv->irqid = LPC43M0_IRQ_I2C0;
priv = &g_i2c0dev;
priv->base = LPC43_I2C0_BASE;
priv->irqid = LPC43M0_IRQ_I2C0;
priv->baseFreq = BOARD_ABP1_FREQUENCY;
//enable, set mode
regval = getreg32(LPC43_SCU_SFSI2C0 );
/* Enable, set mode */
regval = getreg32(LPC43_SCU_SFSI2C0);
regval |= SCU_SFSI2C0_SCL_EZI | SCU_SFSI2C0_SDA_EZI;
if ( CONFIG_I2C0_FREQ == 1000000 ) { //super fast mode
regval |= SCU_SFSI2C0_SCL_EHD | SCU_SFSI2C0_SDA_EHD;
}
if (CONFIG_I2C0_FREQ == 1000000)
{
/* Super fast mode */
regval |= SCU_SFSI2C0_SCL_EHD | SCU_SFSI2C0_SDA_EHD;
}
putreg32(regval, LPC43_SCU_SFSI2C0);
//enable clock
/* Enable clock */
regval = getreg32(LPC43_CCU1_APB1_I2C0_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_APB1_I2C0_CFG);
i2c_setfrequency( (struct i2c_dev_s *)priv,CONFIG_I2C0_FREQ);
i2c_setfrequency((struct i2c_dev_s *)priv,CONFIG_I2C0_FREQ);
//no pins configuration needed
/* No pin configuration needed */
}
else
#endif
@@ -535,14 +545,16 @@ struct i2c_dev_s *up_i2cinitialize(int port)
priv->irqid = LPC43M0_IRQ_I2C1;
priv->baseFreq = BOARD_ABP3_FREQUENCY;
//no need to enable
/* No need to enable */
/* Enable clock */
//enable clock
regval = getreg32(LPC43_CCU1_APB3_I2C1_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_APB3_I2C1_CFG);
//pins configuration
/* Pin configuration */
lpc43_pin_config(PINCONF_I2C1_SCL);
lpc43_pin_config(PINCONF_I2C1_SDA);
@@ -578,7 +590,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
/* Install our operations */
priv->dev.ops = &lpc43_i2c_ops;
return (&priv->dev);
return &priv->dev;
}
/*******************************************************************************
@@ -599,5 +611,4 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
return OK;
}
#endif
#endif /* CONFIG_LPC43_I2C0 || CONFIG_LPC43_I2C1 */
arch/arm/src/lpc43xx/lpc43_ssp.c
+19 -9
View File
@@ -175,7 +175,7 @@ static struct lpc43_sspdev_s g_ssp0dev =
{
.spidev = { &g_spi0ops },
.sspbase = LPC43_SSP0_BASE,
.sspbasefreq = BOARD_SSP0_BASEFREQ
.sspbasefreq = BOARD_SSP0_BASEFREQ
#ifdef CONFIG_LPC43_SSP_INTERRUPTS
.sspirq = LPC43_IRQ_SSP0,
#endif
@@ -210,7 +210,7 @@ static struct lpc43_sspdev_s g_ssp1dev =
{
.spidev = { &g_spi1ops },
.sspbase = LPC43_SSP1_BASE,
.sspbasefreq = BOARD_SSP1_BASEFREQ
.sspbasefreq = BOARD_SSP1_BASEFREQ
#ifdef CONFIG_LPC43_SSP_INTERRUPTS
.sspirq = LPC43_IRQ_SSP1,
#endif
@@ -309,6 +309,7 @@ static int ssp_lock(FAR struct spi_dev_s *dev, bool lock)
{
(void)sem_post(&priv->exclsem);
}
return OK;
}
#endif
@@ -708,22 +709,26 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp0initialize(void)
flags = irqsave();
/* Configure clocking */
regval = getreg32(LPC43_BASE_SSP0_CLK);
regval &= ~BASE_SSP0_CLK_CLKSEL_MASK;
regval |= (BOARD_SSP0_CLKSRC | BASE_SSP0_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_SSP0_CLK);
//clock register
/* Clock register */
regval = getreg32(LPC43_CCU1_M4_SSP0_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_SSP0_CFG);
//clock peripheral
/* Clock peripheral */
regval = getreg32(LPC43_CCU2_APB0_SSP0_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB0_SSP0_CFG);
//pins configuration
/* Pin configuration */
lpc43_pin_config(PINCONF_SSP0_SCK);
lpc43_pin_config(PINCONF_SSP0_SSEL);
lpc43_pin_config(PINCONF_SSP0_MISO);
@@ -758,22 +763,26 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void)
flags = irqsave();
/* Configure clocking */
regval = getreg32(LPC43_BASE_SSP1_CLK);
regval &= ~BASE_SSP1_CLK_CLKSEL_MASK;
regval |= (BOARD_SSP1_CLKSRC | BASE_SSP1_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_SSP1_CLK);
//clock register
/* Clock register */
regval = getreg32(LPC43_CCU1_M4_SSP1_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_SSP1_CFG);
//clock peripheral
/* Clock peripheral */
regval = getreg32(LPC43_CCU2_APB2_SSP1_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB2_SSP1_CFG);
//pins configuration
/* Pins configuration */
lpc43_pin_config(PINCONF_SSP1_SCK);
lpc43_pin_config(PINCONF_SSP1_SSEL);
lpc43_pin_config(PINCONF_SSP1_MISO);
@@ -818,11 +827,13 @@ FAR struct spi_dev_s *lpc43_sspinitialize(int port)
priv = lpc43_ssp0initialize();
break;
#endif
#ifdef CONFIG_LPC43_SSP1
case 1:
priv = lpc43_ssp1initialize();
break;
#endif
default:
return NULL;
}
@@ -908,4 +919,3 @@ void ssp_flush(FAR struct spi_dev_s *dev)
}
#endif /* CONFIG_LPC43_SSP0/1 */
arch/arm/src/lpc43xx/lpc43_uart.c
+17 -9
View File
@@ -334,12 +334,14 @@ void lpc43_usart0_setup(void)
regval |= (BOARD_USART0_CLKSRC | BASE_USART0_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_USART0_CLK);
//clock register
/* Clock register */
regval = getreg32(LPC43_CCU1_M4_USART0_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_USART0_CFG);
//clock peripheral
/* Clock peripheral */
regval = getreg32(LPC43_CCU2_APB0_USART0_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB0_USART0_CFG);
@@ -381,12 +383,14 @@ void lpc43_uart1_setup(void)
regval |= (BOARD_UART1_CLKSRC | BASE_UART1_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_UART1_CLK);
//clock register
/* Clock register */
regval = getreg32(LPC43_CCU1_M4_UART1_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_UART1_CFG);
//clock peripheral
/* Clock peripheral */
regval = getreg32(LPC43_CCU2_APB0_UART1_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB0_UART1_CFG);
@@ -428,12 +432,14 @@ void lpc43_usart2_setup(void)
regval |= (BOARD_USART2_CLKSRC | BASE_USART2_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_USART2_CLK);
//clock register
/* Clock register */
regval = getreg32(LPC43_CCU1_M4_USART2_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_USART2_CFG);
//clock peripheral
/* Clock peripheral */
regval = getreg32(LPC43_CCU2_APB2_USART2_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB2_USART2_CFG);
@@ -476,12 +482,14 @@ void lpc43_usart3_setup(void)
regval |= (BOARD_USART3_CLKSRC | BASE_USART3_CLK_AUTOBLOCK);
putreg32(regval, LPC43_BASE_USART3_CLK);
//clock register
/* Clock register */
regval = getreg32(LPC43_CCU1_M4_USART3_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU1_M4_USART3_CFG);
//clock peripheral
/* Clock peripheral */
regval = getreg32(LPC43_CCU2_APB2_USART3_CFG);
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB2_USART3_CFG);
@@ -561,7 +569,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
/* Candidate:
* dl = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
* (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
*/
*/
uint64_t dl64 = ((uint64_t)basefreq << 28) * cmul /
((cmul + cdivadd) * baud);
arch/arm/src/lpc43xx/lpc43_usb0dev.c
+286 -139
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