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Move SAM3U header files to arch/arm/src/sam3u/chip. Some renaming of SAM3U to SAM to ssupport SAM4. Convert all configs/sam3u-ek configurations to use the kconfig-frontends tool

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This commit is contained in:
Gregory Nutt
2013-06-02 10:33:57 -06:00
parent 47d3a627d6
commit 28c64c90bd
80 changed files with 7744 additions and 7206 deletions
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ChangeLog
+5
View File
@@ -4850,3 +4850,8 @@
From Laurent Latil (2013-6-1).
* configs/stm32_tiny: Fix nRF24L01+ driver integration for the STM32
Tiny. From Laurent Latil (2013-6-01).
* configs/sam3u-ek: All remaining configurations changed to use
the kconfig-frontends tools (2013-6-2).
* arch/arm/src/sam3u/chip: All SAM3U register defintion files moved
to this subdirectory. Naming of registers changed from SAM3U_ to
just SAM_. This is in preparation for a SAM4L port (2013-6-2).
arch/arm/Kconfig
+5 -6
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@@ -110,12 +110,11 @@ config ARCH_CHIP_NUC1XX
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
config ARCH_CHIP_SAM3U
bool "Atmel AT91SAM3"
select ARCH_CORTEXM3
config ARCH_CHIP_SAM34
bool "Atmel AT91SAM3/SAM4"
select ARCH_HAVE_MPU
---help---
Atmel AT91SAM3 architectures (ARM Cortex-M3)
Atmel AT91SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
config ARCH_CHIP_STM32
bool "STMicro STM32"
@@ -178,7 +177,7 @@ config ARCH_CHIP
default "lpc31xx" if ARCH_CHIP_LPC31XX
default "lpc43xx" if ARCH_CHIP_LPC43XX
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "sam3u" if ARCH_CHIP_SAM3U
default "sam3u" if ARCH_CHIP_SAM34
default "stm32" if ARCH_CHIP_STM32
default "str71x" if ARCH_CHIP_STR71X
@@ -325,7 +324,7 @@ endif
if ARCH_CHIP_NUC1XX
source arch/arm/src/nuc1xx/Kconfig
endif
if ARCH_CHIP_SAM3U
if ARCH_CHIP_SAM34
source arch/arm/src/sam3u/Kconfig
endif
if ARCH_CHIP_STM32
arch/arm/include/sam3u/chip.h
+13 -13
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@@ -51,19 +51,19 @@
#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E
/* Internal memory */
# define CONFIG_SAM3U_SRAM0_SIZE 0x00008000 /* 32Kb */
# define CONFIG_SAM3U_SRAM1_SIZE 0x00004000 /* 16Kb */
# define CONFIG_SAM3U_NFCSRAM_SIZE 0x00001000 /* 4Kb */
# define CONFIG_SAM34_SRAM0_SIZE 0x00008000 /* 32Kb */
# define CONFIG_SAM34_SRAM1_SIZE 0x00004000 /* 16Kb */
# define CONFIG_SAM34_NFCSRAM_SIZE 0x00001000 /* 4Kb */
/* DMA */
# define CONFIG_SAM3U_NDMACHAN 4 /* 4 DMA Channels */
# define CONFIG_SAM34_NDMACHAN 4 /* 4 DMA Channels */
/* Memory card interface */
# define CONFIG_SAM3U_MCI2 1
# define CONFIG_SAM34_MCI2 1
#else
# error "Unknown SAM3U chip type"
# error "Unknown SAM3/4 chip type"
#endif
/* NVIC priority levels *************************************************************/
@@ -71,14 +71,14 @@
* the priority of the corresponding interrupt. The processor implements only
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
/************************************************************************************
* Public Types
arch/arm/include/sam3u/irq.h
+186 -186
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/include/sam3u/irq.h
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -50,37 +50,37 @@
/* SAM3U Peripheral Identifiers */
#define SAM3U_PID_SUPC (0) /* Supply Controller */
#define SAM3U_PID_RSTC (1) /* Reset Controller */
#define SAM3U_PID_RTC (2) /* Real Time Clock */
#define SAM3U_PID_RTT (3) /* Real Time Timer */
#define SAM3U_PID_WDT (4) /* Watchdog Timer */
#define SAM3U_PID_PMC (5) /* Power Management Controller */
#define SAM3U_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
#define SAM3U_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */
#define SAM3U_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */
#define SAM3U_PID_SMC (9) /* Static Memory Controller */
#define SAM3U_PID_PIOA (10) /* Parallel I/O Controller A */
#define SAM3U_PID_PIOB (11) /* Parallel I/O Controller B */
#define SAM3U_PID_PIOC (12) /* Parallel I/O Controller C */
#define SAM3U_PID_USART0 (13) /* USART 0 */
#define SAM3U_PID_USART1 (14) /* USART 1 */
#define SAM3U_PID_USART2 (15) /* USART 2 */
#define SAM3U_PID_USART3 (16) /* USART 3 */
#define SAM3U_PID_HSMCI (17) /* High Speed Multimedia Card Interface */
#define SAM3U_PID_TWI0 (18) /* Two-Wire Interface 0 */
#define SAM3U_PID_TWI1 (19) /* Two-Wire Interface 1 */
#define SAM3U_PID_SPI (20) /* Serial Peripheral Interface */
#define SAM3U_PID_SSC (21) /* Synchronous Serial Controller */
#define SAM3U_PID_TC0 (22) /* Timer Counter 0 */
#define SAM3U_PID_TC1 (23) /* Timer Counter 1 */
#define SAM3U_PID_TC2 (24) /* Timer Counter 2 */
#define SAM3U_PID_PWM (25) /* Pulse Width Modulation Controller */
#define SAM3U_PID_ADC12B (26) /* 12-bit ADC Controller */
#define SAM3U_PID_ADC (27) /* 10-bit ADC Controller */
#define SAM3U_PID_DMAC (28) /* DMA Controller */
#define SAM3U_PID_UDPHS (29) /* USB Device High Speed */
#define NR_PIDS (30) /* Number of peripheral identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */
#define SAM_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */
#define SAM_PID_SMC (9) /* Static Memory Controller */
#define SAM_PID_PIOA (10) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (11) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (12) /* Parallel I/O Controller C */
#define SAM_PID_USART0 (13) /* USART 0 */
#define SAM_PID_USART1 (14) /* USART 1 */
#define SAM_PID_USART2 (15) /* USART 2 */
#define SAM_PID_USART3 (16) /* USART 3 */
#define SAM_PID_HSMCI (17) /* High Speed Multimedia Card Interface */
#define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */
#define SAM_PID_SPI (20) /* Serial Peripheral Interface */
#define SAM_PID_SSC (21) /* Synchronous Serial Controller */
#define SAM_PID_TC0 (22) /* Timer Counter 0 */
#define SAM_PID_TC1 (23) /* Timer Counter 1 */
#define SAM_PID_TC2 (24) /* Timer Counter 2 */
#define SAM_PID_PWM (25) /* Pulse Width Modulation Controller */
#define SAM_PID_ADC12B (26) /* 12-bit ADC Controller */
#define SAM_PID_ADC (27) /* 10-bit ADC Controller */
#define SAM_PID_DMAC (28) /* DMA Controller */
#define SAM_PID_UDPHS (29) /* USB Device High Speed */
#define NR_PIDS (30) /* Number of peripheral identifiers */
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
@@ -89,179 +89,179 @@
/* Processor Exceptions (vectors 0-15) */
#define SAM3U_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM3U_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM3U_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM3U_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM3U_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM3U_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define SAM3U_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define SAM3U_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define SAM3U_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM3U_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define SAM3U_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define SAM3U_IRQ_SUPC (SAM3U_IRQ_EXTINT+SAM3U_PID_SUPC) /* Supply Controller */
#define SAM3U_IRQ_RSTC (SAM3U_IRQ_EXTINT+SAM3U_PID_RSTC) /* Reset Controller */
#define SAM3U_IRQ_RTC (SAM3U_IRQ_EXTINT+SAM3U_PID_RTC) /* Real Time Clock */
#define SAM3U_IRQ_RTT (SAM3U_IRQ_EXTINT+SAM3U_PID_RTT) /* Real Time Timer */
#define SAM3U_IRQ_WDT (SAM3U_IRQ_EXTINT+SAM3U_PID_WDT) /* Watchdog Timer */
#define SAM3U_IRQ_PMC (SAM3U_IRQ_EXTINT+SAM3U_PID_PMC) /* Power Management Controller */
#define SAM3U_IRQ_EEFC0 (SAM3U_IRQ_EXTINT+SAM3U_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */
#define SAM3U_IRQ_EEFC1 (SAM3U_IRQ_EXTINT+SAM3U_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */
#define SAM3U_IRQ_UART (SAM3U_IRQ_EXTINT+SAM3U_PID_UART) /* Universal Asynchronous Receiver Transmitter */
#define SAM3U_IRQ_SMC (SAM3U_IRQ_EXTINT+SAM3U_PID_SMC) /* Static Memory Controller */
#define SAM3U_IRQ_PIOA (SAM3U_IRQ_EXTINT+SAM3U_PID_PIOA) /* Parallel I/O Controller A */
#define SAM3U_IRQ_PIOB (SAM3U_IRQ_EXTINT+SAM3U_PID_PIOB) /* Parallel I/O Controller B */
#define SAM3U_IRQ_PIOC (SAM3U_IRQ_EXTINT+SAM3U_PID_PIOC) /* Parallel I/O Controller C */
#define SAM3U_IRQ_USART0 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART0) /* USART 0 */
#define SAM3U_IRQ_USART1 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART1) /* USART 1 */
#define SAM3U_IRQ_USART2 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART2) /* USART 2 */
#define SAM3U_IRQ_USART3 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART3) /* USART 3 */
#define SAM3U_IRQ_HSMCI (SAM3U_IRQ_EXTINT+SAM3U_PID_HSMCI) /* High Speed Multimedia Card Interface */
#define SAM3U_IRQ_TWI0 (SAM3U_IRQ_EXTINT+SAM3U_PID_TWI0) /* Two-Wire Interface 0 */
#define SAM3U_IRQ_TWI1 (SAM3U_IRQ_EXTINT+SAM3U_PID_TWI1) /* Two-Wire Interface 1 */
#define SAM3U_IRQ_SPI (SAM3U_IRQ_EXTINT+SAM3U_PID_SPI) /* Serial Peripheral Interface */
#define SAM3U_IRQ_SSC (SAM3U_IRQ_EXTINT+SAM3U_PID_SSC) /* Synchronous Serial Controller */
#define SAM3U_IRQ_TC0 (SAM3U_IRQ_EXTINT+SAM3U_PID_TC0) /* Timer Counter 0 */
#define SAM3U_IRQ_TC1 (SAM3U_IRQ_EXTINT+SAM3U_PID_TC1) /* Timer Counter 1 */
#define SAM3U_IRQ_TC2 (SAM3U_IRQ_EXTINT+SAM3U_PID_TC2) /* Timer Counter 2 */
#define SAM3U_IRQ_PWM (SAM3U_IRQ_EXTINT+SAM3U_PID_PWM) /* Pulse Width Modulation Controller */
#define SAM3U_IRQ_ADC12B (SAM3U_IRQ_EXTINT+SAM3U_PID_ADC12B) /* 12-bit ADC Controller */
#define SAM3U_IRQ_ADC (SAM3U_IRQ_EXTINT+SAM3U_PID_ADC) /* 10-bit ADC Controller */
#define SAM3U_IRQ_DMAC (SAM3U_IRQ_EXTINT+SAM3U_PID_DMAC) /* DMA Controller */
#define SAM3U_IRQ_UDPHS (SAM3U_IRQ_EXTINT+SAM3U_PID_UDPHS) /* USB Device High Speed */
#define SAM3U_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM3U_IRQ_NIRQS (SAM3U_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */
#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */
#define SAM_IRQ_UART (SAM_IRQ_EXTINT+SAM_PID_UART) /* Universal Asynchronous Receiver Transmitter */
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */
#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* USART 3 */
#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */
#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+SAM_PID_SPI) /* Serial Peripheral Interface */
#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC12B (SAM_IRQ_EXTINT+SAM_PID_ADC12B) /* 12-bit ADC Controller */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* 10-bit ADC Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMA Controller */
#define SAM_IRQ_UDPHS (SAM_IRQ_EXTINT+SAM_PID_UDPHS) /* USB Device High Speed */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM3U_IRQ_PIOA/B/C) */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
#ifdef CONFIG_GPIOA_IRQ
# define SAM3U_IRQ_GPIOA_PINS (SAM3U_IRQ_EXTINT+SAM3U_IRQ_NEXTINT)
# define SAM3U_IRQ_PA0 (SAM3U_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM3U_IRQ_PA1 (SAM3U_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM3U_IRQ_PA2 (SAM3U_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM3U_IRQ_PA3 (SAM3U_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM3U_IRQ_PA4 (SAM3U_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM3U_IRQ_PA5 (SAM3U_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM3U_IRQ_PA6 (SAM3U_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM3U_IRQ_PA7 (SAM3U_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM3U_IRQ_PA8 (SAM3U_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM3U_IRQ_PA9 (SAM3U_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM3U_IRQ_PA10 (SAM3U_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM3U_IRQ_PA11 (SAM3U_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM3U_IRQ_PA12 (SAM3U_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM3U_IRQ_PA13 (SAM3U_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM3U_IRQ_PA14 (SAM3U_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM3U_IRQ_PA15 (SAM3U_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM3U_IRQ_PA16 (SAM3U_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM3U_IRQ_PA17 (SAM3U_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM3U_IRQ_PA18 (SAM3U_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM3U_IRQ_PA19 (SAM3U_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM3U_IRQ_PA20 (SAM3U_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM3U_IRQ_PA21 (SAM3U_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM3U_IRQ_PA22 (SAM3U_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM3U_IRQ_PA23 (SAM3U_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM3U_IRQ_PA24 (SAM3U_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM3U_IRQ_PA25 (SAM3U_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM3U_IRQ_PA26 (SAM3U_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM3U_IRQ_PA27 (SAM3U_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM3U_IRQ_PA28 (SAM3U_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM3U_IRQ_PA29 (SAM3U_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM3U_IRQ_PA30 (SAM3U_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM3U_IRQ_PA31 (SAM3U_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM3U_NGPIOAIRQS 32
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM3U_NGPIOAIRQS 0
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_GPIOB_IRQ
# define SAM3U_IRQ_GPIOB_PINS (SAM3U_IRQ_EXTINT+SAM3U_IRQ_NEXTINT+SAM3U_IRQ_GPIOA_PINS)
# define SAM3U_IRQ_PB0 (SAM3U_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM3U_IRQ_PB1 (SAM3U_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM3U_IRQ_PB2 (SAM3U_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM3U_IRQ_PB3 (SAM3U_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM3U_IRQ_PB4 (SAM3U_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM3U_IRQ_PB5 (SAM3U_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM3U_IRQ_PB6 (SAM3U_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM3U_IRQ_PB7 (SAM3U_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM3U_IRQ_PB8 (SAM3U_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM3U_IRQ_PB9 (SAM3U_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM3U_IRQ_PB10 (SAM3U_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM3U_IRQ_PB11 (SAM3U_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM3U_IRQ_PB12 (SAM3U_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM3U_IRQ_PB13 (SAM3U_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM3U_IRQ_PB14 (SAM3U_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM3U_IRQ_PB15 (SAM3U_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM3U_IRQ_PB16 (SAM3U_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM3U_IRQ_PB17 (SAM3U_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM3U_IRQ_PB18 (SAM3U_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM3U_IRQ_PB19 (SAM3U_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM3U_IRQ_PB20 (SAM3U_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM3U_IRQ_PB21 (SAM3U_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM3U_IRQ_PB22 (SAM3U_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM3U_IRQ_PB23 (SAM3U_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM3U_IRQ_PB24 (SAM3U_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM3U_IRQ_PB25 (SAM3U_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM3U_IRQ_PB26 (SAM3U_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM3U_IRQ_PB27 (SAM3U_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM3U_IRQ_PB28 (SAM3U_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM3U_IRQ_PB29 (SAM3U_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM3U_IRQ_PB30 (SAM3U_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM3U_IRQ_PB31 (SAM3U_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM3U_NGPIOAIRQS 32
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM3U_NGPIOBIRQS 0
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_GPIOC_IRQ
# define SAM3U_IRQ_GPIOC_PINS (SAM3U_IRQ_EXTINT+SAM3U_IRQ_NEXTINT+SAM3U_IRQ_GPIOA_PINS+SAM3U_IRQ_GPIOB_PINS)
# define SAM3U_IRQ_PC0 (SAM3U_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM3U_IRQ_PC1 (SAM3U_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM3U_IRQ_PC2 (SAM3U_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM3U_IRQ_PC3 (SAM3U_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM3U_IRQ_PC4 (SAM3U_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM3U_IRQ_PC5 (SAM3U_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM3U_IRQ_PC6 (SAM3U_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM3U_IRQ_PC7 (SAM3U_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM3U_IRQ_PC8 (SAM3U_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM3U_IRQ_PC9 (SAM3U_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM3U_IRQ_PC10 (SAM3U_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM3U_IRQ_PC11 (SAM3U_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM3U_IRQ_PC12 (SAM3U_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM3U_IRQ_PC13 (SAM3U_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM3U_IRQ_PC14 (SAM3U_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM3U_IRQ_PC15 (SAM3U_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM3U_IRQ_PC16 (SAM3U_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM3U_IRQ_PC17 (SAM3U_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM3U_IRQ_PC18 (SAM3U_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM3U_IRQ_PC19 (SAM3U_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM3U_IRQ_PC20 (SAM3U_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM3U_IRQ_PC21 (SAM3U_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM3U_IRQ_PC22 (SAM3U_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM3U_IRQ_PC23 (SAM3U_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM3U_IRQ_PC24 (SAM3U_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM3U_IRQ_PC25 (SAM3U_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM3U_IRQ_PC26 (SAM3U_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM3U_IRQ_PC27 (SAM3U_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM3U_IRQ_PC28 (SAM3U_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM3U_IRQ_PC29 (SAM3U_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM3U_IRQ_PC30 (SAM3U_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM3U_IRQ_PC31 (SAM3U_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM3U_NGPIOAIRQS 32
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+SAM_IRQ_GPIOA_PINS+SAM_IRQ_GPIOB_PINS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM3U_NGPIOCIRQS 0
# define SAM_NGPIOCIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (SAM3U_IRQ_EXTINT+SAM3U_IRQ_NEXTINT+\
SAM3U_NGPIOAIRQS+SAM3U_NGPIOBIRQS+SAM3U_NGPIOCIRQS)
#define NR_IRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT+\
SAM_NGPIOAIRQS+SAM_NGPIOBIRQS+SAM_NGPIOCIRQS)
/****************************************************************************************
* Public Types
arch/arm/src/sam3u/Kconfig
+23 -14
View File
@@ -3,54 +3,63 @@
# see misc/tools/kconfig-language.txt.
#
comment "AT91SAM3 Configuration Options"
comment "AT91SAM3/SAM4 Configuration Options"
choice
prompt "AT91SAM3 Chip Selection"
default ARCH_CHIP_AT91SAM3U4E
depends on ARCH_CHIP_SAM3U
depends on ARCH_CHIP_SAM34
config ARCH_CHIP_AT91SAM3U4E
bool "AT91SAM3U4E"
select ARCH_CORTEXM3
select ARCH_CHIP_SAM3U
endchoice
config ARCH_CHIP_SAM3U
bool
menu "AT91SAM3 Peripheral Support"
config SAM3U_DMA
config SAM34_DMA
bool "DMA"
default n
select ARCH_DMA
config SAM3U_NAND
config SAM34_NAND
bool "NAND support"
default n
config SAM3U_HSMCI
config SAM34_HSMCI
bool "HSMCI"
default n
config SAM3U_UART
config SAM34_UART
bool "UART"
default y
select ARCH_HAVE_UART
config SAM3U_USART0
config SAM34_USART0
bool "USART0"
default n
config SAM3U_USART1
config SAM34_USART1
bool "USART1"
default n
config SAM3U_USART2
config SAM34_USART2
bool "USART2"
default n
config SAM3U_USART3
config SAM34_USART3
bool "USART3"
default n
config SAM34_SPI
bool "SPI"
default n
endmenu
menu "AT91SAM3 UART Configuration"
@@ -58,25 +67,25 @@ menu "AT91SAM3 UART Configuration"
config USART0_ISUART
bool "USART0 is a UART"
default y
depends on SAM3U_USART0
depends on SAM34_USART0
select ARCH_HAVE_USART0
config USART1_ISUART
bool "USART1 is a UART"
default y
depends on SAM3U_USART1
depends on SAM34_USART1
select ARCH_HAVE_USART1
config USART2_ISUART
bool "USART2 is a UART"
default n
depends on SAM3U_USART2
depends on SAM34_USART2
select ARCH_HAVE_USART2
config USART3_ISUART
bool "USART3 is a UART"
default y
depends on SAM3U_USART3
depends on SAM34_USART3
select ARCH_HAVE_USART2
endmenu
arch/arm/src/sam3u/Make.defs
+6 -6
View File
@@ -74,27 +74,27 @@ ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
endif
# Required SAM3U files
# Required SAM3/4 files
CHIP_ASRCS =
CHIP_ASRCS =
CHIP_CSRCS = sam3u_allocateheap.c sam3u_clockconfig.c sam3u_gpioirq.c
CHIP_CSRCS += sam3u_irq.c sam3u_lowputc.c sam3u_pio.c sam3u_serial.c
CHIP_CSRCS += sam3u_start.c sam3u_timerisr.c
# Configuration-dependent SAM3U files
# Configuration-dependent SAM3/4 files
ifeq ($(CONFIG_NUTTX_KERNEL),y)
CHIP_CSRCS += sam3u_userspace.c sam3u_mpuinit.c
endif
ifeq ($(CONFIG_SAM3U_DMA),y)
ifeq ($(CONFIG_SAM34_DMA),y)
CHIP_CSRCS += sam3u_dmac.c
endif
ifeq ($(CONFIG_SAM3U_HSMCI),y)
ifeq ($(CONFIG_SAM34_HSMCI),y)
CHIP_CSRCS += sam3u_hsmci.c
endif
ifeq ($(CONFIG_SAM3U_SPI),y)
ifeq ($(CONFIG_SAM34_SPI),y)
CHIP_CSRCS += sam3u_spi.c
endif
arch/arm/src/sam3u/chip.h
+1 -1
View File
@@ -47,7 +47,7 @@
*/
#include <arch/sam3u/chip.h>
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
arch/arm/src/sam3u/chip/sam3u_memorymap.h
+145
View File
@@ -0,0 +1,145 @@
/************************************************************************************************
* arch/arm/src/sam3u/chip/sam3u_memorymap.h
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
/************************************************************************************************
* Included Files
************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
# define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */
# define SAM_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */
# define SAM_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */
# define SAM_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */
/* 0x00200000-0x1fffffff: Reserved */
#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
# define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */
# define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */
# define SAM_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */
# define SAM_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */
/* 0x20200000-0x2fffffff: Undefined */
# define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
/* 0x24000000-0x3fffffff: Undefined */
#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
# define SAM_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
# define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */
# define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
/* 0x4000c000-0x4007ffff: Reserved */
# define SAM_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */
# define SAM_TCN_BASE(n) (0x40080000+((n)<<6))
# define SAM_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */
# define SAM_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */
# define SAM_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */
# define SAM_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */
# define SAM_TWIN_BASE(n) (0x40084000+((n)<<14))
# define SAM_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */
# define SAM_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */
# define SAM_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */
# define SAM_USARTN_BASE(n) (0x40090000+((n)<<14))
# define SAM_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */
# define SAM_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */
# define SAM_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */
# define SAM_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */
/* 0x400a0000-0x400a3fff: Reserved */
# define SAM_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */
# define SAM_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */
# define SAM_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */
# define SAM_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */
/* 0x400b4000-0x400dffff: Reserved */
# define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */
/* 0x400e2600-0x400fffff: Reserved */
/* 0x40100000-0x41ffffff: Reserved */
# define SAM_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */
/* 0x44000000-0x5fffffff: Reserved */
#define SAM_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */
# define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
# define SAM_EXTCSN_BASE(n) (0x60000000*((n)<<24))
# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */
# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x67ffffff: Reserved */
# define SAM_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */
/* 0x69000000-0x9fffffff: Reserved */
/* 0xa0000000-0xdfffffff: Reserved */
#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */
#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
#define SAM_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */
#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */
#define SAM_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/
# define SAM_EEFCN_BASE(n) (0x400e0800+((n)<<9))
# define SAM_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
# define SAM_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
#define SAM_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */
# define SAM_PION_BASE(n) (0x400e0c00+((n)<<9))
# define SAM_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
# define SAM_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
# define SAM_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
#define SAM_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */
#define SAM_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */
#define SAM_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */
#define SAM_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */
#define SAM_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */
/* 0x490e1400-0x4007ffff: Reserved */
/************************************************************************************************
* Public Types
************************************************************************************************/
/************************************************************************************************
* Public Data
************************************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */
arch/arm/src/sam3u/chip/sam_adc.h
+236
View File
@@ -0,0 +1,236 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_adc.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM_CHIP_SAM_ADC_H
#define __ARCH_ARM_SRC_SAM_CHIP_SAM_ADC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* ADC register offsets ****************************************************************/
#define SAM_ADC_CR_OFFSET 0x00 /* Control Register (Both) */
#define SAM_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */
/* 0x08: Reserved */
/* 0x0c: Reserved */
#define SAM_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */
#define SAM_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */
#define SAM_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */
#define SAM_ADC_SR_OFFSET 0x1c /* Status Register (Both) */
#define SAM_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */
#define SAM_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */
#define SAM_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */
#define SAM_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */
#define SAM_ADC_CDR_OFFSET(n) (0x30+((n)<<2))
#define SAM_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */
#define SAM_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */
#define SAM_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */
#define SAM_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */
#define SAM_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */
#define SAM_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */
#define SAM_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */
#define SAM_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */
#define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
#define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
/* ADC register adresses ***************************************************************/
#define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET)
#define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET)
#define SAM_ADC12B_CHER (SAM_ADC12B_BASE+SAM_ADC_CHER_OFFSET)
#define SAM_ADC12B_CHDR (SAM_ADC12B_BASE+SAM_ADC_CHDR_OFFSET)
#define SAM_ADC12B_CHSR (SAM_ADC12B_BASE+SAM_ADC_CHSR_OFFSET)
#define SAM_ADC12B_SR (SAM_ADC12B_BASE+SAM_ADC_SR_OFFSET)
#define SAM_ADC12B_LCDR_ (SAM_ADC12B_BASE+SAM_ADC_LCDR_OFFSET)
#define SAM_ADC12B_IER (SAM_ADC12B_BASE+SAM_ADC_IER_OFFSET)
#define SAM_ADC12B_IDR (SAM_ADC12B_BASE+SAM_ADC_IDR_OFFSET)
#define SAM_ADC12B_IMR (SAM_ADC12B_BASE+SAM_ADC_IMR_OFFSET)
#define SAM_ADC12B_CDR(n)) (SAM_ADC12B_BASE+SAM_ADC_CDR_OFFSET(n))
#define SAM_ADC12B_CDR0 (SAM_ADC12B_BASE+SAM_ADC_CDR0_OFFSET)
#define SAM_ADC12B_CDR1 (SAM_ADC12B_BASE+SAM_ADC_CDR1_OFFSET)
#define SAM_ADC12B_CDR2 (SAM_ADC12B_BASE+SAM_ADC_CDR2_OFFSET)
#define SAM_ADC12B_CDR3 (SAM_ADC12B_BASE+SAM_ADC_CDR3_OFFSET)
#define SAM_ADC12B_CDR4 (SAM_ADC12B_BASE+SAM_ADC_CDR4_OFFSET)
#define SAM_ADC12B_CDR5 (SAM_ADC12B_BASE+SAM_ADC_CDR5_OFFSET)
#define SAM_ADC12B_CDR6 (SAM_ADC12B_BASE+SAM_ADC_CDR6_OFFSET)
#define SAM_ADC12B_CDR7 (SAM_ADC12B_BASE+SAM_ADC_CDR7_OFFSET)
#define SAM_ADC12B_ACR (SAM_ADC12B_BASE+SAM_ADC12B_ACR_OFFSET)
#define SAM_ADC12B_EMR (SAM_ADC12B_BASE+SAM_ADC12B_EMR_OFFSET)
#define SAM_ADC_CR (SAM_ADC_BASE+SAM_ADC_CR_OFFSET)
#define SAM_ADC_MR (SAM_ADC_BASE+SAM_ADC_MR_OFFSET)
#define SAM_ADC_CHER (SAM_ADC_BASE+SAM_ADC_CHER_OFFSET)
#define SAM_ADC_CHDR (SAM_ADC_BASE+SAM_ADC_CHDR_OFFSET)
#define SAM_ADC_CHSR (SAM_ADC_BASE+SAM_ADC_CHSR_OFFSET)
#define SAM_ADC_SR (SAM_ADC_BASE+SAM_ADC_SR_OFFSET)
#define SAM_ADC_LCDR (SAM_ADC_BASE+SAM_ADC_LCDR_OFFSET)
#define SAM_ADC_IER (SAM_ADC_BASE+SAM_ADC_IER_OFFSET)
#define SAM_ADC_IDR (SAM_ADC_BASE+SAM_ADC_IDR_OFFSET)
#define SAM_ADC_IMR (SAM_ADC_BASE+SAM_ADC_IMR_OFFSET)
#define SAM_ADC_CDR(n)) (SAM_ADC_BASE+SAM_ADC_CDR_OFFSET(n))
#define SAM_ADC_CDR0 (SAM_ADC_BASE+SAM_ADC_CDR0_OFFSET)
#define SAM_ADC_CDR1 (SAM_ADC_BASE+SAM_ADC_CDR1_OFFSET)
#define SAM_ADC_CDR2 (SAM_ADC_BASE+SAM_ADC_CDR2_OFFSET)
#define SAM_ADC_CDR3 (SAM_ADC_BASE+SAM_ADC_CDR3_OFFSET)
#define SAM_ADC_CDR4 (SAM_ADC_BASE+SAM_ADC_CDR4_OFFSET)
#define SAM_ADC_CDR5 (SAM_ADC_BASE+SAM_ADC_CDR5_OFFSET)
#define SAM_ADC_CDR6 (SAM_ADC_BASE+SAM_ADC_CDR6_OFFSET)
#define SAM_ADC_CDR7 (SAM_ADC_BASE+SAM_ADC_CDR7_OFFSET)
/* ADC register bit definitions ********************************************************/
/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */
#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */
#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */
/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */
#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT)
#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */
#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */
#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT)
#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */
#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT
#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */
#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT)
#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */
#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel
* Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register,
* and ADC(10B) Channel Status Register common bit-field definitions
*/
#define ADC_CH(n) (1 << (n))
#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */
#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */
#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */
#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */
#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */
#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */
#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */
#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */
/* ADC12B Analog Control Register (ADC12B only) */
#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */
#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT)
#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */
#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT)
#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */
#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */
/* ADC12B Extended Mode Register (ADC12B only) */
#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */
#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */
#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT)
/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt
* Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register,
* ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and
* ADC(10B) Interrupt Mask Register common bit-field definitions
*/
#define ADC_INT_EOC(n) (1<<(n))
#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */
#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */
#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */
#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */
#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */
#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */
#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */
#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */
#define ADC_INT_OVRE(n) (1<<((n)+8))
#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */
#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */
#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */
#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */
#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */
#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */
#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */
#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */
#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */
#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */
#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */
#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */
/* ADC12B Last Converted Data Register */
#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */
#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT)
/* ADC(10B) Last Converted Data Register */
#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */
#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT)
/* ADC12B Channel Data Register */
#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */
#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT)
/* ADC(10B) Channel Data Register */
#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */
#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM_CHIP_SAM_ADC_H */
arch/arm/src/sam3u/sam3u_chipid.h → arch/arm/src/sam3u/chip/sam_chipid.h
+10 -10
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_chipid.h
* arch/arm/src/sam3u/chip/sam_chipid.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_CHIPID_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_CHIPID_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,13 +51,13 @@
/* CHIPID register offsets **************************************************************/
#define SAM3U_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM3U_CHIPID_EXID 0x04 /* Chip ID Extension Register */
#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */
/* CHIPID register adresses *************************************************************/
#define SAM3U_CHIPID_CIDR (SAM3U_CHIPID_BASE+SAM3U_CHIPID_CIDR)
#define SAM3U_CHIPID_EXID (SAM3U_CHIPID_BASE+SAM3U_CHIPID_EXID)
#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR)
#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID)
/* CHIPID register bit definitions ******************************************************/
@@ -164,4 +164,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_CHIPID_H */
arch/arm/src/sam3u/sam3u_dmac.h → arch/arm/src/sam3u/chip/sam_dmac.h
+126 -127
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_dmac.h
* arch/arm/src/sam3u/chip/sam_dmac.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_DMAC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_DMAC_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -53,97 +53,96 @@
/* Global Registers */
#define SAM3U_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */
#define SAM3U_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */
#define SAM3U_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */
#define SAM3U_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */
#define SAM3U_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */
/* 0x014-0x18: Reserved */
#define SAM3U_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */
#define SAM3U_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */
#define SAM3U_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */
#define SAM3U_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */
#define SAM3U_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */
#define SAM3U_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */
#define SAM3U_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */
/* 0x034-0x38: Reserved */
#define SAM_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */
#define SAM_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */
#define SAM_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */
#define SAM_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */
#define SAM_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */
/* 0x014-0x18: Reserved */
#define SAM_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */
#define SAM_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */
#define SAM_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */
#define SAM_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */
#define SAM_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */
#define SAM_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */
#define SAM_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */
/* 0x034-0x38: Reserved */
/* DMA channel registers */
#define SAM3U_DMACHAN_OFFSET(n) (0x3c+((n)*0x28))
#define SAM3U_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */
#define SAM3U_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */
#define SAM3U_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */
#define SAM3U_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */
#define SAM_DMACHAN_OFFSET(n) (0x3c+((n)*0x28))
#define SAM_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */
#define SAM_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */
#define SAM_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */
#define SAM_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */
#define SAM3U_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */
#define SAM3U_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */
#define SAM3U_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */
#define SAM3U_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */
#define SAM3U_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */
#define SAM3U_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */
/* 0x18-0x24: Reserved */
/* 0x017c-0x1fc: Reserved */
#define SAM_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */
#define SAM_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */
#define SAM_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */
#define SAM_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */
#define SAM_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */
#define SAM_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */
/* 0x18-0x24: Reserved */
/* 0x017c-0x1fc: Reserved */
/* DMAC register adresses ***************************************************************/
/* Global Registers */
#define SAM3U_DMAC_GCFG (SAM3U_DMAC_BASE+SAM3U_DMAC_GCFG_OFFSET)
#define SAM3U_DMAC_EN (SAM3U_DMAC_BASE+SAM3U_DMAC_EN_OFFSET)
#define SAM3U_DMAC_SREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_SREQ_OFFSET)
#define SAM3U_DMAC_CREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_CREQ_OFFSET)
#define SAM3U_DMAC_LAST (SAM3U_DMAC_BASE+SAM3U_DMAC_LAST_OFFSET)
#define SAM3U_DMAC_EBCIER (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIER_OFFSET)
#define SAM3U_DMAC_EBCIDR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIDR_OFFSET)
#define SAM3U_DMAC_EBCIMR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIMR_OFFSET)
#define SAM3U_DMAC_EBCISR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCISR_OFFSET)
#define SAM3U_DMAC_CHER (SAM3U_DMAC_BASE+SAM3U_DMAC_CHER_OFFSET)
#define SAM3U_DMAC_CHDR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHDR_OFFSET)
#define SAM3U_DMAC_CHSR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHSR_OFFSET)
#define SAM_DMAC_GCFG (SAM_DMAC_BASE+SAM_DMAC_GCFG_OFFSET)
#define SAM_DMAC_EN (SAM_DMAC_BASE+SAM_DMAC_EN_OFFSET)
#define SAM_DMAC_SREQ (SAM_DMAC_BASE+SAM_DMAC_SREQ_OFFSET)
#define SAM_DMAC_CREQ (SAM_DMAC_BASE+SAM_DMAC_CREQ_OFFSET)
#define SAM_DMAC_LAST (SAM_DMAC_BASE+SAM_DMAC_LAST_OFFSET)
#define SAM_DMAC_EBCIER (SAM_DMAC_BASE+SAM_DMAC_EBCIER_OFFSET)
#define SAM_DMAC_EBCIDR (SAM_DMAC_BASE+SAM_DMAC_EBCIDR_OFFSET)
#define SAM_DMAC_EBCIMR (SAM_DMAC_BASE+SAM_DMAC_EBCIMR_OFFSET)
#define SAM_DMAC_EBCISR (SAM_DMAC_BASE+SAM_DMAC_EBCISR_OFFSET)
#define SAM_DMAC_CHER (SAM_DMAC_BASE+SAM_DMAC_CHER_OFFSET)
#define SAM_DMAC_CHDR (SAM_DMAC_BASE+SAM_DMAC_CHDR_OFFSET)
#define SAM_DMAC_CHSR (SAM_DMAC_BASE+SAM_DMAC_CHSR_OFFSET)
/* DMA channel registers */
#define SAM3U_DMACHAN_BASE(n) (SAM3U_DMAC_BASE+SAM3U_DMACHAN_OFFSET(n))
#define SAM3U_DMACHAN0_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN0_OFFSET)
#define SAM3U_DMACHAN1_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN1_OFFSET)
#define SAM3U_DMACHAN2_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN2_OFFSET)
#define SAM3U_DMACHAN3_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN3_OFFSET)
#define SAM_DMACHAN_BASE(n) (SAM_DMAC_BASE+SAM_DMACHAN_OFFSET(n))
#define SAM_DMACHAN0_BASE (SAM_DMAC_BASE+SAM_DMACHAN0_OFFSET)
#define SAM_DMACHAN1_BASE (SAM_DMAC_BASE+SAM_DMACHAN1_OFFSET)
#define SAM_DMACHAN2_BASE (SAM_DMAC_BASE+SAM_DMACHAN2_OFFSET)
#define SAM_DMACHAN3_BASE (SAM_DMAC_BASE+SAM_DMACHAN3_OFFSET)
#define SAM3U_DMACHAN_SADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_SADDR_OFFSET)
#define SAM3U_DMACHAN_DADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DADDR_OFFSET)
#define SAM3U_DMACHAN_DSCR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DSCR_OFFSET)
#define SAM3U_DMACHAN_CTRLA(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLA_OFFSET)
#define SAM3U_DMACHAN_CTRLB(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLB_OFFSET)
#define SAM3U_DMACHAN_CFG(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CFG_OFFSET)
#define SAM_DMACHAN_SADDR(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_SADDR_OFFSET)
#define SAM_DMACHAN_DADDR(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_DADDR_OFFSET)
#define SAM_DMACHAN_DSCR(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_DSCR_OFFSET)
#define SAM_DMACHAN_CTRLA(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_CTRLA_OFFSET)
#define SAM_DMACHAN_CTRLB(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_CTRLB_OFFSET)
#define SAM_DMACHAN_CFG(n) (SAM_DMACHAN_BASE(n)+SAM_DMACHAN_CFG_OFFSET)
#define SAM3U_DMACHAN0_SADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
#define SAM3U_DMACHAN0_DADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
#define SAM3U_DMACHAN0_DSCR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
#define SAM3U_DMACHAN0_CTRLA (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
#define SAM3U_DMACHAN0_CTRLB (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
#define SAM3U_DMACHAN0_CFG (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CFG_OFFSET)
#define SAM_DMACHAN0_SADDR (SAM_DMACHAN0_BASE+SAM_DMACHAN_SADDR_OFFSET)
#define SAM_DMACHAN0_DADDR (SAM_DMACHAN0_BASE+SAM_DMACHAN_DADDR_OFFSET)
#define SAM_DMACHAN0_DSCR (SAM_DMACHAN0_BASE+SAM_DMACHAN_DSCR_OFFSET)
#define SAM_DMACHAN0_CTRLA (SAM_DMACHAN0_BASE+SAM_DMACHAN_CTRLA_OFFSET)
#define SAM_DMACHAN0_CTRLB (SAM_DMACHAN0_BASE+SAM_DMACHAN_CTRLB_OFFSET)
#define SAM_DMACHAN0_CFG (SAM_DMACHAN0_BASE+SAM_DMACHAN_CFG_OFFSET)
#define SAM3U_DMACHAN1_SADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
#define SAM3U_DMACHAN1_DADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
#define SAM3U_DMACHAN1_DSCR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
#define SAM3U_DMACHAN1_CTRLA (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
#define SAM3U_DMACHAN1_CTRLB (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
#define SAM3U_DMACHAN1_CFG (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CFG_OFFSET)
#define SAM_DMACHAN1_SADDR (SAM_DMACHAN1_BASE+SAM_DMACHAN_SADDR_OFFSET)
#define SAM_DMACHAN1_DADDR (SAM_DMACHAN1_BASE+SAM_DMACHAN_DADDR_OFFSET)
#define SAM_DMACHAN1_DSCR (SAM_DMACHAN1_BASE+SAM_DMACHAN_DSCR_OFFSET)
#define SAM_DMACHAN1_CTRLA (SAM_DMACHAN1_BASE+SAM_DMACHAN_CTRLA_OFFSET)
#define SAM_DMACHAN1_CTRLB (SAM_DMACHAN1_BASE+SAM_DMACHAN_CTRLB_OFFSET)
#define SAM_DMACHAN1_CFG (SAM_DMACHAN1_BASE+SAM_DMACHAN_CFG_OFFSET)
#define SAM3U_DMACHAN2_SADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
#define SAM3U_DMACHAN2_DADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
#define SAM3U_DMACHAN2_DSCR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
#define SAM3U_DMACHAN2_CTRLA (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
#define SAM3U_DMACHAN2_CTRLB (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
#define SAM3U_DMACHAN2_CFG (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CFG_OFFSET)
#define SAM_DMACHAN2_SADDR (SAM_DMACHAN2_BASE+SAM_DMACHAN_SADDR_OFFSET)
#define SAM_DMACHAN2_DADDR (SAM_DMACHAN2_BASE+SAM_DMACHAN_DADDR_OFFSET)
#define SAM_DMACHAN2_DSCR (SAM_DMACHAN2_BASE+SAM_DMACHAN_DSCR_OFFSET)
#define SAM_DMACHAN2_CTRLA (SAM_DMACHAN2_BASE+SAM_DMACHAN_CTRLA_OFFSET)
#define SAM_DMACHAN2_CTRLB (SAM_DMACHAN2_BASE+SAM_DMACHAN_CTRLB_OFFSET)
#define SAM_DMACHAN2_CFG (SAM_DMACHAN2_BASE+SAM_DMACHAN_CFG_OFFSET)
#define SAM3U_DMACHAN3_SADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_SADDR_OFFSET)
#define SAM3U_DMACHAN3_DADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DADDR_OFFSET)
#define SAM3U_DMACHAN3_DSCR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DSCR_OFFSET)
#define SAM3U_DMACHAN3_CTRLA (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLA_OFFSET)
#define SAM3U_DMACHAN3_CTRLB (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLB_OFFSET)
#define SAM3U_DMACHAN3_CFG (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CFG_OFFSET)
#define SAM_DMACHAN3_SADDR (SAM_DMACHAN3_BASE+SAM_DMACHAN_SADDR_OFFSET)
#define SAM_DMACHAN3_DADDR (SAM_DMACHAN3_BASE+SAM_DMACHAN_DADDR_OFFSET)
#define SAM_DMACHAN3_DSCR (SAM_DMACHAN3_BASE+SAM_DMACHAN_DSCR_OFFSET)
#define SAM_DMACHAN3_CTRLA (SAM_DMACHAN3_BASE+SAM_DMACHAN_CTRLA_OFFSET)
#define SAM_DMACHAN3_CTRLB (SAM_DMACHAN3_BASE+SAM_DMACHAN_CTRLB_OFFSET)
#define SAM_DMACHAN3_CFG (SAM_DMACHAN3_BASE+SAM_DMACHAN_CFG_OFFSET)
/* DMAC register bit definitions ********************************************************/
@@ -198,16 +197,16 @@
#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */
# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))
# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT)
# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT)
# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT)
# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT)
# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT))
# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT))
# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT))
# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT))
#define DMAC_CREQ_DCREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination chunk transfer */
# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n))))
# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT)
# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT)
# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT)
# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT)
# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))
# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT))
# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT))
# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT))
# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT))
/* DMAC Software Last Transfer Flag Register */
@@ -368,46 +367,46 @@
/* DMAC Channel n [n = 0..3] Control B Register */
#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */
#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */
#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */
#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT)
# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */
# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */
# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */
# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */
#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */
#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */
#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */
#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT)
# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */
# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */
# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */
# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */
#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
/* DMAC Channel n [n = 0..3] Configuration Register */
#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */
#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT)
#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */
#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT)
#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */
#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */
#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */
#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */
#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */
#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */
#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */
#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT)
#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT)
# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */
# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */
# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */
#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */
#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT)
#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */
#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT)
#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */
#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */
#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */
#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */
#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */
#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */
#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */
#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT)
#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT)
# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */
# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */
# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */
/* DMA Peripheral IDs *******************************************************************/
@@ -438,4 +437,4 @@ struct dma_linklist_s
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_DMAC_H */
arch/arm/src/sam3u/chip/sam_eefc.h
+120
View File
@@ -0,0 +1,120 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_eefc.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_EEFC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_EEFC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* EEFC register offsets ****************************************************************/
#define SAM_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */
#define SAM_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */
#define SAM_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
#define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
/* EEFC register adresses ***************************************************************/
#define SAM_EEFC_FMR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FMR_OFFSET)
#define SAM_EEFC_FCR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FCR_OFFSET)
#define SAM_EEFC_FSR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FSR_OFFSET)
#define SAM_EEFC_FRR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FRR_OFFSET)
#define SAM_EEFC0_FMR (SAM_EEFC0_BASE+SAM_EEFC_FMR_OFFSET)
#define SAM_EEFC0_FCR (SAM_EEFC0_BASE+SAM_EEFC_FCR_OFFSET)
#define SAM_EEFC0_FSR (SAM_EEFC0_BASE+SAM_EEFC_FSR_OFFSET)
#define SAM_EEFC0_FRR (SAM_EEFC0_BASE+SAM_EEFC_FRR_OFFSET)
#define SAM_EEFC1_FMR (SAM_EEFC1_BASE+SAM_EEFC_FMR_OFFSET)
#define SAM_EEFC1_FCR (SAM_EEFC1_BASE+SAM_EEFC_FCR_OFFSET)
#define SAM_EEFC1_FSR (SAM_EEFC1_BASE+SAM_EEFC_FSR_OFFSET)
#define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET)
/* EEFC register bit definitions ********************************************************/
#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */
#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT)
#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */
#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */
#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT)
# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */
# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */
# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */
# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */
# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */
# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */
# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */
# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */
# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */
# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */
# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */
# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */
# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */
# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */
#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */
#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT)
#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */
#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT)
#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */
#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */
#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_EEFC_H */
arch/arm/src/sam3u/sam3u_gpbr.h → arch/arm/src/sam3u/chip/sam_gpbr.h
+24 -24
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_gpbr.h
* arch/arm/src/sam3u/chip/sam_gpbr.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_GPBR_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_GPBR_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,27 +51,27 @@
/* GPBR register offsets ****************************************************************/
#define SAM3U_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */
#define SAM3U_GPBR0_OFFSET 0x00
#define SAM3U_GPBR1_OFFSET 0x04
#define SAM3U_GPBR2_OFFSET 0x08
#define SAM3U_GPBR3_OFFSET 0x0c
#define SAM3U_GPBR4_OFFSET 0x10
#define SAM3U_GPBR5_OFFSET 0x14
#define SAM3U_GPBR6_OFFSET 0x18
#define SAM3U_GPBR7_OFFSET 0x1c
#define SAM_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */
#define SAM_GPBR0_OFFSET 0x00
#define SAM_GPBR1_OFFSET 0x04
#define SAM_GPBR2_OFFSET 0x08
#define SAM_GPBR3_OFFSET 0x0c
#define SAM_GPBR4_OFFSET 0x10
#define SAM_GPBR5_OFFSET 0x14
#define SAM_GPBR6_OFFSET 0x18
#define SAM_GPBR7_OFFSET 0x1c
/* GPBR register adresses ***************************************************************/
#define SAM3U_GPBR(n)) (SAM3U_GPBR_BASE+SAM3U_GPBR_OFFSET(n))
#define SAM3U_GPBR0 (SAM3U_GPBR_BASE+SAM3U_GPBR0_OFFSET)
#define SAM3U_GPBR1 (SAM3U_GPBR_BASE+SAM3U_GPBR1_OFFSET)
#define SAM3U_GPBR2 (SAM3U_GPBR_BASE+SAM3U_GPBR2_OFFSET)
#define SAM3U_GPBR3 (SAM3U_GPBR_BASE+SAM3U_GPBR3_OFFSET)
#define SAM3U_GPBR4 (SAM3U_GPBR_BASE+SAM3U_GPBR4_OFFSET)
#define SAM3U_GPBR5 (SAM3U_GPBR_BASE+SAM3U_GPBR5_OFFSET)
#define SAM3U_GPBR6 (SAM3U_GPBR_BASE+SAM3U_GPBR6_OFFSET)
#define SAM3U_GPBR7 (SAM3U_GPBR_BASE+SAM3U_GPBR7_OFFSET)
#define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n))
#define SAM_GPBR0 (SAM_GPBR_BASE+SAM_GPBR0_OFFSET)
#define SAM_GPBR1 (SAM_GPBR_BASE+SAM_GPBR1_OFFSET)
#define SAM_GPBR2 (SAM_GPBR_BASE+SAM_GPBR2_OFFSET)
#define SAM_GPBR3 (SAM_GPBR_BASE+SAM_GPBR3_OFFSET)
#define SAM_GPBR4 (SAM_GPBR_BASE+SAM_GPBR4_OFFSET)
#define SAM_GPBR5 (SAM_GPBR_BASE+SAM_GPBR5_OFFSET)
#define SAM_GPBR6 (SAM_GPBR_BASE+SAM_GPBR6_OFFSET)
#define SAM_GPBR7 (SAM_GPBR_BASE+SAM_GPBR7_OFFSET)
/* GPBR register bit definitions ********************************************************/
@@ -87,4 +87,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_GPBR_H */
arch/arm/src/sam3u/chip/sam_hsmci.h
+297
View File
@@ -0,0 +1,297 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_hsmci.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_HSMCI_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_HSMCI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* HSMCI register offsets ***************************************************************/
#define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */
#define SAM_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */
#define SAM_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */
#define SAM_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */
#define SAM_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */
#define SAM_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */
#define SAM_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */
#define SAM_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */
#define SAM_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */
#define SAM_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */
#define SAM_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */
#define SAM_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */
/* 0x0038-0x003c: Reserved */
#define SAM_HSMCI_SR_OFFSET 0x0040 /* Status Register */
#define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */
#define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */
#define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */
#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */
#define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */
/* 0x0058-0x00e0: Reserved */
#define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */
#define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
/* 0x00ec-0x00fc: Reserved */
/* 0x0100-0x0124: Reserved */
#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */
/* HSMCI register adresses **************************************************************/
#define SAM_HSMCI_CR (SAM_MCI_BASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI_MR (SAM_MCI_BASE+SAM_HSMCI_MR_OFFSET)
#define SAM_HSMCI_DTOR (SAM_MCI_BASE+SAM_HSMCI_DTOR_OFFSET)
#define SAM_HSMCI_SDCR (SAM_MCI_BASE+SAM_HSMCI_SDCR_OFFSET)
#define SAM_HSMCI_ARGR (SAM_MCI_BASE+SAM_HSMCI_ARGR_OFFSET)
#define SAM_HSMCI_CMDR (SAM_MCI_BASE+SAM_HSMCI_CMDR_OFFSET)
#define SAM_HSMCI_BLKR (SAM_MCI_BASE+SAM_HSMCI_BLKR_OFFSET)
#define SAM_HSMCI_CSTOR (SAM_MCI_BASE+SAM_HSMCI_CSTOR_OFFSET)
#define SAM_HSMCI_RSPR0 (SAM_MCI_BASE+SAM_HSMCI_RSPR0_OFFSET)
#define SAM_HSMCI_RSPR1 (SAM_MCI_BASE+SAM_HSMCI_RSPR1_OFFSET)
#define SAM_HSMCI_RSPR2 (SAM_MCI_BASE+SAM_HSMCI_RSPR2_OFFSET)
#define SAM_HSMCI_RSPR3 (SAM_MCI_BASE+SAM_HSMCI_RSPR3_OFFSET)
#define SAM_HSMCI_RDR (SAM_MCI_BASE+SAM_HSMCI_RDR_OFFSET)
#define SAM_HSMCI_TDR (SAM_MCI_BASE+SAM_HSMCI_TDR_OFFSET)
#define SAM_HSMCI_SR (SAM_MCI_BASE+SAM_HSMCI_SR_OFFSET)
#define SAM_HSMCI_IER (SAM_MCI_BASE+SAM_HSMCI_IER_OFFSET)
#define SAM_HSMCI_IDR (SAM_MCI_BASE+SAM_HSMCI_IDR_OFFSET)
#define SAM_HSMCI_IMR (SAM_MCI_BASE+SAM_HSMCI_IMR_OFFSET)
#define SAM_HSMCI_DMA (SAM_MCI_BASE+SAM_HSMCI_DMA_OFFSET)
#define SAM_HSMCI_CFG (SAM_MCI_BASE+SAM_HSMCI_CFG_OFFSET)
#define SAM_HSMCI_WPMR (SAM_MCI_BASE+SAM_HSMCI_WPMR_OFFSET)
#define SAM_HSMCI_WPSR (SAM_MCI_BASE+SAM_HSMCI_WPSR_OFFSET)
#define SAM_HSMCI_FIFO (SAM_MCI_BASE+SAM_HSMCI_FIFO_OFFSET)
/* HSMCI register bit definitions *******************************************************/
/* HSMCI Control Register */
#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */
#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */
#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */
#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */
#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
/* HSMCI Mode Register */
#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */
#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT)
/* HSMCI Data Timeout Register */
#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */
#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT)
# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT)
#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */
#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT)
/* HSMCI SDCard/SDIO Register */
#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */
#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT)
# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT)
#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */
#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT)
/* HSMCI Command Register */
#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */
#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT)
#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */
#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT)
# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */
# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */
# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */
# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */
# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT)
# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */
#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT)
# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */
# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */
# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */
/* HSMCI Block Register */
#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
/* HSMCI Completion Signal Timeout Register */
#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
* Register, and HSMCI Interrupt Mask Register common bit-field definitions
*/
#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */
#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */
#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */
#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */
#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */
#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */
#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */
#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */
#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */
#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */
#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */
#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */
#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */
#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */
#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */
#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */
#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */
#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */
#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */
#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */
/* HSMCI DMA Configuration Register */
#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */
#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT)
#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */
#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */
#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */
/* HSMCI Configuration Register */
#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */
#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */
#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */
#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */
/* HSMCI Write Protect Mode Register */
#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */
#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT)
/* HSMCI Write Protect Status Register */
#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT)
#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_HSMCI_H */
arch/arm/src/sam3u/chip/sam_matrix.h
+214
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@@ -0,0 +1,214 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_matric.h
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MATRIX_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MATRIX_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* MATRIX register offsets **************************************************************/
#define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2)
#define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
#define SAM_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */
#define SAM_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
#define SAM_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
#define SAM_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
/* 0x0014-0x003c: Reserved */
#define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
#define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
#define SAM_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
#define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
#define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
#define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
#define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
#define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
#define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
#define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
#define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
/* 0x0068-0x007c: Reserved */
#define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3))
#define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
/* 0x0084: Reserved */
#define SAM_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
/* 0x008c: Reserved */
#define SAM_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
/* 0x0094: Reserved */
#define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
/* 0x009c: Reserved */
#define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
/* 0x00a4: Reserved */
#define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
/* 0x00ac: Reserved */
#define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
/* 0x00b4: Reserved */
#define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
/* 0x00bc: Reserved */
#define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
/* 0x00c4: Reserved */
#define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
/* 0x00cc-0x00fc: Reserved */
#define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
/* 0x0104-0x010c: Reserved */
#define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
/* 0x0110 - 0x01fc: Reserved */
/* MATRIX register adresses *************************************************************/
#define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n))
#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET)
#define SAM_MATRIX_MCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG1_OFFSET)
#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET)
#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET)
#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET)
#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n))
#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET)
#define SAM_MATRIX_SCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET)
#define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET)
#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET)
#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET)
#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET)
#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET)
#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET)
#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET)
#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET)
#define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n))
#define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET)
#define SAM_MATRIX_PRAS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS1_OFFSET)
#define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET)
#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET)
#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET)
#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET)
#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET)
#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET)
#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET)
#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET)
#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET)
#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET)
#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET)
/* MATRIX register bit definitions ******************************************************/
#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */
#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */
# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */
# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */
#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2)
#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */
#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
#define MATRIX_MRCR_RCB(x) (1 << (x))
#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */
#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */
#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */
#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */
#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */
#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */
#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT)
#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */
#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MATRIX_H */
arch/arm/src/sam3u/chip/sam_memorymap.h
+49
View File
@@ -0,0 +1,49 @@
/************************************************************************************
* arch/arm/src/sam3u/chip/sam_memorymap.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MEMORYMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam3u_memorymap.h"
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_MEMORYMAP_H */
arch/arm/src/sam3u/sam3u_pdc.h → arch/arm/src/sam3u/chip/sam_pdc.h
+16 -16
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_pdc.h
* arch/arm/src/sam3u/chip/sam_pdc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PDC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PDC_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,16 +51,16 @@
/* PDC register offsets *****************************************************************/
#define SAM3U_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */
#define SAM3U_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */
#define SAM3U_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */
#define SAM3U_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */
#define SAM3U_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */
#define SAM3U_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */
#define SAM3U_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */
#define SAM3U_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */
#define SAM3U_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */
#define SAM3U_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */
#define SAM_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */
#define SAM_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */
#define SAM_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */
#define SAM_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */
#define SAM_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */
#define SAM_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */
#define SAM_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */
#define SAM_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */
#define SAM_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */
#define SAM_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */
/* PDC register adresses ****************************************************************/
@@ -100,4 +100,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PDC_H */
arch/arm/src/sam3u/chip/sam_pio.h
+324
View File
@@ -0,0 +1,324 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_pio.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PIO_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PIO_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* PIO register offsets *****************************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
#define SAM_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */
/* 0x000c: Reserved */
#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */
#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */
#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */
/* 0x001c: Reserved */
#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */
#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */
#define SAM_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */
/* 0x002c: Reserved */
#define SAM_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */
#define SAM_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */
#define SAM_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */
#define SAM_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */
#define SAM_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */
#define SAM_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
#define SAM_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
#define SAM_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define SAM_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */
#define SAM_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */
#define SAM_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */
/* 0x005c: Reserved */
#define SAM_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */
#define SAM_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */
#define SAM_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */
/* 0x006c: Reserved */
#define SAM_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */
/* 0x0074-0x007c: Reserved */
#define SAM_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */
#define SAM_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */
#define SAM_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */
#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */
/* 0x0090-0x009c: Reserved */
#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */
#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */
#define SAM_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */
/* 0x00ac: Reserved */
#define SAM_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */
#define SAM_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */
#define SAM_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */
/* 0x00bc: Reserved */
#define SAM_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */
#define SAM_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */
#define SAM_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */
/* 0x00cc: Reserved */
#define SAM_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */
#define SAM_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */
#define SAM_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */
/* 0x00dc: Reserved */
#define SAM_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */
#define SAM_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* 0x00ec-0x00f8: Reserved */
/* 0x0100-0x0144: Reserved */
/* PIO register adresses ****************************************************************/
#define PIOA (0)
#define PIOB (1)
#define PIOC (2)
#define NPIO (3)
#define SAM_PIO_PER(n) (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET)
#define SAM_PIO_PDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET)
#define SAM_PIO_PSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PSR_OFFSET)
#define SAM_PIO_OER(n) (SAM_PIO_BASE(n)+SAM_PIO_OER_OFFSET)
#define SAM_PIO_ODR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODR_OFFSET)
#define SAM_PIO_OSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OSR_OFFSET)
#define SAM_PIO_IFER(n) (SAM_PIO_BASE(n)+SAM_PIO_IFER_OFFSET)
#define SAM_PIO_IFDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDR_OFFSET)
#define SAM_PIO_IFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFSR_OFFSET)
#define SAM_PIO_SODR(n) (SAM_PIO_BASE(n)+SAM_PIO_SODR_OFFSET)
#define SAM_PIO_CODR(n) (SAM_PIO_BASE(n)+SAM_PIO_CODR_OFFSET)
#define SAM_PIO_ODSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ODSR_OFFSET)
#define SAM_PIO_PDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDSR_OFFSET)
#define SAM_PIO_IER(n) (SAM_PIO_BASE(n)+SAM_PIO_IER_OFFSET)
#define SAM_PIO_IDR(n) (SAM_PIO_BASE(n)+SAM_PIO_IDR_OFFSET)
#define SAM_PIO_IMR(n) (SAM_PIO_BASE(n)+SAM_PIO_IMR_OFFSET)
#define SAM_PIO_ISR(n) (SAM_PIO_BASE(n)+SAM_PIO_ISR_OFFSET)
#define SAM_PIO_MDER(n) (SAM_PIO_BASE(n)+SAM_PIO_MDER_OFFSET)
#define SAM_PIO_MDDR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDDR_OFFSET)
#define SAM_PIO_MDSR(n) (SAM_PIO_BASE(n)+SAM_PIO_MDSR_OFFSET)
#define SAM_PIO_PUDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUDR_OFFSET)
#define SAM_PIO_PUER(n) (SAM_PIO_BASE(n)+SAM_PIO_PUER_OFFSET)
#define SAM_PIO_PUSR(n) (SAM_PIO_BASE(n)+SAM_PIO_PUSR_OFFSET)
#define SAM_PIO_ABSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ABSR_OFFSET)
#define SAM_PIO_SCIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCIFSR_OFFSET)
#define SAM_PIO_DIFSR(n) (SAM_PIO_BASE(n)+SAM_PIO_DIFSR_OFFSET)
#define SAM_PIO_IFDGSR(n) (SAM_PIO_BASE(n)+SAM_PIO_IFDGSR_OFFSET)
#define SAM_PIO_SCDR(n) (SAM_PIO_BASE(n)+SAM_PIO_SCDR_OFFSET)
#define SAM_PIO_OWER(n) (SAM_PIO_BASE(n)+SAM_PIO_OWER_OFFSET)
#define SAM_PIO_OWDR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWDR_OFFSET)
#define SAM_PIO_OWSR(n) (SAM_PIO_BASE(n)+SAM_PIO_OWSR_OFFSET)
#define SAM_PIO_AIMER(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMER_OFFSET)
#define SAM_PIO_AIMDR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIO_AIMMR(n) (SAM_PIO_BASE(n)+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIO_ESR(n) (SAM_PIO_BASE(n)+SAM_PIO_ESR_OFFSET)
#define SAM_PIO_LSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LSR_OFFSET)
#define SAM_PIO_ELSR(n) (SAM_PIO_BASE(n)+SAM_PIO_ELSR_OFFSET)
#define SAM_PIO_FELLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIO_REHLSR(n) (SAM_PIO_BASE(n)+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIO_FRLHSR(n) (SAM_PIO_BASE(n)+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIO_LOCKSR(n) (SAM_PIO_BASE(n)+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIO_WPMR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPMR_OFFSET)
#define SAM_PIO_WPSR(n) (SAM_PIO_BASE(n)+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOA_PER (SAM_PIOA_BASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOA_PDR (SAM_PIOA_BASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOA_PSR (SAM_PIOA_BASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOA_OER (SAM_PIOA_BASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOA_ODR (SAM_PIOA_BASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOA_OSR (SAM_PIOA_BASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOA_IFER (SAM_PIOA_BASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOA_IFDR (SAM_PIOA_BASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOA_IFSR (SAM_PIOA_BASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOA_SODR (SAM_PIOA_BASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOA_CODR (SAM_PIOA_BASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOA_ODSR (SAM_PIOA_BASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOA_PDSR (SAM_PIOA_BASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOA_IER (SAM_PIOA_BASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOA_IDR (SAM_PIOA_BASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOA_IMR (SAM_PIOA_BASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOA_ISR (SAM_PIOA_BASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOA_MDER (SAM_PIOA_BASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOA_MDDR (SAM_PIOA_BASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOA_MDSR (SAM_PIOA_BASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOA_PUDR (SAM_PIOA_BASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOA_PUER (SAM_PIOA_BASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOA_PUSR (SAM_PIOA_BASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOA_ABSR (SAM_PIOA_BASE+SAM_PIO_ABSR_OFFSET)
#define SAM_PIOA_SCIFSR (SAM_PIOA_BASE+SAM_PIO_SCIFSR_OFFSET)
#define SAM_PIOA_DIFSR (SAM_PIOA_BASE+SAM_PIO_DIFSR_OFFSET)
#define SAM_PIOA_IFDGSR (SAM_PIOA_BASE+SAM_PIO_IFDGSR_OFFSET)
#define SAM_PIOA_SCDR (SAM_PIOA_BASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOA_OWER (SAM_PIOA_BASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOA_OWDR (SAM_PIOA_BASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOA_OWSR (SAM_PIOA_BASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOA_AIMER (SAM_PIOA_BASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOA_AIMDR (SAM_PIOA_BASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOA_AIMMR (SAM_PIOA_BASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOA_ESR (SAM_PIOA_BASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOA_LSR (SAM_PIOA_BASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOA_ELSR (SAM_PIOA_BASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOA_FELLSR (SAM_PIOA_BASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOA_REHLSR (SAM_PIOA_BASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOA_FRLHSR (SAM_PIOA_BASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOA_LOCKSR (SAM_PIOA_BASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOA_WPMR (SAM_PIOA_BASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOA_WPSR (SAM_PIOA_BASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOB_PER (SAM_PIOB_BASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOB_PDR_ (SAM_PIOB_BASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOB_PSR (SAM_PIOB_BASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOB_OER (SAM_PIOB_BASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOB_ODR (SAM_PIOB_BASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOB_OSR (SAM_PIOB_BASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOB_IFER (SAM_PIOB_BASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOB_IFDR (SAM_PIOB_BASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOB_IFSR (SAM_PIOB_BASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOB_SODR (SAM_PIOB_BASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOB_CODR (SAM_PIOB_BASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOB_ODSR (SAM_PIOB_BASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOB_PDSR (SAM_PIOB_BASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOB_IER (SAM_PIOB_BASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOB_IDR (SAM_PIOB_BASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOB_IMR (SAM_PIOB_BASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOB_ISR (SAM_PIOB_BASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOB_MDER (SAM_PIOB_BASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOB_MDDR (SAM_PIOB_BASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOB_MDSR (SAM_PIOB_BASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOB_PUDR (SAM_PIOB_BASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOB_PUER (SAM_PIOB_BASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOB_PUSR (SAM_PIOB_BASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOB_ABSR (SAM_PIOB_BASE+SAM_PIO_ABSR_OFFSET)
#define SAM_PIOB_SCIFSR (SAM_PIOB_BASE+SAM_PIO_SCIFSR_OFFSET)
#define SAM_PIOB_DIFSR (SAM_PIOB_BASE+SAM_PIO_DIFSR_OFFSET)
#define SAM_PIOB_IFDGSR (SAM_PIOB_BASE+SAM_PIO_IFDGSR_OFFSET)
#define SAM_PIOB_SCDR (SAM_PIOB_BASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOB_OWER (SAM_PIOB_BASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOB_OWDR (SAM_PIOB_BASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOB_OWSR (SAM_PIOB_BASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOB_AIMER (SAM_PIOB_BASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOB_AIMDR (SAM_PIOB_BASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOB_AIMMR (SAM_PIOB_BASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOB_ESR (SAM_PIOB_BASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOB_LSR (SAM_PIOB_BASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOB_ELSR (SAM_PIOB_BASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOB_FELLSR (SAM_PIOB_BASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOB_REHLSR (SAM_PIOB_BASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOB_FRLHSR (SAM_PIOB_BASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOB_LOCKSR (SAM_PIOB_BASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOB_WPMR (SAM_PIOB_BASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOB_WPSR (SAM_PIOB_BASE+SAM_PIO_WPSR_OFFSET)
#define SAM_PIOC_PER (SAM_PIOC_BASE+SAM_PIO_PER_OFFSET)
#define SAM_PIOC_PDR_ (SAM_PIOC_BASE+SAM_PIO_PDR_OFFSET)
#define SAM_PIOC_PSR (SAM_PIOC_BASE+SAM_PIO_PSR_OFFSET)
#define SAM_PIOC_OER (SAM_PIOC_BASE+SAM_PIO_OER_OFFSET)
#define SAM_PIOC_ODR (SAM_PIOC_BASE+SAM_PIO_ODR_OFFSET)
#define SAM_PIOC_OSR (SAM_PIOC_BASE+SAM_PIO_OSR_OFFSET)
#define SAM_PIOC_IFER (SAM_PIOC_BASE+SAM_PIO_IFER_OFFSET)
#define SAM_PIOC_IFDR (SAM_PIOC_BASE+SAM_PIO_IFDR_OFFSET)
#define SAM_PIOC_IFSR (SAM_PIOC_BASE+SAM_PIO_IFSR_OFFSET)
#define SAM_PIOC_SODR (SAM_PIOC_BASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOC_CODR (SAM_PIOC_BASE+SAM_PIO_CODR_OFFSET)
#define SAM_PIOC_ODSR (SAM_PIOC_BASE+SAM_PIO_ODSR_OFFSET)
#define SAM_PIOC_PDSR (SAM_PIOC_BASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOC_IER (SAM_PIOC_BASE+SAM_PIO_IER_OFFSET)
#define SAM_PIOC_IDR (SAM_PIOC_BASE+SAM_PIO_IDR_OFFSET)
#define SAM_PIOC_IMR (SAM_PIOC_BASE+SAM_PIO_IMR_OFFSET)
#define SAM_PIOC_ISR (SAM_PIOC_BASE+SAM_PIO_ISR_OFFSET)
#define SAM_PIOC_MDER (SAM_PIOC_BASE+SAM_PIO_MDER_OFFSET)
#define SAM_PIOC_MDDR (SAM_PIOC_BASE+SAM_PIO_MDDR_OFFSET)
#define SAM_PIOC_MDSR (SAM_PIOC_BASE+SAM_PIO_MDSR_OFFSET)
#define SAM_PIOC_PUDR (SAM_PIOC_BASE+SAM_PIO_PUDR_OFFSET)
#define SAM_PIOC_PUER (SAM_PIOC_BASE+SAM_PIO_PUER_OFFSET)
#define SAM_PIOC_PUSR (SAM_PIOC_BASE+SAM_PIO_PUSR_OFFSET)
#define SAM_PIOC_ABSR (SAM_PIOC_BASE+SAM_PIO_ABSR_OFFSET)
#define SAM_PIOC_SCIFSR (SAM_PIOC_BASE+SAM_PIO_SCIFSR_OFFSET)
#define SAM_PIOC_DIFSR (SAM_PIOC_BASE+SAM_PIO_DIFSR_OFFSET)
#define SAM_PIOC_IFDGSR (SAM_PIOC_BASE+SAM_PIO_IFDGSR_OFFSET)
#define SAM_PIOC_SCDR (SAM_PIOC_BASE+SAM_PIO_SCDR_OFFSET)
#define SAM_PIOC_OWER (SAM_PIOC_BASE+SAM_PIO_OWER_OFFSET)
#define SAM_PIOC_OWDR (SAM_PIOC_BASE+SAM_PIO_OWDR_OFFSET)
#define SAM_PIOC_OWSR (SAM_PIOC_BASE+SAM_PIO_OWSR_OFFSET)
#define SAM_PIOC_AIMER (SAM_PIOC_BASE+SAM_PIO_AIMER_OFFSET)
#define SAM_PIOC_AIMDR (SAM_PIOC_BASE+SAM_PIO_AIMDR_OFFSET)
#define SAM_PIOC_AIMMR (SAM_PIOC_BASE+SAM_PIO_AIMMR_OFFSET)
#define SAM_PIOC_ESR (SAM_PIOC_BASE+SAM_PIO_ESR_OFFSET)
#define SAM_PIOC_LSR (SAM_PIOC_BASE+SAM_PIO_LSR_OFFSET)
#define SAM_PIOC_ELSR (SAM_PIOC_BASE+SAM_PIO_ELSR_OFFSET)
#define SAM_PIOC_FELLSR (SAM_PIOC_BASE+SAM_PIO_FELLSR_OFFSET)
#define SAM_PIOC_REHLSR (SAM_PIOC_BASE+SAM_PIO_REHLSR_OFFSET)
#define SAM_PIOC_FRLHSR (SAM_PIOC_BASE+SAM_PIO_FRLHSR_OFFSET)
#define SAM_PIOC_LOCKSR (SAM_PIOC_BASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOC_WPMR (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOC_WPSR (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET)
/* PIO register bit definitions *********************************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
#define PIO(n) (1<<(n)) /* Bit n: PIO n */
/* PIO Write Protect Mode Register */
#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT)
/* PIO Write Protect Status Register */
#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PIO_H */
arch/arm/src/sam3u/chip/sam_pmc.h
+315
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@@ -0,0 +1,315 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_pmc.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PMC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PMC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* PMC register offsets *****************************************************************/
#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */
#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
/* 0x000c: Reserved */
#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */
#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */
#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
#define SAM_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
#define SAM_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */
#define SAM_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
#define SAM_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
/* 0x002c: Reserved */
#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
/* 0x0034-0x003C Reserved */
#define SAM_PMC_PCK_OFFSET(n) (0x0040+((n)<<2))
#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
/* 0x004c-0x005c: Reserved */
#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */
#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */
#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */
#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */
#define SAM_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */
#define SAM_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */
#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */
/* 0x007c-0x00fc: Reserved */
#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* PMC register adresses ****************************************************************/
#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET)
#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
#define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET)
#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET)
#define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET)
#define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET)
#define SAM_CKGR_UCKR (SAM_PMC_BASE+SAM_CKGR_UCKR_OFFSET)
#define SAM_CKGR_MOR (SAM_PMC_BASE+SAM_CKGR_MOR_OFFSET)
#define SAM_CKGR_MCFR (SAM_PMC_BASE+SAM_CKGR_MCFR_OFFSET)
#define SAM_CKGR_PLLAR (SAM_PMC_BASE+SAM_CKGR_PLLAR_OFFSET)
#define SAM_PMC_MCKR (SAM_PMC_BASE+SAM_PMC_MCKR_OFFSET)
#define SAM_PMC_PCK(n) (SAM_PMC_BASE+SAM_PMC_PCK_OFFSET(n))
#define SAM_PMC_PCK0 (SAM_PMC_BASE+SAM_PMC_PCK0_OFFSET)
#define SAM_PMC_PCK1 (SAM_PMC_BASE+SAM_PMC_PCK1_OFFSET)
#define SAM_PMC_PCK2 (SAM_PMC_BASE+SAM_PMC_PCK2_OFFSET)
#define SAM_PMC_IER (SAM_PMC_BASE+SAM_PMC_IER_OFFSET)
#define SAM_PMC_IDR (SAM_PMC_BASE+SAM_PMC_IDR_OFFSET)
#define SAM_PMC_SR (SAM_PMC_BASE+SAM_PMC_SR_OFFSET)
#define SAM_PMC_IMR (SAM_PMC_BASE+SAM_PMC_IMR_OFFSET)
#define SAM_PMC_FSMR (SAM_PMC_BASE+SAM_PMC_FSMR_OFFSET)
#define SAM_PMC_FSPR (SAM_PMC_BASE+SAM_PMC_FSPR_OFFSET)
#define SAM_PMC_FOCR (SAM_PMC_BASE+SAM_PMC_FOCR_OFFSET)
#define SAM_PMC_WPMR (SAM_PMC_BASE+SAM_PMC_WPMR_OFFSET)
#define SAM_PMC_WPSR (SAM_PMC_BASE+SAM_PMC_WPSR_OFFSET)
/* PMC register bit definitions *********************************************************/
/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
* Clock Status Register common bit-field definitions
*/
#define PMC_PCK(n) (1 <<((n)+8)
#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */
#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */
#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */
/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
* Peripheral Clock Status Register common bit-field definitions.
*/
#define PMC_PID(n) (1<<(n))
#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */
#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */
#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */
#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */
#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */
#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */
#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */
#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */
#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */
#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */
#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */
#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */
#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */
#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */
#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */
#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */
#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */
#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */
#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */
#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */
#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */
#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */
#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */
#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */
#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */
#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */
#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */
#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */
#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */
#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */
/* PMC UTMI Clock Configuration Register */
#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */
#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */
#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT)
/* PMC Clock Generator Main Oscillator Register */
#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */
#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT)
#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */
#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT)
#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT)
#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */
#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */
/* PMC Clock Generator Main Clock Frequency Register */
#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT)
#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
/* PMC Clock Generator PLLA Register */
#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */
#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT)
# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */
# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */
# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */
#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT)
#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */
#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT)
# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */
# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */
#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT)
#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */
/* PMC Master Clock Register */
#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */
#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT)
# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */
# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */
# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */
#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT)
# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */
# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */
# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */
# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */
# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */
# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */
# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */
#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */
/* PMC Programmable Clock Register (0,1,2) */
#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK)
# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */
# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */
# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */
# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */
# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */
#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */
# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */
# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */
# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */
# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */
# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
* and PMC Interrupt Mask Register common bit-field definitions
*/
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */
#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */
#define PMC_INT_PCKRDY(n) (1 << ((n)+8)
#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */
#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */
#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */
#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field
* definitions
*/
#define PMC_FSTI(n) (1 << (n))
#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */
#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */
#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */
#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */
#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */
#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */
#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */
#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */
#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */
#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */
#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */
#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */
#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */
#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */
#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */
#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */
#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */
#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */
#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */
#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */
/* PMC Fault Output Clear Register */
#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */
/* PMC Write Protect Mode Register */
#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT)
/* PMC Write Protect Status Register */
#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_PMC_H */
arch/arm/src/sam3u/chip/sam_pwm.h
+633
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File diff suppressed because it is too large Load Diff
arch/arm/src/sam3u/sam3u_rstc.h → arch/arm/src/sam3u/chip/sam_rstc.h
+12 -12
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_rstc.h
* arch/arm/src/sam3u/chip/sam_rstc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RSTC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RSTC_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,15 +51,15 @@
/* RSTC register offsets ****************************************************************/
#define SAM3U_RSTC_CR_OFFSET 0x00 /* Control Register */
#define SAM3U_RSTC_SR_OFFSET 0x04 /* Status Register */
#define SAM3U_RSTC_MR_OFFSET 0x08 /* Mode Register */
#define SAM_RSTC_CR_OFFSET 0x00 /* Control Register */
#define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */
#define SAM_RSTC_MR_OFFSET 0x08 /* Mode Register */
/* RSTC register adresses ***************************************************************/
#define SAM3U_RSTC_CR (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET)
#define SAM3U_RSTC_SR (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET)
#define SAM3U_RSTC_MR (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET)
#define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET)
#define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET)
#define SAM_RSTC_MR (SAM_RSTC_BASE+SAM_RSTC_MR_OFFSET)
/* RSTC register bit definitions ********************************************************/
@@ -99,4 +99,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RSTC_H */
arch/arm/src/sam3u/chip/sam_rtc.h
+184
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@@ -0,0 +1,184 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_rtc.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RTC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RTC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* RTC register offsets *****************************************************************/
#define SAM_RTC_CR_OFFSET 0x00 /* Control Register */
#define SAM_RTC_MR_OFFSET 0x04 /* Mode Register */
#define SAM_RTC_TIMR_OFFSET 0x08 /* Time Register */
#define SAM_RTC_CALR_OFFSET 0x0c /* Calendar Register */
#define SAM_RTC_TIMALR_OFFSET 0x10 /* Time Alarm Register */
#define SAM_RTC_CALALR_OFFSET 0x14 /* Calendar Alarm Register */
#define SAM_RTC_SR_OFFSET 0x18 /* Status Register */
#define SAM_RTC_SCCR_OFFSET 0x1c /* Status Clear Command Register */
#define SAM_RTC_IER_OFFSET 0x20 /* Interrupt Enable Register */
#define SAM_RTC_IDR_OFFSET 0x24 /* Interrupt Disable Register */
#define SAM_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */
#define SAM_RTC_VER_OFFSET 0x2c /* Valid Entry Register */
/* RTC register adresses ****************************************************************/
#define SAM_RTC_CR (SAM_RTC_BASE+SAM_RTC_CR_OFFSET)
#define SAM_RTC_MR (SAM_RTC_BASE+SAM_RTC_MR_OFFSET)
#define SAM_RTC_TIMR (SAM_RTC_BASE+SAM_RTC_TIMR_OFFSET)
#define SAM_RTC_CALR (SAM_RTC_BASE+SAM_RTC_CALR_OFFSET)
#define SAM_RTC_TIMALR (SAM_RTC_BASE+SAM_RTC_TIMALR_OFFSET)
#define SAM_RTC_CALALR (SAM_RTC_BASE+SAM_RTC_CALALR_OFFSET)
#define SAM_RTC_SR (SAM_RTC_BASE+SAM_RTC_SR_OFFSET)
#define SAM_RTC_SCCR (SAM_RTC_BASE+SAM_RTC_SCCR_OFFSET)
#define SAM_RTC_IER (SAM_RTC_BASE+SAM_RTC_IER_OFFSET)
#define SAM_RTC_IDR (SAM_RTC_BASE+SAM_RTC_IDR_OFFSET)
#define SAM_RTC_IMR (SAM_RTC_BASE+SAM_RTC_IMR_OFFSET)
#define SAM_RTC_VER (SAM_RTC_BASE+SAM_RTC_VER_OFFSET)
/* RTC register bit definitions *********************************************************/
#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */
#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */
#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */
#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT)
# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT)
# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT)
# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT)
# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT)
#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */
#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT)
# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT)
# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT)
# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT)
#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */
#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */
#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT)
#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */
#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT)
#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */
#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT)
#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */
#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT)
#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */
#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT)
#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */
#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT)
#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */
#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT)
#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */
#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT)
#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */
#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT)
#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */
#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */
#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT)
#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */
#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */
#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT)
#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */
#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */
#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */
#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT)
#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */
#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */
#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT)
#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */
#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */
#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */
#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */
#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */
#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */
#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */
#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */
#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */
#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */
#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */
#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */
#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */
#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */
#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */
#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */
#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */
#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */
#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */
#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */
#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */
#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */
#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */
#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */
#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */
#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */
#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */
#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */
#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */
#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RTC_H */
arch/arm/src/sam3u/sam3u_rtt.h → arch/arm/src/sam3u/chip/sam_rtt.h
+14 -14
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_rtt.h
* arch/arm/src/sam3u/chip/sam_rtt.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RTT_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RTT_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,17 +51,17 @@
/* RTT register offsets *****************************************************************/
#define SAM3U_RTT_MR_OFFSET 0x00 /* Mode Register */
#define SAM3U_RTT_AR_OFFSET 0x04 /* Alarm Register */
#define SAM3U_RTT_VR_OFFSET 0x08 /* Value Register */
#define SAM3U_RTT_SR_OFFSET 0x0c /* Status Register */
#define SAM_RTT_MR_OFFSET 0x00 /* Mode Register */
#define SAM_RTT_AR_OFFSET 0x04 /* Alarm Register */
#define SAM_RTT_VR_OFFSET 0x08 /* Value Register */
#define SAM_RTT_SR_OFFSET 0x0c /* Status Register */
/* RTT register adresses ***************************************************************/
#define SAM3U_RTT_MR (SAM3U_RTT_BASE+SAM3U_RTT_MR_OFFSET)
#define SAM3U_RTT_AR (SAM3U_RTT_BASE+SAM3U_RTT_AR_OFFSET)
#define SAM3U_RTT_VR (SAM3U_RTT_BASE+SAM3U_RTT_VR_OFFSET)
#define SAM3U_RTT_SR (SAM3U_RTT_BASE+SAM3U_RTT_SR_OFFSET)
#define SAM_RTT_MR (SAM_RTT_BASE+SAM_RTT_MR_OFFSET)
#define SAM_RTT_AR (SAM_RTT_BASE+SAM_RTT_AR_OFFSET)
#define SAM_RTT_VR (SAM_RTT_BASE+SAM_RTT_VR_OFFSET)
#define SAM_RTT_SR (SAM_RTT_BASE+SAM_RTT_SR_OFFSET)
/* RTT register bit definitions ********************************************************/
@@ -86,4 +86,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_RTT_H */
arch/arm/src/sam3u/sam3u_smc.h → arch/arm/src/sam3u/chip/sam_smc.h
+89 -89
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_smc.h
* arch/arm/src/sam3u/chip/sam_smc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SMC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SMC_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,95 +51,95 @@
/* SMC register offsets *****************************************************************/
#define SAM3U_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */
#define SAM3U_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */
#define SAM3U_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */
#define SAM3U_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */
#define SAM3U_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */
#define SAM3U_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */
#define SAM3U_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */
#define SAM3U_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */
#define SAM3U_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */
#define SAM3U_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */
#define SAM3U_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */
#define SAM3U_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */
#define SAM3U_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */
#define SAM3U_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */
#define SAM3U_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */
#define SAM3U_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */
#define SAM3U_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */
#define SAM3U_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */
#define SAM3U_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */
#define SAM3U_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */
#define SAM3U_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */
#define SAM3U_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */
#define SAM3U_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */
#define SAM3U_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */
#define SAM3U_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */
#define SAM3U_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */
#define SAM3U_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */
#define SAM3U_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */
#define SAM_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */
#define SAM_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */
#define SAM_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */
#define SAM_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */
#define SAM_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */
#define SAM_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */
#define SAM_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */
#define SAM_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */
#define SAM_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */
#define SAM_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */
#define SAM_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */
#define SAM_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */
#define SAM_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */
#define SAM_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */
#define SAM_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */
#define SAM_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */
#define SAM_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */
#define SAM_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */
#define SAM_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */
#define SAM_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */
#define SAM_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */
#define SAM_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */
#define SAM_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */
#define SAM_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */
#define SAM_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */
#define SAM_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */
#define SAM_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */
#define SAM_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */
#define SAM3U_SMCCS_OFFSET(n) (0x070+((n)*0x014))
#define SAM3U_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */
#define SAM3U_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */
#define SAM3U_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */
#define SAM3U_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */
#define SAM3U_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */
#define SAM_SMCCS_OFFSET(n) (0x070+((n)*0x014))
#define SAM_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */
#define SAM_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */
#define SAM_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */
#define SAM_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */
#define SAM_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */
#define SAM3U_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */
#define SAM3U_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */
#define SAM3U_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */
#define SAM3U_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */
#define SAM3U_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */
#define SAM_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */
#define SAM_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */
#define SAM_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */
#define SAM_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */
#define SAM_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */
/* SMC register adresses ****************************************************************/
#define SAM3U_SMC_CFG (SAM3U_SMC_BASE+SAM3U_SMC_CFG_OFFSET)
#define SAM3U_SMC_CTRL (SAM3U_SMC_BASE+SAM3U_SMC_CTRL_OFFSET)
#define SAM3U_SMC_SR (SAM3U_SMC_BASE+SAM3U_SMC_SR_OFFSET)
#define SAM3U_SMC_IER (SAM3U_SMC_BASE+SAM3U_SMC_IER_OFFSET)
#define SAM3U_SMC_IDR (SAM3U_SMC_BASE+SAM3U_SMC_IDR_OFFSET)
#define SAM3U_SMC_IMR (SAM3U_SMC_BASE+SAM3U_SMC_IMR_OFFSET)
#define SAM3U_SMC_ADDR (SAM3U_SMC_BASE+SAM3U_SMC_ADDR_OFFSET)
#define SAM3U_SMC_BANK (SAM3U_SMC_BASE+SAM3U_SMC_BANK_OFFSET)
#define SAM3U_SMC_ECCCTRL (SAM3U_SMC_BASE+SAM3U_SMC_ECCCTRL_OFFSET)
#define SAM3U_SMC_ECCMD (SAM3U_SMC_BASE+SAM3U_SMC_ECCMD_OFFSET)
#define SAM3U_SMC_ECCSR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR1_OFFSET)
#define SAM3U_SMC_ECCPR0 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR0_OFFSET)
#define SAM3U_SMC_ECCPR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR1_OFFSET)
#define SAM3U_SMC_ECCSR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR2_OFFSET)
#define SAM3U_SMC_ECCPR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR2_OFFSET)
#define SAM3U_SMC_ECCPR3 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR3_OFFSET)
#define SAM3U_SMC_ECCPR4 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR4_OFFSET)
#define SAM3U_SMC_ECCPR5 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR5_OFFSET)
#define SAM3U_SMC_ECCPR6 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR6_OFFSET)
#define SAM3U_SMC_ECCPR7 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR7_OFFSET)
#define SAM3U_SMC_ECCPR8 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR8_OFFSET)
#define SAM3U_SMC_ECCPR9 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR9_OFFSET)
#define SAM3U_SMC_ECCPR10 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR10_OFFSET)
#define SAM3U_SMC_ECCPR11 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR11_OFFSET)
#define SAM3U_SMC_ECCPR12 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR12_OFFSET)
#define SAM3U_SMC_ECCPR13 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR13_OFFSET)
#define SAM3U_SMC_ECCPR14 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR14_OFFSET)
#define SAM3U_SMC_ECCPR15 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR15_OFFSET)
#define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET)
#define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET)
#define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET)
#define SAM_SMC_IER (SAM_SMC_BASE+SAM_SMC_IER_OFFSET)
#define SAM_SMC_IDR (SAM_SMC_BASE+SAM_SMC_IDR_OFFSET)
#define SAM_SMC_IMR (SAM_SMC_BASE+SAM_SMC_IMR_OFFSET)
#define SAM_SMC_ADDR (SAM_SMC_BASE+SAM_SMC_ADDR_OFFSET)
#define SAM_SMC_BANK (SAM_SMC_BASE+SAM_SMC_BANK_OFFSET)
#define SAM_SMC_ECCCTRL (SAM_SMC_BASE+SAM_SMC_ECCCTRL_OFFSET)
#define SAM_SMC_ECCMD (SAM_SMC_BASE+SAM_SMC_ECCMD_OFFSET)
#define SAM_SMC_ECCSR1 (SAM_SMC_BASE+SAM_SMC_ECCSR1_OFFSET)
#define SAM_SMC_ECCPR0 (SAM_SMC_BASE+SAM_SMC_ECCPR0_OFFSET)
#define SAM_SMC_ECCPR1 (SAM_SMC_BASE+SAM_SMC_ECCPR1_OFFSET)
#define SAM_SMC_ECCSR2 (SAM_SMC_BASE+SAM_SMC_ECCSR2_OFFSET)
#define SAM_SMC_ECCPR2 (SAM_SMC_BASE+SAM_SMC_ECCPR2_OFFSET)
#define SAM_SMC_ECCPR3 (SAM_SMC_BASE+SAM_SMC_ECCPR3_OFFSET)
#define SAM_SMC_ECCPR4 (SAM_SMC_BASE+SAM_SMC_ECCPR4_OFFSET)
#define SAM_SMC_ECCPR5 (SAM_SMC_BASE+SAM_SMC_ECCPR5_OFFSET)
#define SAM_SMC_ECCPR6 (SAM_SMC_BASE+SAM_SMC_ECCPR6_OFFSET)
#define SAM_SMC_ECCPR7 (SAM_SMC_BASE+SAM_SMC_ECCPR7_OFFSET)
#define SAM_SMC_ECCPR8 (SAM_SMC_BASE+SAM_SMC_ECCPR8_OFFSET)
#define SAM_SMC_ECCPR9 (SAM_SMC_BASE+SAM_SMC_ECCPR9_OFFSET)
#define SAM_SMC_ECCPR10 (SAM_SMC_BASE+SAM_SMC_ECCPR10_OFFSET)
#define SAM_SMC_ECCPR11 (SAM_SMC_BASE+SAM_SMC_ECCPR11_OFFSET)
#define SAM_SMC_ECCPR12 (SAM_SMC_BASE+SAM_SMC_ECCPR12_OFFSET)
#define SAM_SMC_ECCPR13 (SAM_SMC_BASE+SAM_SMC_ECCPR13_OFFSET)
#define SAM_SMC_ECCPR14 (SAM_SMC_BASE+SAM_SMC_ECCPR14_OFFSET)
#define SAM_SMC_ECCPR15 (SAM_SMC_BASE+SAM_SMC_ECCPR15_OFFSET)
#define SAM3U_SMCCS_BASE(n) (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(n))
# define SAM3U_SMC_CS0_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(0))
# define SAM3U_SMC_CS1_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(1))
# define SAM3U_SMC_CS2_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(2))
# define SAM3U_SMC_CS3_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(3))
#define SAM3U_SMCCS_SETUP(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_SETUP_OFFSET)
#define SAM3U_SMCCS_PULSE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_PULSE_OFFSET)
#define SAM3U_SMCCS_CYCLE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_CYCLE_OFFSET)
#define SAM3U_SMCCS_TIMINGS(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_TIMINGS_OFFSET)
#define SAM3U_SMCCS_MODE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_MODE_OFFSET)
#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n))
# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0))
# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1))
# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2))
# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3))
#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET)
#define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET)
#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET)
#define SAM3U_SMC_OCMS (SAM3U_SMC_BASE+SAM3U_SMC_OCMS_OFFSET)
#define SAM3U_SMC_KEY1 (SAM3U_SMC_BASE+SAM3U_SMC_KEY1_OFFSET)
#define SAM3U_SMC_KEY2 (SAM3U_SMC_BASE+SAM3U_SMC_KEY2_OFFSET)
#define SAM3U_SMC_WPCR (SAM3U_SMC_BASE+SAM3U_SMC_WPCR_OFFSET)
#define SAM3U_SMC_WPSR (SAM3U_SMC_BASE+SAM3U_SMC_WPSR_OFFSET)
#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET)
#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET)
#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET)
#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET)
#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET)
/* SMC register bit definitions *********************************************************/
@@ -174,7 +174,7 @@
#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */
/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt
* Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions
* Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions
*/
#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */
@@ -429,4 +429,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SMC_H */
arch/arm/src/sam3u/chip/sam_spi.h
+189
View File
@@ -0,0 +1,189 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_spi.h
*
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SPI_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SPI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SPI register offsets *****************************************************************/
#define SAM_SPI_CR_OFFSET 0x00 /* Control Register */
#define SAM_SPI_MR_OFFSET 0x04 /* Mode Register */
#define SAM_SPI_RDR_OFFSET 0x08 /* Receive Data Register */
#define SAM_SPI_TDR_OFFSET 0x0c /* Transmit Data Register */
#define SAM_SPI_SR_OFFSET 0x10 /* Status Register */
#define SAM_SPI_IER_OFFSET 0x14 /* Interrupt Enable Register */
#define SAM_SPI_IDR_OFFSET 0x18 /* Interrupt Disable Register */
#define SAM_SPI_IMR_OFFSET 0x1c /* Interrupt Mask Register */
/* 0x20-0x2c: Reserved */
#define SAM_SPI_CSR0_OFFSET 0x30 /* Chip Select Register 0 */
#define SAM_SPI_CSR1_OFFSET 0x34 /* Chip Select Register 1 */
#define SAM_SPI_CSR2_OFFSET 0x38 /* Chip Select Register 2 */
#define SAM_SPI_CSR3_OFFSET 0x3c /* Chip Select Register 3 */
/* 0x40-0xe0: Reserved */
#define SAM_SPI_WPCR_OFFSET 0xe4 /* Write Protection Control Register */
#define SAM_SPI_WPSR_OFFSET 0xe8 /* Write Protection Status Register */
/* 0xec-0xf8: Reserved*/
/* SPI register adresses ****************************************************************/
#define SAM_SPI_CR (SAM_SPI_BASE+SAM_SPI_CR_OFFSET) /* Control Register */
#define SAM_SPI_MR (SAM_SPI_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */
#define SAM_SPI_RDR (SAM_SPI_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */
#define SAM_SPI_TDR (SAM_SPI_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */
#define SAM_SPI_SR (SAM_SPI_BASE+SAM_SPI_SR_OFFSET) /* Status Register */
#define SAM_SPI_IER (SAM_SPI_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */
#define SAM_SPI_IDR (SAM_SPI_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */
#define SAM_SPI_IMR (SAM_SPI_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */
#define SAM_SPI_CSR0 (SAM_SPI_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
#define SAM_SPI_CSR1 (SAM_SPI_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
#define SAM_SPI_CSR2 (SAM_SPI_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
#define SAM_SPI_CSR3 (SAM_SPI_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
#define SAM_SPI_WPCR (SAM_SPI_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
#define SAM_SPI_WPSR (SAM_SPI_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
/* SPI register bit definitions *********************************************************/
/* SPI Control Register */
#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
/* SPI Mode Register */
#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
/* SPI Receive Data Register */
#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT)
#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
/* SPI Transmit Data Register */
#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT)
#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
* and SPI Interrupt Mask Register (common bit fields)
*/
#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
/* SPI Chip Select Registers 0-3 */
#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */
# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */
# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */
# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */
# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT)
#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
/* SPI Write Protection Control Register */
#define SPI_WPCR_SPIWPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
#define SPI_WPCR_SPIWPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
#define SPI_WPCR_SPIWPKEY_MASK (0x00ffffff << SPI_WPCR_SPIWPKEY_SHIFT)
/* SPI Write Protection Status Register */
#define SPI_WPSR_SPIWPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
#define SPI_WPSR_SPIWPVS_MASK (7 << SPI_WPSR_SPIWPVS_SHIFT)
#define SPI_WPSR_SPIWPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
#define SPI_WPSR_SPIWPVSRC_MASK (0xff << SPI_WPSR_SPIWPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SPI_H */
arch/arm/src/sam3u/chip/sam_ssc.h
+292
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@@ -0,0 +1,292 @@
/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_ssc.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SSC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SSC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SSC register offsets *****************************************************************/
#define SAM_SSC_CR_OFFSET 0x000 /* Control Register */
#define SAM_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */
/* 0x008: Reserved */
/* 0x00c: Reserved */
#define SAM_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */
#define SAM_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */
#define SAM_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */
#define SAM_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */
#define SAM_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */
#define SAM_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */
/* 0x028: Reserved */
/* 0x02c: Reserved */
#define SAM_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */
#define SAM_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */
#define SAM_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */
#define SAM_SSC_RC1R_OFFSET 0x03c /* Receive Compare 1 Register */
#define SAM_SSC_SR_OFFSET 0x040 /* Status Register */
#define SAM_SSC_IER_OFFSET 0x044 /* Interrupt Enable Register */
#define SAM_SSC_IDR_OFFSET 0x048 /* Interrupt Disable Register */
#define SAM_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */
#define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */
#define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */
/* 0x050-0x0fc: Reserved */
/* 0x100-0x124: Reserved */
/* SSC register adresses ****************************************************************/
#define SAM_SSC_CR (SAM_SSC_BASE+SAM_SSC_CR_OFFSET)
#define SAM_SSC_CMR (SAM_SSC_BASE+SAM_SSC_CMR_OFFSET)
#define SAM_SSC_RCMR (SAM_SSC_BASE+SAM_SSC_RCMR_OFFSET)
#define SAM_SSC_RFMR (SAM_SSC_BASE+SAM_SSC_RFMR_OFFSET)
#define SAM_SSC_TCMR (SAM_SSC_BASE+SAM_SSC_TCMR_OFFSET)
#define SAM_SSC_TFMR (SAM_SSC_BASE+SAM_SSC_TFMR_OFFSET)
#define SAM_SSC_RHR (SAM_SSC_BASE+SAM_SSC_RHR_OFFSET)
#define SAM_SSC_THR (SAM_SSC_BASE+SAM_SSC_THR_OFFSET)
#define SAM_SSC_RSHR (SAM_SSC_BASE+SAM_SSC_RSHR_OFFSET)
#define SAM_SSC_TSHR (SAM_SSC_BASE+SAM_SSC_TSHR_OFFSET)
#define SAM_SSC_RC0R (SAM_SSC_BASE+SAM_SSC_RC0R_OFFSET)
#define SAM_SSC_RC1R (SAM_SSC_BASE+SAM_SSC_RC1R_OFFSET)
#define SAM_SSC_SR (SAM_SSC_BASE+SAM_SSC_SR_OFFSET)
#define SAM_SSC_IER (SAM_SSC_BASE+SAM_SSC_IER_OFFSET)
#define SAM_SSC_IDR (SAM_SSC_BASE+SAM_SSC_IDR_OFFSET)
#define SAM_SSC_IMR (SAM_SSC_BASE+SAM_SSC_IMR_OFFSET)
#define SAM_SSC_WPMR (SAM_SSC_BASE+SAM_SSC_WPMR_OFFSET)
#define SAM_SSC_WPSR (SAM_SSC_BASE+SAM_SSC_WPSR_OFFSET)
/* SSC register bit definitions *********************************************************/
/* SSC Control Register */
#define SSC_CR_RXEN (1 << 0) /* Bit 0: Receive Enable */
#define SSC_CR_RXDIS (1 << 1) /* Bit 1: Receive Disable */
#define SSC_CR_TXEN (1 << 8) /* Bit 8: Transmit Enable */
#define SSC_CR_TXDIS (1 << 9) /* Bit 9: Transmit Disable */
#define SSC_CR_SWRST (1 << 15) /* Bit 15: Software Reset */
/* SSC Clock Mode Register */
#define SSC_CMR_DIV_SHIFT (0) /* Bits 0-11: Clock Divider */
#define SSC_CMR_DIV_MASK (0xfff << SSC_CMR_DIV_SHIFT)
/* SSC Receive Clock Mode Register */
#define SSC_RCMR_CKS_SHIFT (0) /* Bits 0-1: Receive Clock Selection */
#define SSC_RCMR_CKS_MASK (3 << SSC_RCMR_CKS_SHIFT)
# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */
# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */
# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */
#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */
# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */
#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT)
# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */
# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */
#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */
#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT)
# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */
# define SSC_RCMR_START_START (1 << SSC_RCMR_START_SHIFT) /* Transmit start */
# define SSC_RCMR_START_RFLOW (2 << SSC_RCMR_START_SHIFT) /* Low level on RF signal */
# define SSC_RCMR_START_RFHIGH (3 << SSC_RCMR_START_SHIFT) /* High level on RF signal */
# define SSC_RCMR_START_RFFALL (4 << SSC_RCMR_START_SHIFT) /* Falling edge on RF signal */
# define SSC_RCMR_START_RFRISE (5 << SSC_RCMR_START_SHIFT) /* Rising edge on RF signal */
# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */
# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */
# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */
#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT)
#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */
#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT)
/* SSC Receive Frame Mode Register */
#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
#define SSC_RFMR_DATLEN_MASK (31 << SSC_RFMR_DATLEN_SHIFT)
#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */
#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */
#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */
#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT)
#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */
#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT)
#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */
#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT)
# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */
# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */
#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT)
/* SSC Transmit Clock Mode Register */
#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */
#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT)
# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */
# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */
# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */
#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */
# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */
#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT)
# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */
# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */
#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */
#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT)
# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */
# define SSC_TCMR_START_START (1 << SSC_TCMR_START_SHIFT) /* Receive start */
# define SSC_TCMR_START_TFLOW (2 << SSC_TCMR_START_SHIFT) /* Low level on TF signal */
# define SSC_TCMR_START_TFHIGH (3 << SSC_TCMR_START_SHIFT) /* High level on TF signal */
# define SSC_TCMR_START_TFFALL (4 << SSC_TCMR_START_SHIFT) /* Falling edge on TF signal */
# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */
# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */
# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */
#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */
#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT)
#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */
#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT)
/* SSC Transmit Frame Mode Register */
#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
#define SSC_TFMR_DATLEN_MASK (31 << SSC_TFMR_DATLEN_SHIFT)
#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */
#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */
#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per frame */
#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT)
#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Syn Length */
#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT)
#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Output Selection */
#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT)
# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */
# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */
# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */
# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */
#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */
#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT)
/* SSC Receive Synchronization Holding Register */
#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */
#define SSC_RSHR_RSDAT_MASK (0xffff << SSC_RSHR_RSDAT_SHIFT)
/* SSC Transmit Synchronization Holding Register */
#define SSC_TSHR_TSDAT_SHIFT (0) /* Bits 0-15: Transmit Synchronization Data */
#define SSC_TSHR_TSDAT_MASK (0xffff << SSC_TSHR_TSDAT_SHIFT)
/* SSC Receive Compare 0 Register */
#define SSC_RC0R_CP0_SHIFT (0) /* Bits 0-15: Receive Compare Data 0 */
#define SSC_RC0R_CP0_MASK (0xffff << SSC_RC0R_CP0_SHIFT)
/* SSC Receive Compare 1 Register */
#define SSC_RC1R_CP1_SHIFT (0) /* Bits 0-15: Receive Compare Data 1 */
#define SSC_RC1R_CP1_MASK (0xffff << SSC_RC1R_CP1_SHIFT)
/* SSC Status Register, SSC Interrupt Enable Register, SSC Interrupt Disable
* Register, and SSC Interrupt Mask Register commin bit-field definitions
*/
#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */
#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */
#define SSC_INT_ENDTX (1 << 2) /* Bit 2: End of Transmission */
#define SSC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */
#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */
#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */
#define SSC_INT_ENDRX (1 << 6) /* Bit 6: End of Reception */
#define SSC_INT_RXBUFF (1 << 7) /* Bit 7: Receive Buffer Full */
#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */
#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */
#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */
#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */
#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable (SR only) */
#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable (SR only) */
/* SSC Write Protect Mode Register */
#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT)
/* SSC Write Protect Status Register */
#define SSC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SSC_H */
arch/arm/src/sam3u/sam3u_supc.h → arch/arm/src/sam3u/chip/sam_supc.h
+18 -18
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_supc.h
* arch/arm/src/sam3u/chip/sam_supc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SUPC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SUPC_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,21 +51,21 @@
/* SUPC register offsets ****************************************************************/
#define SAM3U_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
#define SAM3U_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
#define SAM3U_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */
#define SAM3U_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */
#define SAM3U_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
#define SAM3U_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
#define SAM_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */
#define SAM_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */
#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
/* SUPC register adresses ***************************************************************/
#define SAM3U_SUPC_CR (SAM3U_SUPC_BASE+SAM3U_SUPC_CR_OFFSET)
#define SAM3U_SUPC_SMMR (SAM3U_SUPC_BASE+SAM3U_SUPC_SMMR_OFFSET)
#define SAM3U_SUPC_MR (SAM3U_SUPC_BASE+SAM3U_SUPC_MR_OFFSET)
#define SAM3U_SUPC_WUMR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUMR_OFFSET)
#define SAM3U_SUPC_WUIR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUIR_OFFSET)
#define SAM3U_SUPC_SR (SAM3U_SUPC_BASE+SAM3U_SUPC_SR_OFFSET)
#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
#define SAM_SUPC_MR (SAM_SUPC_BASE+SAM_SUPC_MR_OFFSET)
#define SAM_SUPC_WUMR (SAM_SUPC_BASE+SAM_SUPC_WUMR_OFFSET)
#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET)
#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET)
/* SUPC register bit definitions ********************************************************/
@@ -161,4 +161,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_SUPC_H */
arch/arm/src/sam3u/chip/sam_tc.h
+347
View File
@@ -0,0 +1,347 @@
/************************************************************************************************
* arch/arm/src/sam3u/chip/sam_tc.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_TC_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_TC_H
/************************************************************************************************
* Included Files
************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* TC register offsets **************************************************************************/
/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */
#define SAM_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */
#define SAM_TCN_CCR_OFFSET 0x00 /* Channel Control Register */
#define SAM_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */
/* 0x08 Reserved */
/* 0x0c Reserved */
#define SAM_TCN_CV_OFFSET 0x10 /* Counter Value */
#define SAM_TCN_RA_OFFSET 0x14 /* Register A */
#define SAM_TCN_RB_OFFSET 0x18 /* Register B */
#define SAM_TCN_RC_OFFSET 0x1c /* Register C */
#define SAM_TCN_SR_OFFSET 0x20 /* Status Register */
#define SAM_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */
#define SAM_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */
#define SAM_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */
/* Timer common registers */
#define SAM_TC_BCR_OFFSET 0xc0 /* Block Control Register */
#define SAM_TC_BMR_OFFSET 0xc4 /* Block Mode Register */
#define SAM_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */
#define SAM_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */
#define SAM_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */
#define SAM_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */
/* 0xd8 Reserved */
/* 0xe4 Reserved */
/* TC register adresses *************************************************************************/
/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */
#define SAM_TC_CCR(n) (SAM_TCN_BASE(n)+SAM_TCN_CCR_OFFSET)
#define SAM_TC_CMR(n) (SAM_TCN_BASE(n)+SAM_TCN_CMR_OFFSET)
#define SAM_TC_CV(n) (SAM_TCN_BASE(n)+SAM_TCN_CV_OFFSET)
#define SAM_TC_RA(n) (SAM_TCN_BASE(n)+SAM_TCN_RA_OFFSET)
#define SAM_TC_RB(n) (SAM_TCN_BASE(n)+SAM_TCN_RB_OFFSET)
#define SAM_TC_RC(n) (SAM_TCN_BASE(n)+SAM_TCN_RC_OFFSET)
#define SAM_TC_SR(n) (SAM_TCN_BASE(n)+SAM_TCN_SR_OFFSET)
#define SAM_TC_IER(n) (SAM_TCN_BASE(n)+SAM_TCN_IER_OFFSET)
#define SAM_TC_IDR(n) (SAM_TCN_BASE(n)+SAM_TCN_IDR_OFFSET)
#define SAM_TC_IMR(n) (SAM_TCN_BASE(n)+SAM_TCN_IMR_OFFSET)
#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TCN_CMR_OFFSET)
#define SAM_TC0_CV (SAM_TC0_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC0_RA (SAM_TC0_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC0_RB (SAM_TC0_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC0_RC (SAM_TC0_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC0_SR (SAM_TC0_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC0_IER (SAM_TC0_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC0_IDR (SAM_TC0_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC0_IMR (SAM_TC0_BASE+SAM_TCN_IMR_OFFSET)
#define SAM_TC1_CCR (SAM_TC1_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC1_CMR (SAM_TC1_BASE+SAM_TCN_CMR_OFFSET)
#define SAM_TC1_CV (SAM_TC1_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC1_RA (SAM_TC1_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC1_RB (SAM_TC1_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC1_RC (SAM_TC1_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC1_SR (SAM_TC1_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC1_IER (SAM_TC1_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC1_IDR (SAM_TC1_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC1_IMR (SAM_TC1_BASE+SAM_TCN_IMR_OFFSET)
#define SAM_TC2_CCR (SAM_TC2_BASE+SAM_TCN_CCR_OFFSET)
#define SAM_TC2_CMR (SAM_TC2_BASE+SAM_TCN_CMR_OFFSET)
#define SAM_TC2_CV (SAM_TC2_BASE+SAM_TCN_CV_OFFSET)
#define SAM_TC2_RA (SAM_TC2_BASE+SAM_TCN_RA_OFFSET)
#define SAM_TC2_RB (SAM_TC2_BASE+SAM_TCN_RB_OFFSET)
#define SAM_TC2_RC (SAM_TC2_BASE+SAM_TCN_RC_OFFSET)
#define SAM_TC2_SR (SAM_TC2_BASE+SAM_TCN_SR_OFFSET)
#define SAM_TC2_IER (SAM_TC2_BASE+SAM_TCN_IER_OFFSET)
#define SAM_TC2_IDR (SAM_TC2_BASE+SAM_TCN_IDR_OFFSET)
#define SAM_TC2_IMR (SAM_TC2_BASE+SAM_TCN_IMR_OFFSET)
/* Timer common registers */
#define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET)
#define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET)
#define SAM_TC_QIER (SAM_TC_BASE+SAM_TC_QIER_OFFSET)
#define SAM_TC_QIDR (SAM_TC_BASE+SAM_TC_QIDR_OFFSET)
#define SAM_TC_QIMR (SAM_TC_BASE+SAM_TC_QIMR_OFFSET)
#define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET)
/* TC register bit definitions ******************************************************************/
/* Timer common registers */
/* TC Block Control Register */
#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command
/* TC Block Mode Register */
#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */
#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT)
# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT)
# define TC_BMR_TC0XC0S_NONE (1 << TC_BMR_TC0XC0S_SHIFT)
# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT)
# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT)
#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */
#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_MASK)
# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT)
# define TC_BMR_TC1XC1S_NONE (1 << TC_BMR_TC1XC1S_SHIFT)
# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT)
# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT)
#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */
#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT)
#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */
#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */
#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */
#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding Transparent */
#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */
#define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */
#define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */
#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */
#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */
#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */
#define TC_BMR_FILTER (1 << 19) /* Bit 19 */
#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */
#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT)
/* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register,
* TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common
* bit field definitions
*/
#define TC_QINT_IDX (1 << 0) /* Bit 0: Index (Common) */
#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction Change (Common) */
#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */
#define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */
/* Timer Channel Registers */
/* TC Channel Control Register */
#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */
#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */
#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */
/* TC Channel Mode Register */
#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */
#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT)
# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT)
#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */
#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */
#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK)
#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK)
# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */
# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */
# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */
# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */
#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */
#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */
#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */
#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */
#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT)
# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */
# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */
# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */
# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */
#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */
#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */
#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */
#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT)
# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */
# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */
# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */
# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */
#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */
#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT)
# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */
# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */
# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */
# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */
#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */
#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */
#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */
#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT)
# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */
# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */
# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */
# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */
#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */
#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT)
# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */
# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */
# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */
# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */
#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */
#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */
#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT)
# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */
# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */
# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */
# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */
#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */
#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT)
# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT)
# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT)
# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT)
# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT)
#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */
#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT)
# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT)
# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT)
# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT)
# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT)
#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */
#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT)
# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT)
# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT)
# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT)
# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT)
#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */
#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT)
# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT)
# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT)
# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT)
# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT)
#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */
#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT)
# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT)
# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT)
# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT)
# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT)
#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */
#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT)
# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT)
# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT)
# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT)
# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT)
#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */
#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT)
# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT)
# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT)
# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT)
# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT)
#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */
#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT)
# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT)
# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT)
# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT)
# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT)
/* TC Counter Value Register */
#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */
#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT)
/* TC Register A, B, C */
#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */
#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT)
/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */
#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */
#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */
#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */
#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */
#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */
#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */
#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */
#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */
#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */
#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */
#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/
/************************************************************************************************
* Public Types
************************************************************************************************/
/************************************************************************************************
* Public Data
************************************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_TC_H */
arch/arm/src/sam3u/chip/sam_twi.h
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/****************************************************************************************
* arch/arm/src/sam3u/chip/sam_twi.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_TWI_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_TWI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* TWI register offsets *****************************************************************/
#define SAM_TWI_CR_OFFSET 0x00 /* Control Register */
#define SAM_TWI_MMR_OFFSET 0x04 /* Master Mode Register */
#define SAM_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */
#define SAM_TWI_IADR_OFFSET 0x0c /* Internal Address Register */
#define SAM_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */
#define SAM_TWI_SR_OFFSET 0x20 /* Status Register */
#define SAM_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */
#define SAM_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */
#define SAM_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */
#define SAM_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */
#define SAM_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */
/* 0x38-0xfc: Reserved */
/* 0x100-0x124: Reserved for the PDC */
/* TWI register adresses ****************************************************************/
#define SAM_TWI_CR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CR_OFFSET)
#define SAM_TWI_MMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_MMR_OFFSET)
#define SAM_TWI_SMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_SMR_OFFSET)
#define SAM_TWI_IADR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IADR_OFFSET)
#define SAM_TWI_CWGR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CWGR_OFFSET)
#define SAM_TWI_SR(n) (SAM_TWIN_BASE(n)+SAM_TWI_SR_OFFSET)
#define SAM_TWI_IER(n) (SAM_TWIN_BASE(n)+SAM_TWI_IER_OFFSET)
#define SAM_TWI_IDR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IDR_OFFSET)
#define SAM_TWI_IMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IMR_OFFSET)
#define SAM_TWI_RHR(n) (SAM_TWIN_BASE(n)+SAM_TWI_RHR_OFFSET)
#define SAM_TWI_THR(n) (SAM_TWIN_BASE(n)+SAM_TWI_THR_OFFSET)
#define SAM_TWI0_CR (SAM_TWI0_BASE+SAM_TWI_CR_OFFSET)
#define SAM_TWI0_MMR (SAM_TWI0_BASE+SAM_TWI_MMR_OFFSET)
#define SAM_TWI0_SMR (SAM_TWI0_BASE+SAM_TWI_SMR_OFFSET)
#define SAM_TWI0_IADR (SAM_TWI0_BASE+SAM_TWI_IADR_OFFSET)
#define SAM_TWI0_CWGR (SAM_TWI0_BASE+SAM_TWI_CWGR_OFFSET)
#define SAM_TWI0_SR (SAM_TWI0_BASE+SAM_TWI_SR_OFFSET)
#define SAM_TWI0_IER (SAM_TWI0_BASE+SAM_TWI_IER_OFFSET)
#define SAM_TWI0_IDR (SAM_TWI0_BASE+SAM_TWI_IDR_OFFSET)
#define SAM_TWI0_IMR (SAM_TWI0_BASE+SAM_TWI_IMR_OFFSET)
#define SAM_TWI0_RHR (SAM_TWI0_BASE+SAM_TWI_RHR_OFFSET)
#define SAM_TWI0_THR (SAM_TWI0_BASE+SAM_TWI_THR_OFFSET)
#define SAM_TWI1_CR (SAM_TWI1_BASE+SAM_TWI_CR_OFFSET)
#define SAM_TWI1_MMR (SAM_TWI1_BASE+SAM_TWI_MMR_OFFSET)
#define SAM_TWI1_SMR (SAM_TWI1_BASE+SAM_TWI_SMR_OFFSET)
#define SAM_TWI1_IADR (SAM_TWI1_BASE+SAM_TWI_IADR_OFFSET)
#define SAM_TWI1_CWGR (SAM_TWI1_BASE+SAM_TWI_CWGR_OFFSET)
#define SAM_TWI1_SR (SAM_TWI1_BASE+SAM_TWI_SR_OFFSET)
#define SAM_TWI1_IER (SAM_TWI1_BASE+SAM_TWI_IER_OFFSET)
#define SAM_TWI1_IDR (SAM_TWI1_BASE+SAM_TWI_IDR_OFFSET)
#define SAM_TWI1_IMR (SAM_TWI1_BASE+SAM_TWI_IMR_OFFSET)
#define SAM_TWI1_RHR (SAM_TWI1_BASE+SAM_TWI_RHR_OFFSET)
#define SAM_TWI1_THR (SAM_TWI1_BASE+SAM_TWI_THR_OFFSET)
/* TWI register bit definitions *********************************************************/
/* TWI Control Register */
#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */
#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */
#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */
#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */
#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */
#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */
#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */
#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
/* TWI Master Mode Register */'
#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */
#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT)
# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */
# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */
# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */
#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT)
/* TWI Slave Mode Register */
#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */
#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT)
/* TWI Internal Address Register */
#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */
#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT)
/* TWI Clock Waveform Generator Register */
#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */
#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */
#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */
#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT)
/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable
* Register, and TWI Interrupt Mask Register common bit fields.
*/
#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */
#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */
#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */
#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */
#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */
#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */
#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */
#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */
#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */
#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */
#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */
#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */
#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */
#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */
#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */
/* TWI Receive Holding Register */
#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */
#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT)
/* TWI Transmit Holding Register */
#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */
#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_TWI_H */
arch/arm/src/sam3u/chip/sam_uart.h
+391
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/************************************************************************************************
* arch/arm/src/sam3u/chip/sam_uart.h
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_UART_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_UART_H
/************************************************************************************************
* Included Files
************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* UART register offsets ************************************************************************/
#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */
#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */
#define SAM_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */
#define SAM_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */
#define SAM_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */
#define SAM_UART_SR_OFFSET 0x0014 /* Status Register (Common) */
#define SAM_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */
#define SAM_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */
#define SAM_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */
/* 0x0024-0x003c: Reserved (UART) */
#define SAM_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */
#define SAM_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */
/* 0x002c-0x003c: Reserved (UART) */
#define SAM_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */
#define SAM_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */
/* 0x0048: Reserved (USART) */
#define SAM_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */
#define SAM_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */
#define SAM_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */
#define SAM_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */
/* 0x005c-0xf008: Reserved (USART) */
#define SAM_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */
/* 0x0100-0x0124: PDC Area (Common) */
/* UART register adresses ***********************************************************************/
#define SAM_UART_CR (SAM_UART_BASE+SAM_UART_CR_OFFSET)
#define SAM_UART_MR (SAM_UART_BASE+SAM_UART_MR_OFFSET)
#define SAM_UART_IER (SAM_UART_BASE+SAM_UART_IER_OFFSET)
#define SAM_UART_IDR (SAM_UART_BASE+SAM_UART_IDR_OFFSET)
#define SAM_UART_IMR (SAM_UART_BASE+SAM_UART_IMR_OFFSET)
#define SAM_UART_SR (SAM_UART_BASE+SAM_UART_SR_OFFSET)
#define SAM_UART_RHR (SAM_UART_BASE+SAM_UART_RHR_OFFSET)
#define SAM_UART_THR (SAM_UART_BASE+SAM_UART_THR_OFFSET)
#define SAM_UART_BRGR (SAM_UART_BASE+SAM_UART_BRGR_OFFSET)
#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET)
#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET)
#define SAM_USART_IER(n) (SAM_USARTN_BASE(n)+SAM_UART_IER_OFFSET)
#define SAM_USART_IDR(n) (SAM_USARTN_BASE(n)+SAM_UART_IDR_OFFSET)
#define SAM_USART_IMR(n) (SAM_USARTN_BASE(n)+SAM_UART_IMR_OFFSET)
#define SAM_USART_SR(n) (SAM_USARTN_BASE(n)+SAM_UART_SR_OFFSET)
#define SAM_USART_RHR(n) (SAM_USARTN_BASE(n)+SAM_UART_RHR_OFFSET)
#define SAM_USART_THR(n) (SAM_USARTN_BASE(n)+SAM_UART_THR_OFFSET)
#define SAM_USART_BRGR(n) (SAM_USARTN_BASE(n)+SAM_UART_BRGR_OFFSET)
#define SAM_USART_RTOR(n) (SAM_USARTN_BASE(n)+SAM_USART_RTOR_OFFSET)
#define SAM_USART_TTGR(n) (SAM_USARTN_BASE(n)+SAM_USART_TTGR_OFFSET)
#define SAM_USART_FIDI(n) (SAM_USARTN_BASE(n)+SAM_USART_FIDI_OFFSET)
#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_USART_NER_OFFSET)
#define SAM_USART_IF(n) (SAM_USARTN_BASE(n)+SAM_USART_IF_OFFSET)
#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_USART_MAN_OFFSET)
#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPMR_OFFSET)
#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_USART_WPSR_OFFSET)
#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_USART_VERSION_OFFSET)
#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET)
#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET)
#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET)
#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET)
#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET)
#define SAM_USART0_SR (SAM_USART0_BASE+SAM_UART_SR_OFFSET)
#define SAM_USART0_RHR (SAM_USART0_BASE+SAM_UART_RHR_OFFSET)
#define SAM_USART0_THR (SAM_USART0_BASE+SAM_UART_THR_OFFSET)
#define SAM_USART0_BRGR (SAM_USART0_BASE+SAM_UART_BRGR_OFFSET)
#define SAM_USART0_RTOR (SAM_USART0_BASE+SAM_USART_RTOR_OFFSET)
#define SAM_USART0_TTGR (SAM_USART0_BASE+SAM_USART_TTGR_OFFSET)
#define SAM_USART0_FIDI (SAM_USART0_BASE+SAM_USART_FIDI_OFFSET)
#define SAM_USART0_NER (SAM_USART0_BASE+SAM_USART_NER_OFFSET)
#define SAM_USART0_IF (SAM_USART0_BASE+SAM_USART_IF_OFFSET)
#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_USART_MAN_OFFSET)
#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_USART_WPMR_OFFSET)
#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_USART_WPSR_OFFSET)
#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_USART_VERSION_OFFSET)
#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET)
#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET)
#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET)
#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET)
#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET)
#define SAM_USART1_SR (SAM_USART1_BASE+SAM_UART_SR_OFFSET)
#define SAM_USART1_RHR (SAM_USART1_BASE+SAM_UART_RHR_OFFSET)
#define SAM_USART1_THR (SAM_USART1_BASE+SAM_UART_THR_OFFSET)
#define SAM_USART1_BRGR (SAM_USART1_BASE+SAM_UART_BRGR_OFFSET)
#define SAM_USART1_RTOR (SAM_USART1_BASE+SAM_USART_RTOR_OFFSET)
#define SAM_USART1_TTGR (SAM_USART1_BASE+SAM_USART_TTGR_OFFSET)
#define SAM_USART1_FIDI (SAM_USART1_BASE+SAM_USART_FIDI_OFFSET)
#define SAM_USART1_NER (SAM_USART1_BASE+SAM_USART_NER_OFFSET)
#define SAM_USART1_IF (SAM_USART1_BASE+SAM_USART_IF_OFFSET)
#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_USART_MAN_OFFSET)
#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_USART_WPMR_OFFSET)
#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_USART_WPSR_OFFSET)
#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_USART_VERSION_OFFSET)
#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET)
#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET)
#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET)
#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET)
#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET)
#define SAM_USART2_SR (SAM_USART2_BASE+SAM_UART_SR_OFFSET)
#define SAM_USART2_RHR (SAM_USART2_BASE+SAM_UART_RHR_OFFSET)
#define SAM_USART2_THR (SAM_USART2_BASE+SAM_UART_THR_OFFSET)
#define SAM_USART2_BRGR (SAM_USART2_BASE+SAM_UART_BRGR_OFFSET)
#define SAM_USART2_RTOR (SAM_USART2_BASE+SAM_USART_RTOR_OFFSET)
#define SAM_USART2_TTGR (SAM_USART2_BASE+SAM_USART_TTGR_OFFSET)
#define SAM_USART2_FIDI (SAM_USART2_BASE+SAM_USART_FIDI_OFFSET)
#define SAM_USART2_NER (SAM_USART2_BASE+SAM_USART_NER_OFFSET)
#define SAM_USART2_IF (SAM_USART2_BASE+SAM_USART_IF_OFFSET)
#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_USART_MAN_OFFSET)
#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_USART_WPMR_OFFSET)
#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_USART_WPSR_OFFSET)
#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_USART_VERSION_OFFSET)
#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET)
#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET)
#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET)
#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET)
#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET)
#define SAM_USART3_SR (SAM_USART3_BASE+SAM_UART_SR_OFFSET)
#define SAM_USART3_RHR (SAM_USART3_BASE+SAM_UART_RHR_OFFSET)
#define SAM_USART3_THR (SAM_USART3_BASE+SAM_UART_THR_OFFSET)
#define SAM_USART3_BRGR (SAM_USART3_BASE+SAM_UART_BRGR_OFFSET)
#define SAM_USART3_RTOR (SAM_USART3_BASE+SAM_USART_RTOR_OFFSET)
#define SAM_USART3_TTGR (SAM_USART3_BASE+SAM_USART_TTGR_OFFSET)
#define SAM_USART3_FIDI (SAM_USART3_BASE+SAM_USART_FIDI_OFFSET)
#define SAM_USART3_NER (SAM_USART3_BASE+SAM_USART_NER_OFFSET)
#define SAM_USART3_IF (SAM_USART3_BASE+SAM_USART_IF_OFFSET)
#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_USART_MAN_OFFSET)
#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_USART_WPMR_OFFSET)
#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_USART_WPSR_OFFSET)
#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_USART_VERSION_OFFSET)
/* UART register bit definitions ****************************************************************/
/* UART Control Register */
#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */
#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */
#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */
#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */
#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */
#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */
#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */
#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */
#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */
#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */
#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */
#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */
#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */
#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */
#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */
#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */
#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */
#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */
/* UART Mode Register */
#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */
#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT)
# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */
# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */
# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */
# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */
# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */
# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */
# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */
# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */
#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */
#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT)
# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */
# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */
# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */
#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */
#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT)
# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */
# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */
# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */
# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */
#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */
#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */
#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */
#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT)
# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */
# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */
# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */
# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */
# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */
# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */
#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */
#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT)
# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */
# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */
#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */
#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT)
# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */
# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */
# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */
# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */
#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */
#define USART_MR_CPOL (1 << 16)
#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */
#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */
#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */
#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */
#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */
#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */
#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */
#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */
#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT)
#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */
#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */
#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */
#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */
/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask
* Register, and UART Status Register common bit field definitions
*/
#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */
#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */
#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */
#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */
#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */
#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */
#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */
#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */
#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */
#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */
#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */
#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */
#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */
#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */
#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */
#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */
#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */
/* UART Receiver Holding Register */
#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */
#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT)
#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */
#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT)
#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */
/* UART Transmit Holding Register */
#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */
#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT)
#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */
#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT)
#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */
/* UART Baud Rate Generator Register */
#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */
#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT)
#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */
#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT)
/* USART Receiver Time-out Register (USART only) */
#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */
#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT)
/* USART Transmitter Timeguard Register (USART only) */
#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */
#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT)
/* USART FI DI RATIO Register (USART only) */
#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */
#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT)
/* USART Number of Errors Register (USART only) */
#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */
#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT)
/* USART IrDA FILTER Register (USART only) */
#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */
#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT)
/* USART Manchester Configuration Register (USART only) */
#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */
#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT)
#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */
#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT)
# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */
# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */
# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */
# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */
#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */
#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */
#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT)
#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */
#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT)
# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */
# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */
# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */
# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */
#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */
#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */
/* USART Write Protect Mode Register (USART only) */
#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */
#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */
#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT)
/* USART Write Protect Status Register (USART only) */
#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */
#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */
#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT)
/* USART Version Register */
#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */
#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT)
#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */
#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT)
/************************************************************************************************
* Public Types
************************************************************************************************/
/************************************************************************************************
* Public Data
************************************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_UART_H */
arch/arm/src/sam3u/sam3u_udphs.h → arch/arm/src/sam3u/chip/sam_udphs.h
+92 -92
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_udphs.h
* arch/arm/src/sam3u/chip/sam_udphs.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_UDPHS_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_UDPHS_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,76 +51,76 @@
/* UDPHS register offsets ***************************************************************/
#define SAM3U_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */
#define SAM3U_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */
#define SAM_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */
#define SAM_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */
/* 0x08-0x0C: Reserved */
#define SAM3U_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */
#define SAM3U_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */
#define SAM3U_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */
#define SAM3U_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */
#define SAM_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */
#define SAM_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */
#define SAM_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */
#define SAM_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */
/* 0x20-0xcc: Reserved */
#define SAM3U_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */
#define SAM_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */
/* 0xE4-0xE8: Reserved */
#define SAM3U_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */
#define SAM3U_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */
#define SAM3U_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */
#define SAM_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */
#define SAM_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */
#define SAM_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */
/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180,
* 0x1a0, and 0x1c0
*/
#define SAM3U_UDPHSEP_OFFSET(n) (0x100+((n)<<5))
#define SAM3U_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */
#define SAM3U_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */
#define SAM3U_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */
#define SAM3U_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */
#define SAM_UDPHSEP_OFFSET(n) (0x100+((n)<<5))
#define SAM_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */
#define SAM_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */
#define SAM_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */
#define SAM_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */
/* 0x10: Reserved */
#define SAM3U_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */
#define SAM3U_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */
#define SAM3U_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */
#define SAM_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */
#define SAM_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */
#define SAM_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */
/* 0x1e0-0x300: Reserved */
/* 0x300-0x30c: Reserved */
/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and
* 0x360. NOTE that there is no DMA channel 0.
*/
#define SAM3U_UDPHSDMA_OFFSET(n) (0x310+((n)<<4))
#define SAM3U_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */
#define SAM3U_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */
#define SAM3U_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
#define SAM3U_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */
#define SAM_UDPHSDMA_OFFSET(n) (0x310+((n)<<4))
#define SAM_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */
#define SAM_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */
#define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
#define SAM_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */
/* UDPHS register adresses **************************************************************/
#define SAM3U_UDPHS_CTRL (SAM3U_UDPHS_BASE+SAM3U_UDPHS_CTRL_OFFSET)
#define SAM3U_UDPHS_FNUM (SAM3U_UDPHS_BASE+SAM3U_UDPHS_FNUM_OFFSET)
#define SAM3U_UDPHS_IEN (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IEN_OFFSET)
#define SAM3U_UDPHS_INTSTA (SAM3U_UDPHS_BASE+SAM3U_UDPHS_INTSTA_OFFSET)
#define SAM3U_UDPHS_CLRINT (SAM3U_UDPHS_BASE+ SAM3U_UDPHS_CLRINT_OFFSET)
#define SAM3U_UDPHS_EPTRST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_EPTRST_OFFSET)
#define SAM3U_UDPHS_TST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_TST_OFFSET)
#define SAM3U_UDPHS_IPNAME1 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME1_OFFSET)
#define SAM3U_UDPHS_IPNAME2 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME2_OFFSET)
#define SAM3U_UDPHS_IPFEATURES (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPFEATURES_OFFSET)
#define SAM_UDPHS_CTRL (SAM_UDPHS_BASE+SAM_UDPHS_CTRL_OFFSET)
#define SAM_UDPHS_FNUM (SAM_UDPHS_BASE+SAM_UDPHS_FNUM_OFFSET)
#define SAM_UDPHS_IEN (SAM_UDPHS_BASE+SAM_UDPHS_IEN_OFFSET)
#define SAM_UDPHS_INTSTA (SAM_UDPHS_BASE+SAM_UDPHS_INTSTA_OFFSET)
#define SAM_UDPHS_CLRINT (SAM_UDPHS_BASE+ SAM_UDPHS_CLRINT_OFFSET)
#define SAM_UDPHS_EPTRST (SAM_UDPHS_BASE+SAM_UDPHS_EPTRST_OFFSET)
#define SAM_UDPHS_TST (SAM_UDPHS_BASE+SAM_UDPHS_TST_OFFSET)
#define SAM_UDPHS_IPNAME1 (SAM_UDPHS_BASE+SAM_UDPHS_IPNAME1_OFFSET)
#define SAM_UDPHS_IPNAME2 (SAM_UDPHS_BASE+SAM_UDPHS_IPNAME2_OFFSET)
#define SAM_UDPHS_IPFEATURES (SAM_UDPHS_BASE+SAM_UDPHS_IPFEATURES_OFFSET)
/* Endpoint registers */
#define SAM3U_UDPHSEP_BASE(n)) (SAM3U_UDPHS_BASE+SAM3U_UDPHSEP_OFFSET(n))
#define SAM3U_UDPHSEP_CFG(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CFG_OFFSET)
#define SAM3U_UDPHSEP_CTLENB(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLENB_OFFSET)
#define SAM3U_UDPHSEP_CTLDIS(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLDIS_OFFSET)
#define SAM3U_UDPHSEP_CTL(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTL_OFFSET)
#define SAM3U_UDPHSEP_SETSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_SETSTA_OFFSET)
#define SAM3U_UDPHSEP_CLRSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CLRSTA_OFFSET)
#define SAM3U_UDPHSEP_STA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_STA_OFFSET)
#define SAM_UDPHSEP_BASE(n)) (SAM_UDPHS_BASE+SAM_UDPHSEP_OFFSET(n))
#define SAM_UDPHSEP_CFG(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CFG_OFFSET)
#define SAM_UDPHSEP_CTLENB(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CTLENB_OFFSET)
#define SAM_UDPHSEP_CTLDIS(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CTLDIS_OFFSET)
#define SAM_UDPHSEP_CTL(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CTL_OFFSET)
#define SAM_UDPHSEP_SETSTA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_SETSTA_OFFSET)
#define SAM_UDPHSEP_CLRSTA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CLRSTA_OFFSET)
#define SAM_UDPHSEP_STA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_STA_OFFSET)
/* DMA Channel Registers*/
#define SAM3U_UDPHSDMA_BASE(n) (SAM3U_UDPHS_BASE+SAM3U_UDPHSDMA_OFFSET(n))
#define SAM3U_UDPHSDMA_NXTDSC(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_NXTDSC_OFFSET)
#define SAM3U_UDPHSDMA_ADDRESS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_ADDRESS_OFFSET)
#define SAM3U_UDPHSDMA_CONTROL(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_CONTROL_OFFSET)
#define SAM3U_UDPHSDMA_STATUS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_STATUS_OFFSET)
#define SAM_UDPHSDMA_BASE(n) (SAM_UDPHS_BASE+SAM_UDPHSDMA_OFFSET(n))
#define SAM_UDPHSDMA_NXTDSC(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_NXTDSC_OFFSET)
#define SAM_UDPHSDMA_ADDRESS(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_ADDRESS_OFFSET)
#define SAM_UDPHSDMA_CONTROL(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_CONTROL_OFFSET)
#define SAM_UDPHSDMA_STATUS(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_STATUS_OFFSET)
/* UDPHS register bit definitions *******************************************************/
/* UDPHS Control Register */
@@ -308,52 +308,52 @@
# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */
# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */
# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */
#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */
#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */
#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */
#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */
#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */
#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */
#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */
#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */
#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */
#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */
#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */
#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */
#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */
#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */
#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */
#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK)
#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */
#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT)
#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */
#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT)
#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */
#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT)
#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet
#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */
#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */
#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */
#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */
#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */
#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */
#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */
#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */
#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */
#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */
#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */
#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */
#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */
#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */
#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */
#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK)
#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */
#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT)
#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */
#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT)
#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */
#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT)
#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet
/* UDPHS DMA Channel Control Register */
#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */
#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */
#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */
#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */
#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */
#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */
#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */
#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */
#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */
#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT)
#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */
#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */
#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */
#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */
#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */
#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */
#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */
#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */
#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */
#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT)
/* UDPHS DMA Channel Status Register */
#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */
#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */
#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */
#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */
#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */
#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */
#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT)
#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */
#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */
#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */
#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */
#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */
#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */
#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT)
/****************************************************************************************
* Public Types
@@ -367,5 +367,5 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_UDPHS_H */
arch/arm/src/sam3u/sam3u_wdt.h → arch/arm/src/sam3u/chip/sam_wdt.h
+27 -27
View File
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_wdt.h
* arch/arm/src/sam3u/chip/sam_wdt.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H
#ifndef __ARCH_ARM_SRC_SAM3U_CHIP_SAM_WDT_H
#define __ARCH_ARM_SRC_SAM3U_CHIP_SAM_WDT_H
/****************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
#include "chip/sam_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
@@ -51,35 +51,35 @@
/* WDT register offsets ****************************************************************/
#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */
#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */
#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */
#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */
#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */
#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */
/* WDT register adresses ***************************************************************/
#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET)
#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET)
#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET)
#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET)
#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET)
#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET)
/* WDT register bit definitions ********************************************************/
#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT)
#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */
#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)
#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */
#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT)
#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */
#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */
#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT)
#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
/****************************************************************************************
* Public Types
@@ -93,4 +93,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H */
#endif /* __ARCH_ARM_SRC_SAM3U_CHIP_SAM_WDT_H */
arch/arm/src/sam3u/sam3u_adc.h
-236
View File
@@ -1,236 +0,0 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_adc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* ADC register offsets ****************************************************************/
#define SAM3U_ADC_CR_OFFSET 0x00 /* Control Register (Both) */
#define SAM3U_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */
/* 0x08: Reserved */
/* 0x0c: Reserved */
#define SAM3U_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */
#define SAM3U_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */
#define SAM3U_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */
#define SAM3U_ADC_SR_OFFSET 0x1c /* Status Register (Both) */
#define SAM3U_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */
#define SAM3U_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */
#define SAM3U_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */
#define SAM3U_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */
#define SAM3U_ADC_CDR_OFFSET(n) (0x30+((n)<<2))
#define SAM3U_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */
#define SAM3U_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */
#define SAM3U_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */
#define SAM3U_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */
#define SAM3U_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */
#define SAM3U_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */
#define SAM3U_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */
#define SAM3U_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */
#define SAM3U_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
#define SAM3U_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
/* ADC register adresses ***************************************************************/
#define SAM3U_ADC12B_CR (SAM3U_ADC12B_BASE+SAM3U_ADC_CR_OFFSET)
#define SAM3U_ADC12B_MR (SAM3U_ADC12B_BASE+SAM3U_ADC_MR_OFFSET)
#define SAM3U_ADC12B_CHER (SAM3U_ADC12B_BASE+SAM3U_ADC_CHER_OFFSET)
#define SAM3U_ADC12B_CHDR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHDR_OFFSET)
#define SAM3U_ADC12B_CHSR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHSR_OFFSET)
#define SAM3U_ADC12B_SR (SAM3U_ADC12B_BASE+SAM3U_ADC_SR_OFFSET)
#define SAM3U_ADC12B_LCDR_ (SAM3U_ADC12B_BASE+SAM3U_ADC_LCDR_OFFSET)
#define SAM3U_ADC12B_IER (SAM3U_ADC12B_BASE+SAM3U_ADC_IER_OFFSET)
#define SAM3U_ADC12B_IDR (SAM3U_ADC12B_BASE+SAM3U_ADC_IDR_OFFSET)
#define SAM3U_ADC12B_IMR (SAM3U_ADC12B_BASE+SAM3U_ADC_IMR_OFFSET)
#define SAM3U_ADC12B_CDR(n)) (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR_OFFSET(n))
#define SAM3U_ADC12B_CDR0 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR0_OFFSET)
#define SAM3U_ADC12B_CDR1 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR1_OFFSET)
#define SAM3U_ADC12B_CDR2 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR2_OFFSET)
#define SAM3U_ADC12B_CDR3 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR3_OFFSET)
#define SAM3U_ADC12B_CDR4 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR4_OFFSET)
#define SAM3U_ADC12B_CDR5 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR5_OFFSET)
#define SAM3U_ADC12B_CDR6 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR6_OFFSET)
#define SAM3U_ADC12B_CDR7 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR7_OFFSET)
#define SAM3U_ADC12B_ACR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_ACR_OFFSET)
#define SAM3U_ADC12B_EMR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_EMR_OFFSET)
#define SAM3U_ADC_CR (SAM3U_ADC_BASE+SAM3U_ADC_CR_OFFSET)
#define SAM3U_ADC_MR (SAM3U_ADC_BASE+SAM3U_ADC_MR_OFFSET)
#define SAM3U_ADC_CHER (SAM3U_ADC_BASE+SAM3U_ADC_CHER_OFFSET)
#define SAM3U_ADC_CHDR (SAM3U_ADC_BASE+SAM3U_ADC_CHDR_OFFSET)
#define SAM3U_ADC_CHSR (SAM3U_ADC_BASE+SAM3U_ADC_CHSR_OFFSET)
#define SAM3U_ADC_SR (SAM3U_ADC_BASE+SAM3U_ADC_SR_OFFSET)
#define SAM3U_ADC_LCDR (SAM3U_ADC_BASE+SAM3U_ADC_LCDR_OFFSET)
#define SAM3U_ADC_IER (SAM3U_ADC_BASE+SAM3U_ADC_IER_OFFSET)
#define SAM3U_ADC_IDR (SAM3U_ADC_BASE+SAM3U_ADC_IDR_OFFSET)
#define SAM3U_ADC_IMR (SAM3U_ADC_BASE+SAM3U_ADC_IMR_OFFSET)
#define SAM3U_ADC_CDR(n)) (SAM3U_ADC_BASE+SAM3U_ADC_CDR_OFFSET(n))
#define SAM3U_ADC_CDR0 (SAM3U_ADC_BASE+SAM3U_ADC_CDR0_OFFSET)
#define SAM3U_ADC_CDR1 (SAM3U_ADC_BASE+SAM3U_ADC_CDR1_OFFSET)
#define SAM3U_ADC_CDR2 (SAM3U_ADC_BASE+SAM3U_ADC_CDR2_OFFSET)
#define SAM3U_ADC_CDR3 (SAM3U_ADC_BASE+SAM3U_ADC_CDR3_OFFSET)
#define SAM3U_ADC_CDR4 (SAM3U_ADC_BASE+SAM3U_ADC_CDR4_OFFSET)
#define SAM3U_ADC_CDR5 (SAM3U_ADC_BASE+SAM3U_ADC_CDR5_OFFSET)
#define SAM3U_ADC_CDR6 (SAM3U_ADC_BASE+SAM3U_ADC_CDR6_OFFSET)
#define SAM3U_ADC_CDR7 (SAM3U_ADC_BASE+SAM3U_ADC_CDR7_OFFSET)
/* ADC register bit definitions ********************************************************/
/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */
#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */
#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */
/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */
#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT)
#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */
#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */
#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT)
#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */
#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT
#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */
#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT)
#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */
#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel
* Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register,
* and ADC(10B) Channel Status Register common bit-field definitions
*/
#define ADC_CH(n) (1 << (n))
#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */
#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */
#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */
#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */
#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */
#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */
#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */
#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */
/* ADC12B Analog Control Register (ADC12B only) */
#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */
#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT)
#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */
#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT)
#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */
#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */
/* ADC12B Extended Mode Register (ADC12B only) */
#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */
#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */
#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT)
/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt
* Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register,
* ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and
* ADC(10B) Interrupt Mask Register common bit-field definitions
*/
#define ADC_INT_EOC(n) (1<<(n))
#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */
#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */
#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */
#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */
#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */
#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */
#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */
#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */
#define ADC_INT_OVRE(n) (1<<((n)+8))
#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */
#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */
#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */
#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */
#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */
#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */
#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */
#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */
#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */
#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */
#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */
#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */
/* ADC12B Last Converted Data Register */
#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */
#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT)
/* ADC(10B) Last Converted Data Register */
#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */
#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT)
/* ADC12B Channel Data Register */
#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */
#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT)
/* ADC(10B) Channel Data Register */
#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */
#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H */
arch/arm/src/sam3u/sam3u_allocateheap.c
+9 -9
View File
@@ -61,21 +61,21 @@
# warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP"
#endif
#if CONFIG_MM_REGIONS < 3 && !defined(CONFIG_SAM3U_NAND)
#if CONFIG_MM_REGIONS < 3 && !defined(CONFIG_SAM34_NAND)
# warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP"
#endif
#if CONFIG_MM_REGIONS > 2 && defined(CONFIG_SAM3U_NAND)
#if CONFIG_MM_REGIONS > 2 && defined(CONFIG_SAM34_NAND)
# error "CONFIG_MM_REGIONS > 3 but cannot used NFC SRAM"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
#endif
#if CONFIG_DRAM_END > (SAM3U_INTSRAM0_BASE+CONFIG_SAM3U_SRAM0_SIZE)
#if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE)
# error "CONFIG_DRAM_END is beyond the end of SRAM0"
# undef CONFIG_DRAM_END
# define CONFIG_DRAM_END (SAM3U_INTSRAM0_BASE+CONFIG_SAM3U_SRAM0_SIZE)
#elif CONFIG_DRAM_END < (SAM3U_INTSRAM0_BASE+CONFIG_SAM3U_SRAM0_SIZE)
# define CONFIG_DRAM_END (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE)
#elif CONFIG_DRAM_END < (SAM_INTSRAM0_BASE+CONFIG_SAM34_SRAM0_SIZE)
# warning "CONFIG_DRAM_END is before end of SRAM0... not all of SRAM0 used"
#endif
@@ -226,20 +226,20 @@ void up_addregion(void)
{
/* Allow user access to the heap memory */
sam3u_mpu_uheap(SAM3U_INTSRAM1_BASE, CONFIG_SAM3U_SRAM1_SIZE);
sam3u_mpu_uheap(SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM3U_INTSRAM1_BASE, CONFIG_SAM3U_SRAM1_SIZE);
kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, CONFIG_SAM34_SRAM1_SIZE);
#if CONFIG_MM_REGIONS > 2
/* Allow user access to the heap memory */
sam3u_mpu_uheap(SAM3U_NFCSRAM_BASE, CONFIG_SAM3U_NFCSRAM_SIZE);
sam3u_mpu_uheap(SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM3U_NFCSRAM_BASE, CONFIG_SAM3U_NFCSRAM_SIZE);
kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, CONFIG_SAM34_NFCSRAM_SIZE);
#endif
}
#endif
arch/arm/src/sam3u/sam3u_clockconfig.c
+38 -38
View File
@@ -49,11 +49,11 @@
#include "up_arch.h"
#include "up_internal.h"
#include "sam3u_internal.h"
#include "sam3u_pmc.h"
#include "sam3u_eefc.h"
#include "sam3u_wdt.h"
#include "sam3u_supc.h"
#include "sam3u_matrix.h"
#include "chip/sam_pmc.h"
#include "chip/sam_eefc.h"
#include "chip/sam_wdt.h"
#include "chip/sam_supc.h"
#include "chip/sam_matrix.h"
/****************************************************************************
* Pre-processor Definitions
@@ -101,8 +101,8 @@
static inline void sam3u_efcsetup(void)
{
putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM3U_EEFC0_FMR);
putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM3U_EEFC1_FMR);
putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR);
putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR);
}
/****************************************************************************
@@ -115,7 +115,7 @@ static inline void sam3u_efcsetup(void)
static inline void sam3u_wdtsetup(void)
{
putreg32(WDT_MR_WDDIS, SAM3U_WDT_MR);
putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
}
/****************************************************************************
@@ -130,12 +130,12 @@ static inline void sam3u_supcsetup(void)
{
/* Check if the 32-kHz is already selected */
if ((getreg32(SAM3U_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
{
uint32_t delay;
putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM3U_SUPC_CR);
putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR);
for (delay = 0;
(getreg32(SAM3U_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
(getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
delay++);
}
}
@@ -152,7 +152,7 @@ static void sam3u_pmcwait(uint32_t bit)
{
uint32_t delay;
for (delay = 0;
(getreg32(SAM3U_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
(getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
delay++);
}
@@ -170,7 +170,7 @@ static inline void sam3u_pmcsetup(void)
/* Enable main oscillator (if it has not already been selected) */
if ((getreg32(SAM3U_CKGR_MOR) & CKGR_MOR_MOSCSEL) == 0)
if ((getreg32(SAM_CKGR_MOR) & CKGR_MOR_MOSCSEL) == 0)
{
/* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to
* enable the main oscillator, the MOSCXTS bit in the Power Management
@@ -180,10 +180,10 @@ static inline void sam3u_pmcsetup(void)
* indicating that the main clock is valid."
*/
putreg32(BOARD_CKGR_MOR, SAM3U_CKGR_MOR);
putreg32(BOARD_CKGR_MOR, SAM_CKGR_MOR);
sam3u_pmcwait(PMC_INT_MOSCXTS);
}
/* "Switch to the main oscillator. The selection is made by writing the
* MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of
* the Main Clock source is glitch free, so there is no need to run out
@@ -196,7 +196,7 @@ static inline void sam3u_pmcsetup(void)
* 1 = Selection is in progress
*/
putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM3U_CKGR_MOR);
putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM_CKGR_MOR);
sam3u_pmcwait(PMC_INT_MOSCSELS);
/* "Select the master clock. "The Master Clock selection is made by writing
@@ -208,32 +208,32 @@ static inline void sam3u_pmcsetup(void)
* established.
*/
regval = getreg32(SAM3U_PMC_MCKR);
regval = getreg32(SAM_PMC_MCKR);
regval &= ~PMC_MCKR_CSS_MASK;
regval |= PMC_MCKR_CSS_MAIN;
putreg32(regval, SAM3U_PMC_MCKR);
putreg32(regval, SAM_PMC_MCKR);
sam3u_pmcwait(PMC_INT_MCKRDY);
/* Settup PLLA and wait for LOCKA */
putreg32(BOARD_CKGR_PLLAR, SAM3U_CKGR_PLLAR);
putreg32(BOARD_CKGR_PLLAR, SAM_CKGR_PLLAR);
sam3u_pmcwait(PMC_INT_LOCKA);
/* Setup UTMI for USB and wait for LOCKU */
#ifdef CONFIG_USBDEV
regval = getreg32(SAM3U_CKGR_UCKR);
regval = getreg32(SAM_CKGR_UCKR);
regval |= BOARD_CKGR_UCKR;
putreg32(regval, SAM3U_CKGR_UCKR);
putreg32(regval, SAM_CKGR_UCKR);
sam3u_pmcwait(PMC_INT_LOCKU);
#endif
/* Switch to the fast clock and wait for MCKRDY */
putreg32(BOARD_PMC_MCKR_FAST, SAM3U_PMC_MCKR);
putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR);
sam3u_pmcwait(PMC_INT_MCKRDY);
putreg32(BOARD_PMC_MCKR, SAM3U_PMC_MCKR);
putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR);
sam3u_pmcwait(PMC_INT_MCKRDY);
}
@@ -251,21 +251,21 @@ static inline void sam3u_enabledefaultmaster(void)
/* Set default master: SRAM0 -> Cortex-M3 System */
regval = getreg32(SAM3U_MATRIX_SCFG0);
regval = getreg32(SAM_MATRIX_SCFG0);
regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
putreg32(regval, SAM3U_MATRIX_SCFG0);
putreg32(regval, SAM_MATRIX_SCFG0);
/* Set default master: SRAM1 -> Cortex-M3 System */
regval = getreg32(SAM3U_MATRIX_SCFG1);
regval = getreg32(SAM_MATRIX_SCFG1);
regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
putreg32(regval, SAM3U_MATRIX_SCFG1);
putreg32(regval, SAM_MATRIX_SCFG1);
/* Set default master: Internal flash0 -> Cortex-M3 Instruction/Data */
regval = getreg32(SAM3U_MATRIX_SCFG3);
regval = getreg32(SAM_MATRIX_SCFG3);
regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
putreg32(regval, SAM3U_MATRIX_SCFG3);
putreg32(regval, SAM_MATRIX_SCFG3);
}
#if 0 /* Not used */
@@ -275,21 +275,21 @@ static inline void sam3u_disabledefaultmaster(void)
/* Clear default master: SRAM0 -> Cortex-M3 System */
regval = getreg32(SAM3U_MATRIX_SCFG0);
regval = getreg32(SAM_MATRIX_SCFG0);
regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
putreg32(regval, SAM3U_MATRIX_SCFG0);
putreg32(regval, SAM_MATRIX_SCFG0);
/* Clear default master: SRAM1 -> Cortex-M3 System */
regval = getreg32(SAM3U_MATRIX_SCFG1);
regval = getreg32(SAM_MATRIX_SCFG1);
regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
putreg32(regval, SAM3U_MATRIX_SCFG1);
putreg32(regval, SAM_MATRIX_SCFG1);
/* Clear default master: Internal flash0 -> Cortex-M3 Instruction/Data */
regval = getreg32(SAM3U_MATRIX_SCFG3);
regval = getreg32(SAM_MATRIX_SCFG3);
regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
putreg32(regval, SAM3U_MATRIX_SCFG3);
putreg32(regval, SAM_MATRIX_SCFG3);
}
#endif
@@ -301,9 +301,9 @@ static inline void sam3u_disabledefaultmaster(void)
* Name: sam3u_clockconfig
*
* Description:
* Called to initialize the SAM3U. This does whatever setup is needed to put the
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
* SoC in a usable state. This includes the initialization of clocking using the
* settings in board.h. (After power-on reset, the sam3u is initiallyrunning on
* settings in board.h. (After power-on reset, the SAM3/4 is initially running on
* a 4MHz internal RC clock). This function also performs other low-level chip
* initialization of the chip including EFC, master clock, IRQ & watchdog
* configuration.
@@ -319,7 +319,7 @@ void sam3u_clockconfig(void)
/* Configure the watchdog timer */
sam3u_wdtsetup();
/* Setup the supply controller to use the external slow clock */
sam3u_supcsetup();
arch/arm/src/sam3u/sam3u_dmac.c
+96 -96
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sam3u-ek/sam3u_dmac.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -56,8 +56,8 @@
#include "chip.h"
#include "sam3u_internal.h"
#include "sam3u_pmc.h"
#include "sam3u_dmac.h"
#include "chip/sam_pmc.h"
#include "chip/sam_dmac.h"
/****************************************************************************
* Pre-processor Definitions
@@ -67,7 +67,7 @@
/* Condition out the whole file unless DMA is selected in the configuration */
#ifdef CONFIG_SAM3U_DMA
#ifdef CONFIG_SAM34_DMA
/* If AT90SAM3U support is enabled, then OS DMA support should also be enabled */
@@ -77,15 +77,15 @@
/* Check the number of link list descriptors to allocate */
#ifndef CONFIG_SAM3U_NLLDESC
# define CONFIG_SAM3U_NLLDESC CONFIG_SAM3U_NDMACHAN
#ifndef CONFIG_SAM34_NLLDESC
# define CONFIG_SAM34_NLLDESC CONFIG_SAM34_NDMACHAN
#endif
#if CONFIG_SAM3U_NLLDESC < CONFIG_SAM3U_NDMACHAN
# warning "At least CONFIG_SAM3U_NDMACHAN descriptors must be allocated"
#if CONFIG_SAM34_NLLDESC < CONFIG_SAM34_NDMACHAN
# warning "At least CONFIG_SAM34_NDMACHAN descriptors must be allocated"
# undef CONFIG_SAM3U_NLLDESC
# define CONFIG_SAM3U_NLLDESC CONFIG_SAM3U_NDMACHAN
# undef CONFIG_SAM34_NLLDESC
# define CONFIG_SAM34_NLLDESC CONFIG_SAM34_NDMACHAN
#endif
/* Register values **********************************************************/
@@ -146,40 +146,40 @@ static const uint32_t g_fifocfg[3] =
/* This array describes the available link list descriptors */
static struct dma_linklist_s g_linklist[CONFIG_SAM3U_NLLDESC];
static struct dma_linklist_s g_linklist[CONFIG_SAM34_NLLDESC];
/* This array describes the state of each DMA */
static struct sam3u_dma_s g_dma[CONFIG_SAM3U_NDMACHAN] =
static struct sam3u_dma_s g_dma[CONFIG_SAM34_NDMACHAN] =
{
#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E
/* the AT91SAM3U4E has four DMA channels. The FIFOs for channels 0-2 are
* 8 bytes in size; channel 3 is 32 bytes.
*/
#if CONFIG_SAM3U_NDMACHAN != 4
# error "Logic here assumes CONFIG_SAM3U_NDMACHAN is 4"
#if CONFIG_SAM34_NDMACHAN != 4
# error "Logic here assumes CONFIG_SAM34_NDMACHAN is 4"
#endif
{
.chan = 0,
.flags = DMACH_FLAG_FIFO_8BYTES,
.base = SAM3U_DMACHAN0_BASE,
.base = SAM_DMACHAN0_BASE,
},
{
.chan = 1,
.flags = DMACH_FLAG_FIFO_8BYTES,
.base = SAM3U_DMACHAN1_BASE,
.base = SAM_DMACHAN1_BASE,
},
{
.chan = 2,
.flags = DMACH_FLAG_FIFO_8BYTES,
.base = SAM3U_DMACHAN2_BASE,
.base = SAM_DMACHAN2_BASE,
},
{
.chan = 3,
.flags = (DMACH_FLAG_FIFO_32BYTES | DMACH_FLAG_FLOWCONTROL),
.base = SAM3U_DMACHAN3_BASE,
.base = SAM_DMACHAN3_BASE,
}
#else
# error "Nothing is known about the DMA channels for this device"
@@ -330,7 +330,7 @@ static inline uint32_t sam3u_rxcfg(struct sam3u_dma_s *dmach)
uint32_t regval;
/* Set received (peripheral to memory) DMA channel config */
regval = (((dmach->flags & DMACH_FLAG_PERIPHPID_MASK) >> DMACH_FLAG_PERIPHPID_SHIFT) << DMACHAN_CFG_SRCPER_SHIFT);
regval |= (dmach->flags & DMACH_FLAG_PERIPHH2SEL) != 0 ? DMACHAN_CFG_SRCH2SEL : 0;
regval |= (((dmach->flags & DMACH_FLAG_MEMPID_MASK) >> DMACH_FLAG_MEMPID_SHIFT) << DMACHAN_CFG_DSTPER_SHIFT);
@@ -426,7 +426,7 @@ static inline uint32_t sam3u_txctrla(struct sam3u_dma_s *dmach,
{
dmasize >>= 2;
}
DEBUGASSERT(dmasize <= DMACHAN_CTRLA_BTSIZE_MAX);
return (txctrlabits & ~DMACHAN_CTRLA_BTSIZE_MASK) | (dmasize << DMACHAN_CTRLA_BTSIZE_SHIFT);
}
@@ -517,7 +517,7 @@ static inline uint32_t sam3u_rxctrla(struct sam3u_dma_s *dmach,
{
dmasize >>= 2;
}
DEBUGASSERT(dmasize <= DMACHAN_CTRLA_BTSIZE_MAX);
return (txctrlabits & ~DMACHAN_CTRLA_BTSIZE_MASK) | (dmasize << DMACHAN_CTRLA_BTSIZE_SHIFT);
}
@@ -534,7 +534,7 @@ static inline uint32_t sam3u_rxctrla(struct sam3u_dma_s *dmach,
static inline uint32_t sam3u_txctrlb(struct sam3u_dma_s *dmach)
{
uint32_t regval;
/* Assume that we will not be using the link list and disable the source
* and destination descriptors. The default will be single transfer mode.
*/
@@ -613,7 +613,7 @@ static inline uint32_t sam3u_txctrlb(struct sam3u_dma_s *dmach)
static inline uint32_t sam3u_rxctrlb(struct sam3u_dma_s *dmach)
{
uint32_t regval;
/* Assume that we will not be using the link list and disable the source and
* destination descriptors. The default will be single transfer mode.
*/
@@ -722,7 +722,7 @@ sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
*/
sam3u_takechsem();
for (i = 0; i < CONFIG_SAM3U_NLLDESC; i++)
for (i = 0; i < CONFIG_SAM34_NLLDESC; i++)
{
if (g_linklist[i].src == 0)
{
@@ -760,7 +760,7 @@ sam3u_allocdesc(struct sam3u_dma_s *dmach, struct dma_linklist_s *prev,
*/
prev->ctrlb &= ~DMACHAN_CTRLB_BOTHDSCR;
/* Link the previous tail to the new tail */
prev->next = (uint32_t)desc;
@@ -849,10 +849,10 @@ static int sam3u_txbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
}
else
{
regval = sam3u_txctrlabits(dmach);
regval = sam3u_txctrlabits(dmach);
ctrlb = sam3u_txctrlb(dmach);
}
ctrla = sam3u_txctrla(dmach, regval, nbytes);
ctrla = sam3u_txctrla(dmach, regval, nbytes);
/* Add the new link list entry */
@@ -897,10 +897,10 @@ static int sam3u_rxbuffer(struct sam3u_dma_s *dmach, uint32_t paddr,
}
else
{
regval = sam3u_rxctrlabits(dmach);
regval = sam3u_rxctrlabits(dmach);
ctrlb = sam3u_rxctrlb(dmach);
}
ctrla = sam3u_rxctrla(dmach, regval, nbytes);
ctrla = sam3u_rxctrla(dmach, regval, nbytes);
/* Add the new link list entry */
@@ -933,24 +933,24 @@ static inline int sam3u_single(struct sam3u_dma_s *dmach)
* the interrupt status register.
*/
(void)getreg32(SAM3U_DMAC_EBCISR);
(void)getreg32(SAM_DMAC_EBCISR);
/* Write the starting source address in the SADDR register */
DEBUGASSERT(llhead != NULL && llhead->src != 0);
putreg32(llhead->src, dmach->base + SAM3U_DMACHAN_SADDR_OFFSET);
putreg32(llhead->src, dmach->base + SAM_DMACHAN_SADDR_OFFSET);
/* Write the starting destination address in the DADDR register */
putreg32(llhead->dest, dmach->base + SAM3U_DMACHAN_DADDR_OFFSET);
putreg32(llhead->dest, dmach->base + SAM_DMACHAN_DADDR_OFFSET);
/* Set up the CTRLA register */
putreg32(llhead->ctrla, dmach->base + SAM3U_DMACHAN_CTRLA_OFFSET);
putreg32(llhead->ctrla, dmach->base + SAM_DMACHAN_CTRLA_OFFSET);
/* Set up the CTRLB register */
putreg32(llhead->ctrlb, dmach->base + SAM3U_DMACHAN_CTRLA_OFFSET);
putreg32(llhead->ctrlb, dmach->base + SAM_DMACHAN_CTRLA_OFFSET);
/* Both the DST and SRC DSCR bits should be '1' in CTRLB */
@@ -958,11 +958,11 @@ static inline int sam3u_single(struct sam3u_dma_s *dmach)
/* Set up the CFG register */
putreg32(dmach->cfg, dmach->base + SAM3U_DMACHAN_CFG_OFFSET);
putreg32(dmach->cfg, dmach->base + SAM_DMACHAN_CFG_OFFSET);
/* Enable the channel by writing a ‘1’ to the CHER enable bit */
putreg32(DMAC_CHER_ENA(dmach->chan), SAM3U_DMAC_CHER);
putreg32(DMAC_CHER_ENA(dmach->chan), SAM_DMAC_CHER);
/* The DMA has been started. Once the transfer completes, hardware sets the
* interrupts and disables the channel. We will received buffer complete and
@@ -973,7 +973,7 @@ static inline int sam3u_single(struct sam3u_dma_s *dmach)
* interrupt).
*/
putreg32(DMAC_EBC_CBTCINTS(dmach->chan), SAM3U_DMAC_EBCIER);
putreg32(DMAC_EBC_CBTCINTS(dmach->chan), SAM_DMAC_EBCIER);
return OK;
}
@@ -1000,27 +1000,27 @@ static inline int sam3u_multiple(struct sam3u_dma_s *dmach)
* status register
*/
(void)getreg32(SAM3U_DMAC_EBCISR);
(void)getreg32(SAM_DMAC_EBCISR);
/* Set up the initial CTRLB register (to enable descriptors) */
putreg32(llhead->ctrlb, dmach->base + SAM3U_DMACHAN_CTRLA_OFFSET);
putreg32(llhead->ctrlb, dmach->base + SAM_DMACHAN_CTRLA_OFFSET);
/* Set up the CTRLB register */
putreg32(llhead->ctrlb, dmach->base + SAM3U_DMACHAN_CTRLA_OFFSET);
putreg32(llhead->ctrlb, dmach->base + SAM_DMACHAN_CTRLA_OFFSET);
/* Write the channel configuration information into the CFG register */
putreg32(dmach->cfg, dmach->base + SAM3U_DMACHAN_CFG_OFFSET);
putreg32(dmach->cfg, dmach->base + SAM_DMACHAN_CFG_OFFSET);
/* Program the DSCR register with the pointer to the firstlink list entry. */
putreg32((uint32_t)llhead, dmach->base + SAM3U_DMACHAN_DSCR_OFFSET);
putreg32((uint32_t)llhead, dmach->base + SAM_DMACHAN_DSCR_OFFSET);
/* Finally, enable the channel by writing a ‘1’ to the CHER enable */
putreg32(DMAC_CHER_ENA(dmach->chan), SAM3U_DMAC_CHER);
putreg32(DMAC_CHER_ENA(dmach->chan), SAM_DMAC_CHER);
/* As each buffer of data is transferred, the CTRLA register is written back
* into the link list entry. The CTRLA contains updated BTSIZE and DONE bits.
@@ -1034,7 +1034,7 @@ static inline int sam3u_multiple(struct sam3u_dma_s *dmach)
* just to handle stall conditions.
*/
putreg32(DMAC_EBC_CHANINTS(dmach->chan), SAM3U_DMAC_EBCIER);
putreg32(DMAC_EBC_CHANINTS(dmach->chan), SAM_DMAC_EBCIER);
return OK;
}
@@ -1050,14 +1050,14 @@ static void sam3u_dmaterminate(struct sam3u_dma_s *dmach, int result)
{
/* Disable all channel interrupts */
putreg32(DMAC_EBC_CHANINTS(dmach->chan), SAM3U_DMAC_EBCIDR);
putreg32(DMAC_EBC_CHANINTS(dmach->chan), SAM_DMAC_EBCIDR);
/* Disable the channel by writing one to the write-only channel disable register */
putreg32(DMAC_CHDR_DIS(dmach->chan), SAM3U_DMAC_CHDR);
putreg32(DMAC_CHDR_DIS(dmach->chan), SAM_DMAC_CHDR);
/* Free the linklist */
sam3u_freelinklist(dmach);
/* Perform the DMA complete callback */
@@ -1089,7 +1089,7 @@ static int sam3u_dmainterrupt(int irq, void *context)
* status bits.
*/
regval = getreg32(SAM3U_DMAC_EBCISR) & getreg32(SAM3U_DMAC_EBCIMR);
regval = getreg32(SAM_DMAC_EBCISR) & getreg32(SAM_DMAC_EBCIMR);
/* Check if the any transfer has completed */
@@ -1097,7 +1097,7 @@ static int sam3u_dmainterrupt(int irq, void *context)
{
/* Yes.. Check each bit to see which channel has interrupted */
for (chndx = 0; chndx < CONFIG_SAM3U_NDMACHAN; chndx++)
for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++)
{
/* Are any interrupts pending for this channel? */
@@ -1131,7 +1131,7 @@ static int sam3u_dmainterrupt(int irq, void *context)
{
/* Write the KEEPON field to clear the STALL states */
putreg32(DMAC_CHER_KEEP(dmach->chan), SAM3U_DMAC_CHER);
putreg32(DMAC_CHER_KEEP(dmach->chan), SAM_DMAC_CHER);
}
}
}
@@ -1158,32 +1158,32 @@ void weak_function up_dmainitialize(void)
{
/* Enable peripheral clock */
putreg32((1 << SAM3U_PID_DMAC), SAM3U_PMC_PCER);
putreg32((1 << SAM_PID_DMAC), SAM_PMC_PCER);
/* Disable all DMA interrupts */
putreg32(DMAC_EBC_ALLINTS, SAM3U_DMAC_EBCIDR);
putreg32(DMAC_EBC_ALLINTS, SAM_DMAC_EBCIDR);
/* Disable all DMA channels */
putreg32(DMAC_CHDR_DIS_ALL, SAM3U_DMAC_CHDR);
putreg32(DMAC_CHDR_DIS_ALL, SAM_DMAC_CHDR);
/* Attach DMA interrupt vector */
(void)irq_attach(SAM3U_IRQ_DMAC, sam3u_dmainterrupt);
(void)irq_attach(SAM_IRQ_DMAC, sam3u_dmainterrupt);
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
up_enable_irq(SAM3U_IRQ_DMAC);
up_enable_irq(SAM_IRQ_DMAC);
/* Enable the DMA controller */
putreg32(DMAC_EN_ENABLE, SAM3U_DMAC_EN);
putreg32(DMAC_EN_ENABLE, SAM_DMAC_EN);
/* Initialize semaphores */
sem_init(&g_chsem, 0, 1);
sem_init(&g_dsem, 0, CONFIG_SAM3U_NDMACHAN);
sem_init(&g_dsem, 0, CONFIG_SAM34_NDMACHAN);
}
/****************************************************************************
@@ -1222,7 +1222,7 @@ DMA_HANDLE sam3u_dmachannel(uint32_t dmach_flags)
dmach = NULL;
sam3u_takechsem();
for (chndx = 0; chndx < CONFIG_SAM3U_NDMACHAN; chndx++)
for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++)
{
struct sam3u_dma_s *candidate = &g_dma[chndx];
if (!candidate->inuse &&
@@ -1236,13 +1236,13 @@ DMA_HANDLE sam3u_dmachannel(uint32_t dmach_flags)
* channel
*/
(void)getreg32(SAM3U_DMAC_EBCISR);
(void)getreg32(SAM_DMAC_EBCISR);
/* Disable the channel by writing one to the write-only channel
* disable register
*/
putreg32(DMAC_CHDR_DIS(chndx), SAM3U_DMAC_CHDR);
putreg32(DMAC_CHDR_DIS(chndx), SAM_DMAC_CHDR);
/* See the DMA channel flags, retaining the fifo size and flow
* control settings which are inherent properties of the FIFO
@@ -1318,7 +1318,7 @@ int sam3u_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t n
/* Increment the memory & peripheral address (if it is appropriate to
* do do).
*/
if ((dmach->flags & DMACH_FLAG_PERIPHINCREMENT) != 0)
{
paddr += DMACHAN_CTRLA_BTSIZE_MAX;
@@ -1368,13 +1368,13 @@ int sam3u_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t n
if (ret == OK);
{
/* Decrement the number of bytes left to transfer */
nbytes -= DMACHAN_CTRLA_BTSIZE_MAX;
/* Increment the memory & peripheral address (if it is appropriate to
* do do).
*/
if ((dmach->flags & DMACH_FLAG_PERIPHINCREMENT) != 0)
{
paddr += DMACHAN_CTRLA_BTSIZE_MAX;
@@ -1449,7 +1449,7 @@ void sam3u_dmastop(DMA_HANDLE handle)
{
struct sam3u_dma_s *dmach = (struct sam3u_dma_s *)handle;
irqstate_t flags;
DEBUGASSERT(dmach != NULL);
flags = irqsave();
sam3u_dmaterminate(dmach, -EINTR);
@@ -1480,23 +1480,23 @@ void sam3u_dmasample(DMA_HANDLE handle, struct sam3u_dmaregs_s *regs)
*/
flags = irqsave();
regs->gcfg = getreg32(SAM3U_DMAC_GCFG);
regs->en = getreg32(SAM3U_DMAC_EN);
regs->sreq = getreg32(SAM3U_DMAC_SREQ);
regs->creq = getreg32(SAM3U_DMAC_CREQ);
regs->last = getreg32(SAM3U_DMAC_LAST);
regs->ebcimr = getreg32(SAM3U_DMAC_EBCIMR);
regs->ebcisr = getreg32(SAM3U_DMAC_EBCISR);
regs->chsr = getreg32(SAM3U_DMAC_CHSR);
regs->gcfg = getreg32(SAM_DMAC_GCFG);
regs->en = getreg32(SAM_DMAC_EN);
regs->sreq = getreg32(SAM_DMAC_SREQ);
regs->creq = getreg32(SAM_DMAC_CREQ);
regs->last = getreg32(SAM_DMAC_LAST);
regs->ebcimr = getreg32(SAM_DMAC_EBCIMR);
regs->ebcisr = getreg32(SAM_DMAC_EBCISR);
regs->chsr = getreg32(SAM_DMAC_CHSR);
/* Sample channel registers */
regs->saddr = getreg32(dmach->base + SAM3U_DMACHAN_SADDR_OFFSET);
regs->daddr = getreg32(dmach->base + SAM3U_DMACHAN_DADDR_OFFSET);
regs->dscr = getreg32(dmach->base + SAM3U_DMACHAN_DSCR_OFFSET);
regs->ctrla = getreg32(dmach->base + SAM3U_DMACHAN_CTRLA_OFFSET);
regs->ctrlb = getreg32(dmach->base + SAM3U_DMACHAN_CTRLB_OFFSET);
regs->cfg = getreg32(dmach->base + SAM3U_DMACHAN_CFG_OFFSET);
regs->saddr = getreg32(dmach->base + SAM_DMACHAN_SADDR_OFFSET);
regs->daddr = getreg32(dmach->base + SAM_DMACHAN_DADDR_OFFSET);
regs->dscr = getreg32(dmach->base + SAM_DMACHAN_DSCR_OFFSET);
regs->ctrla = getreg32(dmach->base + SAM_DMACHAN_CTRLA_OFFSET);
regs->ctrlb = getreg32(dmach->base + SAM_DMACHAN_CTRLB_OFFSET);
regs->cfg = getreg32(dmach->base + SAM_DMACHAN_CFG_OFFSET);
irqrestore(flags);
}
#endif /* CONFIG_DEBUG_DMA */
@@ -1520,21 +1520,21 @@ void sam3u_dmadump(DMA_HANDLE handle, const struct sam3u_dmaregs_s *regs,
dmadbg("%s\n", msg);
dmadbg(" DMA Global Registers:\n");
dmadbg(" GCFG[%08x]: %08x\n", SAM3U_DMAC_GCFG, regs->gcfg);
dmadbg(" EN[%08x]: %08x\n", SAM3U_DMAC_EN, regs->en);
dmadbg(" SREQ[%08x]: %08x\n", SAM3U_DMAC_SREQ, regs->sreq);
dmadbg(" CREQ[%08x]: %08x\n", SAM3U_DMAC_CREQ, regs->creq);
dmadbg(" LAST[%08x]: %08x\n", SAM3U_DMAC_LAST, regs->last);
dmadbg(" EBCIMR[%08x]: %08x\n", SAM3U_DMAC_EBCIMR, regs->ebcimr);
dmadbg(" EBCISR[%08x]: %08x\n", SAM3U_DMAC_EBCISR, regs->ebcisr);
dmadbg(" CHSR[%08x]: %08x\n", SAM3U_DMAC_CHSR, regs->chsr);
dmadbg(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg);
dmadbg(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en);
dmadbg(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq);
dmadbg(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq);
dmadbg(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last);
dmadbg(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr);
dmadbg(" EBCISR[%08x]: %08x\n", SAM_DMAC_EBCISR, regs->ebcisr);
dmadbg(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr);
dmadbg(" DMA Channel Registers:\n");
dmadbg(" SADDR[%08x]: %08x\n", dmach->base + SAM3U_DMACHAN_SADDR_OFFSET, regs->saddr);
dmadbg(" DADDR[%08x]: %08x\n", dmach->base + SAM3U_DMACHAN_DADDR_OFFSET, regs->daddr);
dmadbg(" DSCR[%08x]: %08x\n", dmach->base + SAM3U_DMACHAN_DSCR_OFFSET, regs->dscr);
dmadbg(" CTRLA[%08x]: %08x\n", dmach->base + SAM3U_DMACHAN_CTRLA_OFFSET, regs->ctrla);
dmadbg(" CTRLB[%08x]: %08x\n", dmach->base + SAM3U_DMACHAN_CTRLB_OFFSET, regs->ctrlb);
dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM3U_DMACHAN_CFG_OFFSET, regs->cfg);
dmadbg(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr);
dmadbg(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr);
dmadbg(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr);
dmadbg(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla);
dmadbg(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb);
dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
}
#endif /* CONFIG_DEBUG_DMA */
#endif /* CONFIG_SAM3U_DMA */
#endif /* CONFIG_SAM34_DMA */
arch/arm/src/sam3u/sam3u_eefc.h
-120
View File
@@ -1,120 +0,0 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_eefc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* EEFC register offsets ****************************************************************/
#define SAM3U_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */
#define SAM3U_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */
#define SAM3U_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
#define SAM3U_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
/* EEFC register adresses ***************************************************************/
#define SAM3U_EEFC_FMR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FMR_OFFSET)
#define SAM3U_EEFC_FCR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FCR_OFFSET)
#define SAM3U_EEFC_FSR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FSR_OFFSET)
#define SAM3U_EEFC_FRR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FRR_OFFSET)
#define SAM3U_EEFC0_FMR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET)
#define SAM3U_EEFC0_FCR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET)
#define SAM3U_EEFC0_FSR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FSR_OFFSET)
#define SAM3U_EEFC0_FRR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FRR_OFFSET)
#define SAM3U_EEFC1_FMR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FMR_OFFSET)
#define SAM3U_EEFC1_FCR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FCR_OFFSET)
#define SAM3U_EEFC1_FSR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FSR_OFFSET)
#define SAM3U_EEFC1_FRR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FRR_OFFSET)
/* EEFC register bit definitions ********************************************************/
#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */
#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT)
#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */
#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */
#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT)
# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */
# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */
# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */
# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */
# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */
# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */
# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */
# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */
# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */
# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */
# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */
# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */
# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */
# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */
#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */
#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT)
#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */
#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT)
#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */
#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */
#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H */
arch/arm/src/sam3u/sam3u_gpioirq.c
+48 -48
View File
@@ -55,8 +55,8 @@
#include "up_internal.h"
#include "sam3u_internal.h"
#include "sam3u_pio.h"
#include "sam3u_pmc.h"
#include "chip/sam_pio.h"
#include "chip/sam_pmc.h"
#ifdef CONFIG_GPIO_IRQ
@@ -87,7 +87,7 @@
static inline uint32_t sam3u_gpiobase(uint16_t pinset)
{
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
return SAM3U_PION_BASE(port >> GPIO_PORT_SHIFT);
return SAM_PION_BASE(port >> GPIO_PORT_SHIFT);
}
/****************************************************************************
@@ -113,29 +113,29 @@ static inline int sam3u_gpiopin(uint16_t pinset)
static int sam3u_irqbase(int irq, uint32_t *base, int *pin)
{
if (irq >= SAM3U_IRQ_NIRQS)
if (irq >= SAM_IRQ_NIRQS)
{
#ifdef CONFIG_GPIOA_IRQ
if (irq <= SAM3U_IRQ_PA31)
if (irq <= SAM_IRQ_PA31)
{
*base = SAM3U_PIOA_BASE;
*pin = irq - SAM3U_IRQ_PA0;
*base = SAM_PIOA_BASE;
*pin = irq - SAM_IRQ_PA0;
return OK;
}
#endif
#ifdef CONFIG_GPIOB_IRQ
if (irq <= SAM3U_IRQ_PB31)
if (irq <= SAM_IRQ_PB31)
{
*base = SAM3U_PIOB_BASE;
*pin = irq - SAM3U_IRQ_PB0;
*base = SAM_PIOB_BASE;
*pin = irq - SAM_IRQ_PB0;
return OK;
}
#endif
#ifdef CONFIG_GPIOC_IRQ
if (irq <= SAM3U_IRQ_PC31)
if (irq <= SAM_IRQ_PC31)
{
*base = SAM3U_PIOC_BASE;
*pin = irq - SAM3U_IRQ_PC0;
*base = SAM_PIOC_BASE;
*pin = irq - SAM_IRQ_PC0;
return OK;
}
#endif
@@ -157,7 +157,7 @@ static int up_gpiointerrupt(uint32_t base, int irq0, void *context)
uint32_t bit;
int irq;
pending = getreg32(base+SAM3U_PIO_ISR_OFFSET) & getreg32(base+SAM3U_PIO_IMR_OFFSET);
pending = getreg32(base + SAM_PIO_ISR_OFFSET) & getreg32(base + SAM_PIO_IMR_OFFSET);
for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++)
{
if ((pending & bit) != 0)
@@ -177,21 +177,21 @@ static int up_gpiointerrupt(uint32_t base, int irq0, void *context)
#ifdef CONFIG_GPIOA_IRQ
static int up_gpioainterrupt(int irq, void *context)
{
return up_gpiointerrupt(SAM3U_PIOA_BASE, SAM3U_IRQ_PA0, context);
return up_gpiointerrupt(SAM_PIOA_BASE, SAM_IRQ_PA0, context);
}
#endif
#ifdef CONFIG_GPIOB_IRQ
static int up_gpiobinterrupt(int irq, void *context)
{
return up_gpiointerrupt(SAM3U_PIOB_BASE, SAM3U_IRQ_PB0, context);
return up_gpiointerrupt(SAM_PIOB_BASE, SAM_IRQ_PB0, context);
}
#endif
#ifdef CONFIG_GPIOC_IRQ
static int up_gpiocinterrupt(int irq, void *context)
{
return up_gpiointerrupt(SAM3U_PIOC_BASE, SAM3U_IRQ_PC0, context);
return up_gpiointerrupt(SAM_PIOC_BASE, SAM_IRQ_PC0, context);
}
#endif
@@ -217,18 +217,18 @@ void sam3u_gpioirqinitialize(void)
#ifdef CONFIG_GPIOA_IRQ
/* Enable GPIOA clocking */
pcer |= (1 << SAM3U_PID_PIOA);
putreg32(pcer, SAM3U_PMC_PCER);
pcer |= (1 << SAM_PID_PIOA);
putreg32(pcer, SAM_PMC_PCER);
/* Clear and disable all GPIOA interrupts */
(void)getreg32(SAM3U_PIOA_ISR);
putreg32(0xffffffff, SAM3U_PIOA_IDR);
(void)getreg32(SAM_PIOA_ISR);
putreg32(0xffffffff, SAM_PIOA_IDR);
/* Attach and enable the GPIOA IRQ */
(void)irq_attach(SAM3U_IRQ_PIOA, up_gpioainterrupt);
up_enable_irq(SAM3U_IRQ_PIOA);
(void)irq_attach(SAM_IRQ_PIOA, up_gpioainterrupt);
up_enable_irq(SAM_IRQ_PIOA);
#endif
/* Configure GPIOB interrupts */
@@ -236,18 +236,18 @@ void sam3u_gpioirqinitialize(void)
#ifdef CONFIG_GPIOB_IRQ
/* Enable GPIOB clocking */
pcer |= (1 << SAM3U_PID_PIOB);
putreg32(pcer, SAM3U_PMC_PCER);
pcer |= (1 << SAM_PID_PIOB);
putreg32(pcer, SAM_PMC_PCER);
/* Clear and disable all GPIOB interrupts */
(void)getreg32(SAM3U_PIOB_ISR);
putreg32(0xffffffff, SAM3U_PIOB_IDR);
(void)getreg32(SAM_PIOB_ISR);
putreg32(0xffffffff, SAM_PIOB_IDR);
/* Attach and enable the GPIOB IRQ */
(void)irq_attach(SAM3U_IRQ_PIOB, up_gpiobinterrupt);
up_enable_irq(SAM3U_IRQ_PIOB);
(void)irq_attach(SAM_IRQ_PIOB, up_gpiobinterrupt);
up_enable_irq(SAM_IRQ_PIOB);
#endif
/* Configure GPIOC interrupts */
@@ -255,18 +255,18 @@ void sam3u_gpioirqinitialize(void)
#ifdef CONFIG_GPIOC_IRQ
/* Enable GPIOC clocking */
pcer |= (1 << SAM3U_PID_PIOC);
putreg32(pcer, SAM3U_PMC_PCER);
pcer |= (1 << SAM_PID_PIOC);
putreg32(pcer, SAM_PMC_PCER);
/* Clear and disable all GPIOC interrupts */
(void)getreg32(SAM3U_PIOC_ISR);
putreg32(0xffffffff, SAM3U_PIOC_IDR);
(void)getreg32(SAM_PIOC_ISR);
putreg32(0xffffffff, SAM_PIOC_IDR);
/* Attach and enable the GPIOC IRQ */
(void)irq_attach(SAM3U_IRQ_PIOC, up_gpioainterrupt);
up_enable_irq(SAM3U_IRQ_PIOC);
(void)irq_attach(SAM_IRQ_PIOC, up_gpioainterrupt);
up_enable_irq(SAM_IRQ_PIOC);
#endif
}
@@ -282,42 +282,42 @@ void sam3u_gpioirq(uint16_t pinset)
{
uint32_t base = sam3u_gpiobase(pinset);
int pin = sam3u_gpiopin(pinset);
/* Are any additional interrupt modes selected? */
if ((pinset & GPIO_INT_MASK) != 0)
{
/* Yes.. Enable additional interrupt mode */
putreg32(pin, base+SAM3U_PIO_AIMER_OFFSET);
putreg32(pin, base + SAM_PIO_AIMER_OFFSET);
/* Level or edge detected interrupt? */
if ((pinset & GPIO_INT_LEVEL) != 0)
{
putreg32(pin, base+SAM3U_PIO_LSR_OFFSET); /* Level */
putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */
}
else
{
putreg32(pin, base+SAM3U_PIO_ESR_OFFSET); /* Edge */
putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */
}
/* High level/rising edge or low level /falling edge? */
if ((pinset & GPIO_INT_HIGHLEVEL) != 0)
{
putreg32(pin, base+SAM3U_PIO_REHLSR_OFFSET); /* High level/Rising edge */
putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */
}
else
{
putreg32(pin, base+SAM3U_PIO_FELLSR_OFFSET); /* Low level/Falling edge */
putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */
}
}
else
{
/* No.. Disable additional interrupt mode */
putreg32(pin, base+SAM3U_PIO_AIMDR_OFFSET);
putreg32(pin, base + SAM_PIO_AIMDR_OFFSET);
}
}
@@ -338,8 +338,8 @@ void sam3u_gpioirqenable(int irq)
{
/* Clear (all) pending interrupts and enable this pin interrupt */
(void)getreg32(base+SAM3U_PIO_ISR_OFFSET);
putreg32((1 << pin), base+SAM3U_PIO_IER_OFFSET);
(void)getreg32(base + SAM_PIO_ISR_OFFSET);
putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
}
}
@@ -360,8 +360,8 @@ void sam3u_gpioirqdisable(int irq)
{
/* Disable this pin interrupt */
putreg32((1 << pin), base+SAM3U_PIO_IDR_OFFSET);
putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET);
}
}
#endif /* CONFIG_GPIO_IRQ */
#endif /* CONFIG_GPIO_IRQ */
arch/arm/src/sam3u/sam3u_hsmci.c
+126 -126
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/sam3u/sam3u_hsmci.h
-297
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@@ -1,297 +0,0 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_hsmci.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* HSMCI register offsets ***************************************************************/
#define SAM3U_HSMCI_CR_OFFSET 0x0000 /* Control Register */
#define SAM3U_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
#define SAM3U_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */
#define SAM3U_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */
#define SAM3U_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */
#define SAM3U_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */
#define SAM3U_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */
#define SAM3U_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */
#define SAM3U_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */
#define SAM3U_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */
#define SAM3U_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */
#define SAM3U_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */
#define SAM3U_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */
#define SAM3U_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */
/* 0x0038-0x003c: Reserved */
#define SAM3U_HSMCI_SR_OFFSET 0x0040 /* Status Register */
#define SAM3U_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */
#define SAM3U_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */
#define SAM3U_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */
#define SAM3U_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */
#define SAM3U_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */
/* 0x0058-0x00e0: Reserved */
#define SAM3U_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */
#define SAM3U_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
/* 0x00ec-0x00fc: Reserved */
/* 0x0100-0x0124: Reserved */
#define SAM3U_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */
/* HSMCI register adresses **************************************************************/
#define SAM3U_HSMCI_CR (SAM3U_MCI_BASE+SAM3U_HSMCI_CR_OFFSET)
#define SAM3U_HSMCI_MR (SAM3U_MCI_BASE+SAM3U_HSMCI_MR_OFFSET)
#define SAM3U_HSMCI_DTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_DTOR_OFFSET)
#define SAM3U_HSMCI_SDCR (SAM3U_MCI_BASE+SAM3U_HSMCI_SDCR_OFFSET)
#define SAM3U_HSMCI_ARGR (SAM3U_MCI_BASE+SAM3U_HSMCI_ARGR_OFFSET)
#define SAM3U_HSMCI_CMDR (SAM3U_MCI_BASE+SAM3U_HSMCI_CMDR_OFFSET)
#define SAM3U_HSMCI_BLKR (SAM3U_MCI_BASE+SAM3U_HSMCI_BLKR_OFFSET)
#define SAM3U_HSMCI_CSTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_CSTOR_OFFSET)
#define SAM3U_HSMCI_RSPR0 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR0_OFFSET)
#define SAM3U_HSMCI_RSPR1 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR1_OFFSET)
#define SAM3U_HSMCI_RSPR2 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR2_OFFSET)
#define SAM3U_HSMCI_RSPR3 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR3_OFFSET)
#define SAM3U_HSMCI_RDR (SAM3U_MCI_BASE+SAM3U_HSMCI_RDR_OFFSET)
#define SAM3U_HSMCI_TDR (SAM3U_MCI_BASE+SAM3U_HSMCI_TDR_OFFSET)
#define SAM3U_HSMCI_SR (SAM3U_MCI_BASE+SAM3U_HSMCI_SR_OFFSET)
#define SAM3U_HSMCI_IER (SAM3U_MCI_BASE+SAM3U_HSMCI_IER_OFFSET)
#define SAM3U_HSMCI_IDR (SAM3U_MCI_BASE+SAM3U_HSMCI_IDR_OFFSET)
#define SAM3U_HSMCI_IMR (SAM3U_MCI_BASE+SAM3U_HSMCI_IMR_OFFSET)
#define SAM3U_HSMCI_DMA (SAM3U_MCI_BASE+SAM3U_HSMCI_DMA_OFFSET)
#define SAM3U_HSMCI_CFG (SAM3U_MCI_BASE+SAM3U_HSMCI_CFG_OFFSET)
#define SAM3U_HSMCI_WPMR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPMR_OFFSET)
#define SAM3U_HSMCI_WPSR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPSR_OFFSET)
#define SAM3U_HSMCI_FIFO (SAM3U_MCI_BASE+SAM3U_HSMCI_FIFO_OFFSET)
/* HSMCI register bit definitions *******************************************************/
/* HSMCI Control Register */
#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */
#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */
#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */
#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */
#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
/* HSMCI Mode Register */
#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */
#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT)
/* HSMCI Data Timeout Register */
#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */
#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT)
# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT)
#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */
#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT)
# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT)
/* HSMCI SDCard/SDIO Register */
#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */
#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT)
# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT)
#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */
#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT)
# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT)
/* HSMCI Command Register */
#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */
#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT)
#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */
#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT)
# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */
# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */
# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */
# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */
# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT)
# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */
#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT)
# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */
# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */
# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */
/* HSMCI Block Register */
#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
/* HSMCI Completion Signal Timeout Register */
#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT)
# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
* Register, and HSMCI Interrupt Mask Register common bit-field definitions
*/
#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */
#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */
#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */
#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */
#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */
#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */
#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */
#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */
#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */
#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */
#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */
#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */
#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */
#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */
#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */
#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */
#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */
#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */
#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */
#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */
/* HSMCI DMA Configuration Register */
#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */
#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT)
#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */
#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */
#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */
/* HSMCI Configuration Register */
#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */
#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */
#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */
#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */
/* HSMCI Write Protect Mode Register */
#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */
#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT)
/* HSMCI Write Protect Status Register */
#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT)
#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H */
arch/arm/src/sam3u/sam3u_internal.h
+11 -11
View File
@@ -114,7 +114,7 @@
*/
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
#define GPIO_OUTPUT_CLEAR (0)
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:
* .... .... .PP. ....
@@ -423,7 +423,7 @@ extern "C"
* Name: sam3u_clockconfig
*
* Description:
* Called to initialize the SAM3U. This does whatever setup is needed to put the
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
* SoC in a usable state. This includes the initialization of clocking using the
* settings in board.h. (After power-on reset, the sam3u is initiallyrunning on
* a 4MHz internal RC clock). This function also performs other low-level chip
@@ -465,7 +465,7 @@ void sam3u_userspace(void);
* Name: sam3u_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted SAM3U
* Configure the MPU to permit user-space access to only unrestricted SAM3/4
* resources.
*
****************************************************************************/
@@ -733,7 +733,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno);
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* cardinslot - true is a card has been detected in the slot; false if a
* cardinslot - true is a card has been detected in the slot; false if a
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
@@ -771,12 +771,12 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
* include:
*
* o sam3u_spicsnumbe and sam3u_spiselect which are helper functions to
* manage the board-specific aspects of the unique SAM3U chip select
* manage the board-specific aspects of the unique SAM3/4 chip select
* architecture.
* o sam3u_spistatus and sam3u_spicmddata: Implementations of the status
* and cmddata methods of the SPI interface defined by struct spi_ops_
* (see include/nuttx/spi.h). All other methods including
* up_spiinitialize()) are provided by common SAM3U logic.
* up_spiinitialize()) are provided by common SAM3/4 logic.
*
* To use this common SPI logic on your board:
*
@@ -793,13 +793,13 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
* 3. Add a call to up_spiinitialize() in your low level application
* initialization logic
* 4. The handle returned by up_spiinitialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_SAM3U_SPI
#ifdef CONFIG_SAM34_SPI
struct spi_dev_s;
enum spi_dev_e;
@@ -807,10 +807,10 @@ enum spi_dev_e;
* Name: sam3u_spicsnumber
*
* Description:
* The SAM3U has 4 CS registers for controlling device features. This
* The SAM3/4 has 4 CS registers for controlling device features. This
* function must be provided by board-specific code. Given a logical device
* ID, this function returns a number from 0 to 3 that identifies one of
* these SAM3U CS resources.
* these SAM3/4 CS resources.
*
* If CONFIG_SPI_OWNBUS is not defined and the GPIO is controlled by
* sam3u_spiselect, then the same CS register may be used to control
@@ -900,7 +900,7 @@ uint8_t sam3u_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
int sam3u_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
#endif /* CONFIG_SAM3U_SPI */
#endif /* CONFIG_SAM34_SPI */
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam3u/sam3u_irq.c
+30 -30
View File
@@ -62,7 +62,7 @@
* bringup
*/
#undef SAM3U_IRQ_DEBUG
#undef SAM_IRQ_DEBUG
/* Get a 32-bit version of the default priority */
@@ -94,7 +94,7 @@ volatile uint32_t *current_regs;
*
****************************************************************************/
#if defined(SAM3U_IRQ_DEBUG) && defined (CONFIG_DEBUG)
#if defined(SAM_IRQ_DEBUG) && defined (CONFIG_DEBUG)
static void sam3u_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
@@ -112,10 +112,10 @@ static void sam3u_dumpnvic(const char *msg, int irq)
slldbg(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
slldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
slldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
slldbg(" %08x %08x %08x %08x\n",
slldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqrestore(flags);
@@ -219,16 +219,16 @@ static inline void sam3u_prioritize_syscall(int priority)
static int sam3u_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{
DEBUGASSERT(irq >= SAM3U_IRQ_NMI && irq < NR_IRQS);
DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= SAM3U_IRQ_EXTINT)
if (irq >= SAM_IRQ_EXTINT)
{
if (irq < SAM3U_IRQ_NIRQS)
if (irq < SAM_IRQ_NIRQS)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << (irq - SAM3U_IRQ_EXTINT);
*bit = 1 << (irq - SAM_IRQ_EXTINT);
}
else
{
@@ -241,19 +241,19 @@ static int sam3u_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
else
{
*regaddr = NVIC_SYSHCON;
if (irq == SAM3U_IRQ_MEMFAULT)
if (irq == SAM_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == SAM3U_IRQ_BUSFAULT)
else if (irq == SAM_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == SAM3U_IRQ_USAGEFAULT)
else if (irq == SAM_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == SAM3U_IRQ_SYSTICK)
else if (irq == SAM_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
@@ -318,13 +318,13 @@ void up_irqinitialize(void)
* under certain conditions.
*/
irq_attach(SAM3U_IRQ_SVCALL, up_svcall);
irq_attach(SAM3U_IRQ_HARDFAULT, up_hardfault);
irq_attach(SAM_IRQ_SVCALL, up_svcall);
irq_attach(SAM_IRQ_HARDFAULT, up_hardfault);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(SAM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
sam3u_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
@@ -335,32 +335,32 @@ void up_irqinitialize(void)
*/
#ifdef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM3U_IRQ_MEMFAULT);
irq_attach(SAM_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
irq_attach(SAM_IRQ_NMI, sam3u_nmi);
#ifndef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
irq_attach(SAM_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);
irq_attach(SAM3U_IRQ_USAGEFAULT, sam3u_usagefault);
irq_attach(SAM3U_IRQ_PENDSV, sam3u_pendsv);
irq_attach(SAM3U_IRQ_DBGMONITOR, sam3u_dbgmonitor);
irq_attach(SAM3U_IRQ_RESERVED, sam3u_reserved);
irq_attach(SAM_IRQ_BUSFAULT, sam3u_busfault);
irq_attach(SAM_IRQ_USAGEFAULT, sam3u_usagefault);
irq_attach(SAM_IRQ_PENDSV, sam3u_pendsv);
irq_attach(SAM_IRQ_DBGMONITOR, sam3u_dbgmonitor);
irq_attach(SAM_IRQ_RESERVED, sam3u_reserved);
#endif
sam3u_dumpnvic("initial", SAM3U_IRQ_NIRQS);
sam3u_dumpnvic("initial", SAM_IRQ_NIRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*/
#ifdef CONFIG_GPIO_IRQ
sam3u_gpioirqinitialize();
#endif
@@ -469,15 +469,15 @@ int up_prioritize_irq(int irq, int priority)
int shift;
#ifdef CONFIG_ARMV7M_USEBASEPRI
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS &&
DEBUGASSERT(irq >= SAM_IRQ_MEMFAULT && irq < SAM_IRQ_NIRQS &&
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
priority <= NVIC_SYSH_PRIORITY_MIN);
#else
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS &&
DEBUGASSERT(irq >= SAM_IRQ_MEMFAULT && irq < SAM_IRQ_NIRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
#endif
if (irq < SAM3U_IRQ_EXTINT)
if (irq < SAM_IRQ_EXTINT)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
@@ -490,7 +490,7 @@ int up_prioritize_irq(int irq, int priority)
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= SAM3U_IRQ_EXTINT;
irq -= SAM_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
arch/arm/src/sam3u/sam3u_lowputc.c
+74 -73
View File
@@ -1,7 +1,7 @@
/**************************************************************************
* arch/arm/src/sam3u/sam3u_lowputc.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -48,8 +48,8 @@
#include "up_arch.h"
#include "sam3u_internal.h"
#include "sam3u_pmc.h"
#include "sam3u_uart.h"
#include "chip/sam_pmc.h"
#include "chip/sam_uart.h"
/**************************************************************************
* Private Definitions
@@ -62,45 +62,45 @@
*/
#ifndef CONFIG_USART0_ISUART
# undef CONFIG_SAM3U_USART0
# undef CONFIG_SAM34_USART0
#endif
#ifndef CONFIG_USART1_ISUART
# undef CONFIG_SAM3U_USART1
# undef CONFIG_SAM34_USART1
#endif
#ifndef CONFIG_USART2_ISUART
# undef CONFIG_SAM3U_USART2
# undef CONFIG_SAM34_USART2
#endif
#ifndef CONFIG_USART3_ISUART
# undef CONFIG_SAM3U_USART3
# undef CONFIG_SAM34_USART3
#endif
/* Is there a serial console? It could be on the UART, or USARTn */
#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_UART)
#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART)
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART0)
#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0)
# undef CONFIG_USART_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART1)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1)
# undef CONFIG_USART_SERIAL_CONSOLE
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART2)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2)
# undef CONFIG_USART_SERIAL_CONSOLE
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART3)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3)
# undef CONFIG_USART_SERIAL_CONSOLE
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
@@ -118,70 +118,71 @@
/* Select USART parameters for the selected console */
#if defined(CONFIG_UART_SERIAL_CONSOLE)
# define SAM3U_CONSOLE_BASE SAM3U_UART_BASE
# define SAM3U_CONSOLE_BAUD CONFIG_UART_BAUD
# define SAM3U_CONSOLE_BITS CONFIG_UART_BITS
# define SAM3U_CONSOLE_PARITY CONFIG_UART_PARITY
# define SAM3U_CONSOLE_2STOP CONFIG_UART_2STOP
# define SAM_CONSOLE_BASE SAM_UART_BASE
# define SAM_CONSOLE_BAUD CONFIG_UART_BAUD
# define SAM_CONSOLE_BITS CONFIG_UART_BITS
# define SAM_CONSOLE_PARITY CONFIG_UART_PARITY
# define SAM_CONSOLE_2STOP CONFIG_UART_2STOP
#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
# define SAM3U_CONSOLE_BASE SAM3U_USART0_BASE
# define SAM3U_CONSOLE_BAUD CONFIG_USART0_BAUD
# define SAM3U_CONSOLE_BITS CONFIG_USART0_BITS
# define SAM3U_CONSOLE_PARITY CONFIG_USART0_PARITY
# define SAM3U_CONSOLE_2STOP CONFIG_USART0_2STOP
# define SAM_CONSOLE_BASE SAM_USART0_BASE
# define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART0_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART0_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART0_2STOP
#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
# define SAM3U_CONSOLE_BASE SAM3U_USART1_BASE
# define SAM3U_CONSOLE_BAUD CONFIG_USART1_BAUD
# define SAM3U_CONSOLE_BITS CONFIG_USART1_BITS
# define SAM3U_CONSOLE_PARITY CONFIG_USART1_PARITY
# define SAM3U_CONSOLE_2STOP CONFIG_USART1_2STOP
# define SAM_CONSOLE_BASE SAM_USART1_BASE
# define SAM_CONSOLE_BAUD CONFIG_USART1_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART1_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART1_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART1_2STOP
#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define SAM3U_CONSOLE_BASE SAM3U_USART2_BASE
# define SAM3U_CONSOLE_BAUD CONFIG_USART2_BAUD
# define SAM3U_CONSOLE_BITS CONFIG_USART2_BITS
# define SAM3U_CONSOLE_PARITY CONFIG_USART2_PARITY
# define SAM3U_CONSOLE_2STOP CONFIG_USART2_2STOP
# define SAM_CONSOLE_BASE SAM_USART2_BASE
# define SAM_CONSOLE_BAUD CONFIG_USART2_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART2_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART2_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART2_2STOP
#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define SAM3U_CONSOLE_BASE SAM3U_USART3_BASE
# define SAM3U_CONSOLE_BAUD CONFIG_USART3_BAUD
# define SAM3U_CONSOLE_BITS CONFIG_USART3_BITS
# define SAM3U_CONSOLE_PARITY CONFIG_USART3_PARITY
# define SAM3U_CONSOLE_2STOP CONFIG_USART3_2STOP
# define SAM_CONSOLE_BASE SAM_USART3_BASE
# define SAM_CONSOLE_BAUD CONFIG_USART3_BAUD
# define SAM_CONSOLE_BITS CONFIG_USART3_BITS
# define SAM_CONSOLE_PARITY CONFIG_USART3_PARITY
# define SAM_CONSOLE_2STOP CONFIG_USART3_2STOP
#else
# error "No CONFIG_U[S]ARTn_SERIAL_CONSOLE Setting"
#endif
/* Select the settings for the mode register */
#if SAM3U_CONSOLE_BITS == 5
#if SAM_CONSOLE_BITS == 5
# define MR_CHRL_VALUE USART_MR_CHRL_5BITS /* 5 bits */
#elif SAM3U_CONSOLE_BITS == 6
#elif SAM_CONSOLE_BITS == 6
# define MR_CHRL_VALUE USART_MR_CHRL_6BITS /* 6 bits */
#elif SAM3U_CONSOLE_BITS == 7
#elif SAM_CONSOLE_BITS == 7
# define MR_CHRL_VALUE USART_MR_CHRL_7BITS /* 7 bits */
#elif SAM3U_CONSOLE_BITS == 8
#elif SAM_CONSOLE_BITS == 8
# define MR_CHRL_VALUE USART_MR_CHRL_8BITS /* 8 bits */
#elif SAM3U_CONSOLE_BITS == 9 && !defined(CONFIG_UART_SERIAL_CONSOLE)
#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART_SERIAL_CONSOLE)
# define MR_CHRL_VALUE USART_MR_MODE9
#else
# error "Invlaid number of bits"
#endif
#if SAM3U_CONSOLE_PARITY == 1
#if SAM_CONSOLE_PARITY == 1
# define MR_PAR_VALUE UART_MR_PAR_ODD
#elif SAM3U_CONSOLE_PARITY == 2
#elif SAM_CONSOLE_PARITY == 2
# define MR_PAR_VALUE UART_MR_PAR_EVEN
#else
# define MR_PAR_VALUE UART_MR_PAR_NONE
#endif
#if SAM3U_CONSOLE_2STOP != 0
#if SAM_CONSOLE_2STOP != 0
# define MR_NBSTOP_VALUE USART_MR_NBSTOP_2
#else
# define MR_NBSTOP_VALUE USART_MR_NBSTOP_1
#endif
#define MR_VALUE (USART_MR_MODE_NORMAL|USART_MR_USCLKS_MCK|MR_CHRL_VALUE|MR_PAR_VALUE|MR_NBSTOP_VALUE)
#define MR_VALUE (USART_MR_MODE_NORMAL | USART_MR_USCLKS_MCK | \
MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE)
/**************************************************************************
* Private Types
@@ -219,11 +220,11 @@ void up_lowputc(char ch)
{
/* Wait for the transmitter to be available */
while ((getreg32(SAM3U_CONSOLE_BASE+SAM3U_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) == 0);
/* Send the character */
putreg32((uint32_t)ch, SAM3U_CONSOLE_BASE+SAM3U_UART_THR_OFFSET);
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
}
/**************************************************************************
@@ -243,48 +244,48 @@ void sam3u_lowsetup(void)
/* Enable clocking for all selected UART/USARTs */
regval = 0;
#ifdef CONFIG_SAM3U_UART
regval |= (1 << SAM3U_PID_UART);
#ifdef CONFIG_SAM34_UART
regval |= (1 << SAM_PID_UART);
#endif
#ifdef CONFIG_SAM3U_USART0
regval |= (1 << SAM3U_PID_USART0);
#ifdef CONFIG_SAM34_USART0
regval |= (1 << SAM_PID_USART0);
#endif
#ifdef CONFIG_SAM3U_USART1
regval |= (1 << SAM3U_PID_USART1);
#ifdef CONFIG_SAM34_USART1
regval |= (1 << SAM_PID_USART1);
#endif
#ifdef CONFIG_SAM3U_USART2
regval |= (1 << SAM3U_PID_USART2);
#ifdef CONFIG_SAM34_USART2
regval |= (1 << SAM_PID_USART2);
#endif
#ifdef CONFIG_SAM3U_USART3
regval |= (1 << SAM3U_PID_USART3);
#ifdef CONFIG_SAM34_USART3
regval |= (1 << SAM_PID_USART3);
#endif
putreg32(regval, SAM3U_PMC_PCER);
putreg32(regval, SAM_PMC_PCER);
/* Configure UART pins for all selected UART/USARTs */
#ifdef CONFIG_SAM3U_UART
#ifdef CONFIG_SAM34_UART
(void)sam3u_configgpio(GPIO_UART_RXD);
(void)sam3u_configgpio(GPIO_UART_TXD);
#endif
#ifdef CONFIG_SAM3U_USART0
#ifdef CONFIG_SAM34_USART0
(void)sam3u_configgpio(GPIO_USART0_RXD);
(void)sam3u_configgpio(GPIO_USART0_TXD);
(void)sam3u_configgpio(GPIO_USART0_CTS);
(void)sam3u_configgpio(GPIO_USART0_RTS);
#endif
#ifdef CONFIG_SAM3U_USART1
#ifdef CONFIG_SAM34_USART1
(void)sam3u_configgpio(GPIO_USART1_RXD);
(void)sam3u_configgpio(GPIO_USART1_TXD);
(void)sam3u_configgpio(GPIO_USART1_CTS);
(void)sam3u_configgpio(GPIO_USART1_RTS);
#endif
#ifdef CONFIG_SAM3U_USART2
#ifdef CONFIG_SAM34_USART2
(void)sam3u_configgpio(GPIO_USART2_RXD);
(void)sam3u_configgpio(GPIO_USART2_TXD);
(void)sam3u_configgpio(GPIO_USART2_CTS);
(void)sam3u_configgpio(GPIO_USART2_RTS);
#endif
#ifdef CONFIG_SAM3U_USART3
#ifdef CONFIG_SAM34_USART3
(void)sam3u_configgpio(GPIO_USART3_RXD);
(void)sam3u_configgpio(GPIO_USART3_TXD);
(void)sam3u_configgpio(GPIO_USART3_CTS);
@@ -307,26 +308,26 @@ void sam3u_lowsetup(void)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Reset and disable receiver and transmitter */
putreg32((UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS),
SAM3U_CONSOLE_BASE+SAM3U_UART_CR_OFFSET);
putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS),
SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
/* Disable all interrupts */
putreg32(0xffffffff, SAM3U_CONSOLE_BASE+SAM3U_UART_IDR_OFFSET);
putreg32(0xffffffff, SAM_CONSOLE_BASE + SAM_UART_IDR_OFFSET);
/* Set up the mode register */
putreg32(MR_VALUE, SAM3U_CONSOLE_BASE+SAM3U_UART_MR_OFFSET);
putreg32(MR_VALUE, SAM_CONSOLE_BASE + SAM_UART_MR_OFFSET);
/* Configure the console baud */
putreg32(((SAM3U_MCK_FREQUENCY + (SAM3U_CONSOLE_BAUD << 3))/(SAM3U_CONSOLE_BAUD << 4)),
SAM3U_CONSOLE_BASE+SAM3U_UART_BRGR_OFFSET);
putreg32(((SAM_MCK_FREQUENCY + (SAM_CONSOLE_BAUD << 3))/(SAM_CONSOLE_BAUD << 4)),
SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET);
/* Enable receiver & transmitter */
putreg32((UART_CR_RXEN|UART_CR_TXEN),
SAM3U_CONSOLE_BASE+SAM3U_UART_CR_OFFSET);
putreg32((UART_CR_RXEN | UART_CR_TXEN),
SAM_CONSOLE_BASE + SAM_UART_CR_OFFSET);
#endif
}
arch/arm/src/sam3u/sam3u_matrix.h
-214
View File
@@ -1,214 +0,0 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_matric.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* MATRIX register offsets **************************************************************/
#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2)
#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */
#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
/* 0x0014-0x003c: Reserved */
#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
/* 0x0068-0x007c: Reserved */
#define SAM3U_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3))
#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
/* 0x0084: Reserved */
#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
/* 0x008c: Reserved */
#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
/* 0x0094: Reserved */
#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
/* 0x009c: Reserved */
#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
/* 0x00a4: Reserved */
#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
/* 0x00ac: Reserved */
#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
/* 0x00b4: Reserved */
#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
/* 0x00bc: Reserved */
#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
/* 0x00c4: Reserved */
#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
/* 0x00cc-0x00fc: Reserved */
#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
/* 0x0104-0x010c: Reserved */
#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
/* 0x0110 - 0x01fc: Reserved */
/* MATRIX register adresses *************************************************************/
#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n))
#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET)
#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET)
#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET)
#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET)
#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET)
#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))
#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET)
#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET)
#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET)
#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET)
#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET)
#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET)
#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET)
#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET)
#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET)
#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET)
#define SAM3U_MATRIX_PRAS(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS_OFFSET(n))
#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET)
#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET)
#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET)
#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET)
#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET)
#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET)
#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET)
#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET)
#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET)
#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET)
#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET)
#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET)
#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET)
/* MATRIX register bit definitions ******************************************************/
#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */
#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */
# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */
# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */
#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2)
#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */
#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
#define MATRIX_MRCR_RCB(x) (1 << (x))
#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */
#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */
#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */
#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */
#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */
#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */
#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT)
#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */
#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H */
arch/arm/src/sam3u/sam3u_memorymap.h
-145
View File
@@ -1,145 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam3u/sam3u_memorymap.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H
/************************************************************************************************
* Included Files
************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
#define SAM3U_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
# define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */
# define SAM3U_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */
# define SAM3U_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */
# define SAM3U_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */
/* 0x00200000-0x1fffffff: Reserved */
#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */
# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */
# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */
# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */
/* 0x20200000-0x2fffffff: Undefined */
# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
/* 0x24000000-0x3fffffff: Undefined */
#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
# define SAM3U_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */
# define SAM3U_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
/* 0x4000c000-0x4007ffff: Reserved */
# define SAM3U_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */
# define SAM3U_TCN_BASE(n) (0x40080000+((n)<<6))
# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */
# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */
# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */
# define SAM3U_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */
# define SAM3U_TWIN_BASE(n) (0x40084000+((n)<<14))
# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */
# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */
# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */
# define SAM3U_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */
# define SAM3U_USARTN_BASE(n) (0x40090000+((n)<<14))
# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */
# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */
# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */
# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */
/* 0x400a0000-0x400a3fff: Reserved */
# define SAM3U_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */
# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */
# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */
# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */
/* 0x400b4000-0x400dffff: Reserved */
# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */
/* 0x400e2600-0x400fffff: Reserved */
/* 0x40100000-0x41ffffff: Reserved */
# define SAM3U_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */
/* 0x44000000-0x5fffffff: Reserved */
#define SAM3U_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */
# define SAM3U_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
# define SAM3U_EXTCSN_BASE(n) (0x60000000*((n)<<24))
# define SAM3U_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */
# define SAM3U_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */
# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x67ffffff: Reserved */
# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */
/* 0x69000000-0x9fffffff: Reserved */
/* 0xa0000000-0xdfffffff: Reserved */
#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
#define SAM3U_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */
#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */
#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */
#define SAM3U_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/
# define SAM3U_EEFCN_BASE(n) (0x400e0800+((n)<<9))
# define SAM3U_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
# define SAM3U_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
#define SAM3U_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */
# define SAM3U_PION_BASE(n) (0x400e0c00+((n)<<9))
# define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
# define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
# define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
#define SAM3U_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */
#define SAM3U_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */
#define SAM3U_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */
#define SAM3U_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */
#define SAM3U_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */
#define SAM3U_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */
/* 0x490e1400-0x4007ffff: Reserved */
/************************************************************************************************
* Public Types
************************************************************************************************/
/************************************************************************************************
* Public Data
************************************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */
arch/arm/src/sam3u/sam3u_mpuinit.c
+1 -1
View File
@@ -75,7 +75,7 @@
* Name: sam3u_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* Configure the MPU to permit user-space access to only restricted SAM3/4
* resources.
*
****************************************************************************/
arch/arm/src/sam3u/sam3u_pio.c
+45 -45
View File
@@ -52,7 +52,7 @@
#include "chip.h"
#include "sam3u_internal.h"
#include "sam3u_pio.h"
#include "chip/sam_pio.h"
/****************************************************************************
* Definitions
@@ -84,7 +84,7 @@ static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
static inline uintptr_t sam3u_gpiobase(uint16_t cfgset)
{
int port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
return SAM3U_PION_BASE(port);
return SAM_PION_BASE(port);
}
/****************************************************************************
@@ -113,34 +113,34 @@ static inline int sam3u_configinput(uintptr_t base, uint32_t pin,
{
/* Disable interrupts on the pin */
putreg32(pin, base+SAM3U_PIO_IDR_OFFSET);
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
putreg32(pin, base+SAM3U_PIO_PUER_OFFSET);
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
/* Check if filtering should be enabled */
if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
{
putreg32(pin, base+SAM3U_PIO_IFER_OFFSET);
putreg32(pin, base + SAM_PIO_IFER_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_IFDR_OFFSET);
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
}
/* Configure the pin as an input and enable the GPIO function */
putreg32(pin, base+SAM3U_PIO_ODR_OFFSET);
putreg32(pin, base+SAM3U_PIO_PER_OFFSET);
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
* registers. This would probably best be done with another, new
@@ -163,45 +163,45 @@ static inline int sam3u_configoutput(uintptr_t base, uint32_t pin,
{
/* Disable interrupts on the pin */
putreg32(pin, base+SAM3U_PIO_IDR_OFFSET);
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
putreg32(pin, base+SAM3U_PIO_PUER_OFFSET);
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
/* Enable the open drain driver if requrested */
if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
{
putreg32(pin, base+SAM3U_PIO_MDER_OFFSET);
putreg32(pin, base + SAM_PIO_MDER_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_MDDR_OFFSET);
putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
}
/* Set default value */
if ((cfgset & GPIO_OUTPUT_SET) != 0)
{
putreg32(pin, base+SAM3U_PIO_SODR_OFFSET);
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_CODR_OFFSET);
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
/* Configure the pin as an input and enable the GPIO function */
putreg32(pin, base+SAM3U_PIO_OER_OFFSET);
putreg32(pin, base+SAM3U_PIO_PER_OFFSET);
putreg32(pin, base + SAM_PIO_OER_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
return OK;
}
@@ -221,22 +221,22 @@ static inline int sam3u_configperiph(uintptr_t base, uint32_t pin,
/* Disable interrupts on the pin */
putreg32(pin, base+SAM3U_PIO_IDR_OFFSET);
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
/* Enable/disable the pull-up as requested */
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
putreg32(pin, base+SAM3U_PIO_PUER_OFFSET);
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
/* Configure pin, depending upon the peripheral A or B*/
regval = getreg32(base+SAM3U_PIO_ABSR_OFFSET);
regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
{
regval &= ~pin;
@@ -245,11 +245,11 @@ static inline int sam3u_configperiph(uintptr_t base, uint32_t pin,
{
regval |= pin;
}
putreg32(regval, base+SAM3U_PIO_ABSR_OFFSET);
putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
/* Disable PIO functionality */
putreg32(pin, base+SAM3U_PIO_PDR_OFFSET);
putreg32(pin, base + SAM_PIO_PDR_OFFSET);
return OK;
}
@@ -272,20 +272,20 @@ int sam3u_configgpio(uint16_t cfgset)
int ret;
switch (cfgset & GPIO_MODE_MASK)
{
{
case GPIO_INPUT:
ret = sam3u_configinput(base, pin, cfgset);
break;
case GPIO_OUTPUT:
ret = sam3u_configoutput(base, pin, cfgset);
break;
case GPIO_PERIPHA:
case GPIO_PERIPHB:
ret = sam3u_configperiph(base, pin, cfgset);
break;
default:
ret = -EINVAL;
break;
@@ -308,11 +308,11 @@ void sam3u_gpiowrite(uint16_t pinset, bool value)
if (value)
{
putreg32(pin, base+SAM3U_PIO_SODR_OFFSET);
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
}
else
{
putreg32(pin, base+SAM3U_PIO_CODR_OFFSET);
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
}
}
@@ -332,11 +332,11 @@ bool sam3u_gpioread(uint16_t pinset)
if ((pinset & GPIO_MODE_MASK) == GPIO_OUTPUT)
{
regval = getreg32(base+SAM3U_PIO_ODSR_OFFSET);
regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
}
else
{
regval = getreg32(base+SAM3U_PIO_PDSR_OFFSET);
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
}
return (regval & pin) != 0;
@@ -362,7 +362,7 @@ int sam3u_dumpgpio(uint32_t pinset, const char *msg)
pin = sam3u_gpiopin(pinset);
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
base = SAM3U_PION_BASE(port);
base = SAM_PION_BASE(port);
/* The following requires exclusive access to the GPIO registers */
@@ -370,23 +370,23 @@ int sam3u_dumpgpio(uint32_t pinset, const char *msg)
lldbg("PIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
lldbg(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
getreg32(base + SAM3U_PIO_PSR_OFFSET), getreg32(base + SAM3U_PIO_OSR_OFFSET),
getreg32(base + SAM3U_PIO_IFSR_OFFSET), getreg32(base + SAM3U_PIO_ODSR_OFFSET));
getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
getreg32(base + SAM3U_PIO_PDSR_OFFSET), getreg32(base + SAM3U_PIO_IMR_OFFSET),
getreg32(base + SAM3U_PIO_ISR_OFFSET), getreg32(base + SAM3U_PIO_MDSR_OFFSET));
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
lldbg(" PUSR: %08x ABSR: %08x SCIFSR: %08x DIFSR: %08x\n",
getreg32(base + SAM3U_PIO_PUSR_OFFSET), getreg32(base + SAM3U_PIO_ABSR_OFFSET),
getreg32(base + SAM3U_PIO_SCIFSR_OFFSET), getreg32(base + SAM3U_PIO_DIFSR_OFFSET));
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_ABSR_OFFSET),
getreg32(base + SAM_PIO_SCIFSR_OFFSET), getreg32(base + SAM_PIO_DIFSR_OFFSET));
lldbg(" IFDGSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
getreg32(base + SAM3U_PIO_IFDGSR_OFFSET), getreg32(base + SAM3U_PIO_SCDR_OFFSET),
getreg32(base + SAM3U_PIO_OWSR_OFFSET), getreg32(base + SAM3U_PIO_AIMMR_OFFSET));
getreg32(base + SAM_PIO_IFDGSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
getreg32(base + SAM3U_PIO_ESR_OFFSET), getreg32(base + SAM3U_PIO_LSR_OFFSET),
getreg32(base + SAM3U_PIO_ELSR_OFFSET), getreg32(base + SAM3U_PIO_FELLSR_OFFSET));
getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM3U_PIO_FRLHSR_OFFSET), getreg32(base + SAM3U_PIO_LOCKSR_OFFSET),
getreg32(base + SAM3U_PIO_WPMR_OFFSET), getreg32(base + SAM3U_PIO_WPSR_OFFSET));
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
irqrestore(flags);
return OK;
}
arch/arm/src/sam3u/sam3u_pio.h
-324
View File
@@ -1,324 +0,0 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_pio.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* PIO register offsets *****************************************************************/
#define SAM3U_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM3U_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
#define SAM3U_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */
/* 0x000c: Reserved */
#define SAM3U_PIO_OER_OFFSET 0x0010 /* Output Enable Register */
#define SAM3U_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */
#define SAM3U_PIO_OSR_OFFSET 0x0018 /* utput Status Register */
/* 0x001c: Reserved */
#define SAM3U_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */
#define SAM3U_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */
#define SAM3U_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */
/* 0x002c: Reserved */
#define SAM3U_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */
#define SAM3U_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */
#define SAM3U_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */
#define SAM3U_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */
#define SAM3U_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */
#define SAM3U_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */
#define SAM3U_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */
#define SAM3U_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */
#define SAM3U_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */
#define SAM3U_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */
#define SAM3U_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */
/* 0x005c: Reserved */
#define SAM3U_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */
#define SAM3U_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */
#define SAM3U_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */
/* 0x006c: Reserved */
#define SAM3U_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */
/* 0x0074-0x007c: Reserved */
#define SAM3U_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */
#define SAM3U_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */
#define SAM3U_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */
#define SAM3U_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */
/* 0x0090-0x009c: Reserved */
#define SAM3U_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */
#define SAM3U_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */
#define SAM3U_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */
/* 0x00ac: Reserved */
#define SAM3U_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */
#define SAM3U_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */
#define SAM3U_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */
/* 0x00bc: Reserved */
#define SAM3U_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */
#define SAM3U_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */
#define SAM3U_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */
/* 0x00cc: Reserved */
#define SAM3U_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */
#define SAM3U_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */
#define SAM3U_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */
/* 0x00dc: Reserved */
#define SAM3U_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */
#define SAM3U_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM3U_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* 0x00ec-0x00f8: Reserved */
/* 0x0100-0x0144: Reserved */
/* PIO register adresses ****************************************************************/
#define PIOA (0)
#define PIOB (1)
#define PIOC (2)
#define NPIO (3)
#define SAM3U_PIO_PER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PER_OFFSET)
#define SAM3U_PIO_PDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDR_OFFSET)
#define SAM3U_PIO_PSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PSR_OFFSET)
#define SAM3U_PIO_OER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OER_OFFSET)
#define SAM3U_PIO_ODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODR_OFFSET)
#define SAM3U_PIO_OSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OSR_OFFSET)
#define SAM3U_PIO_IFER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFER_OFFSET)
#define SAM3U_PIO_IFDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDR_OFFSET)
#define SAM3U_PIO_IFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFSR_OFFSET)
#define SAM3U_PIO_SODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SODR_OFFSET)
#define SAM3U_PIO_CODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_CODR_OFFSET)
#define SAM3U_PIO_ODSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODSR_OFFSET)
#define SAM3U_PIO_PDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDSR_OFFSET)
#define SAM3U_PIO_IER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IER_OFFSET)
#define SAM3U_PIO_IDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IDR_OFFSET)
#define SAM3U_PIO_IMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IMR_OFFSET)
#define SAM3U_PIO_ISR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ISR_OFFSET)
#define SAM3U_PIO_MDER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDER_OFFSET)
#define SAM3U_PIO_MDDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDDR_OFFSET)
#define SAM3U_PIO_MDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDSR_OFFSET)
#define SAM3U_PIO_PUDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUDR_OFFSET)
#define SAM3U_PIO_PUER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUER_OFFSET)
#define SAM3U_PIO_PUSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUSR_OFFSET)
#define SAM3U_PIO_ABSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ABSR_OFFSET)
#define SAM3U_PIO_SCIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCIFSR_OFFSET)
#define SAM3U_PIO_DIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_DIFSR_OFFSET)
#define SAM3U_PIO_IFDGSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDGSR_OFFSET)
#define SAM3U_PIO_SCDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCDR_OFFSET)
#define SAM3U_PIO_OWER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWER_OFFSET)
#define SAM3U_PIO_OWDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWDR_OFFSET)
#define SAM3U_PIO_OWSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWSR_OFFSET)
#define SAM3U_PIO_AIMER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMER_OFFSET)
#define SAM3U_PIO_AIMDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMDR_OFFSET)
#define SAM3U_PIO_AIMMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMMR_OFFSET)
#define SAM3U_PIO_ESR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ESR_OFFSET)
#define SAM3U_PIO_LSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LSR_OFFSET)
#define SAM3U_PIO_ELSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ELSR_OFFSET)
#define SAM3U_PIO_FELLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FELLSR_OFFSET)
#define SAM3U_PIO_REHLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_REHLSR_OFFSET)
#define SAM3U_PIO_FRLHSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FRLHSR_OFFSET)
#define SAM3U_PIO_LOCKSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LOCKSR_OFFSET)
#define SAM3U_PIO_WPMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPMR_OFFSET)
#define SAM3U_PIO_WPSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPSR_OFFSET)
#define SAM3U_PIOA_PER (SAM3U_PIOA_BASE+SAM3U_PIO_PER_OFFSET)
#define SAM3U_PIOA_PDR_ (SAM3U_PIOA_BASE+SAM3U_PIO_PDR_OFFSET)
#define SAM3U_PIOA_PSR (SAM3U_PIOA_BASE+SAM3U_PIO_PSR_OFFSET)
#define SAM3U_PIOA_OER (SAM3U_PIOA_BASE+SAM3U_PIO_OER_OFFSET)
#define SAM3U_PIOA_ODR (SAM3U_PIOA_BASE+SAM3U_PIO_ODR_OFFSET)
#define SAM3U_PIOA_OSR (SAM3U_PIOA_BASE+SAM3U_PIO_OSR_OFFSET)
#define SAM3U_PIOA_IFER (SAM3U_PIOA_BASE+SAM3U_PIO_IFER_OFFSET)
#define SAM3U_PIOA_IFDR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDR_OFFSET)
#define SAM3U_PIOA_IFSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFSR_OFFSET)
#define SAM3U_PIOA_SODR (SAM3U_PIOA_BASE+SAM3U_PIO_SODR_OFFSET)
#define SAM3U_PIOA_CODR (SAM3U_PIOA_BASE+SAM3U_PIO_CODR_OFFSET)
#define SAM3U_PIOA_ODSR (SAM3U_PIOA_BASE+SAM3U_PIO_ODSR_OFFSET)
#define SAM3U_PIOA_PDSR (SAM3U_PIOA_BASE+SAM3U_PIO_PDSR_OFFSET)
#define SAM3U_PIOA_IER (SAM3U_PIOA_BASE+SAM3U_PIO_IER_OFFSET)
#define SAM3U_PIOA_IDR (SAM3U_PIOA_BASE+SAM3U_PIO_IDR_OFFSET)
#define SAM3U_PIOA_IMR (SAM3U_PIOA_BASE+SAM3U_PIO_IMR_OFFSET)
#define SAM3U_PIOA_ISR (SAM3U_PIOA_BASE+SAM3U_PIO_ISR_OFFSET)
#define SAM3U_PIOA_MDER (SAM3U_PIOA_BASE+SAM3U_PIO_MDER_OFFSET)
#define SAM3U_PIOA_MDDR (SAM3U_PIOA_BASE+SAM3U_PIO_MDDR_OFFSET)
#define SAM3U_PIOA_MDSR (SAM3U_PIOA_BASE+SAM3U_PIO_MDSR_OFFSET)
#define SAM3U_PIOA_PUDR (SAM3U_PIOA_BASE+SAM3U_PIO_PUDR_OFFSET)
#define SAM3U_PIOA_PUER (SAM3U_PIOA_BASE+SAM3U_PIO_PUER_OFFSET)
#define SAM3U_PIOA_PUSR (SAM3U_PIOA_BASE+SAM3U_PIO_PUSR_OFFSET)
#define SAM3U_PIOA_ABSR (SAM3U_PIOA_BASE+SAM3U_PIO_ABSR_OFFSET)
#define SAM3U_PIOA_SCIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_SCIFSR_OFFSET)
#define SAM3U_PIOA_DIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_DIFSR_OFFSET)
#define SAM3U_PIOA_IFDGSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDGSR_OFFSET)
#define SAM3U_PIOA_SCDR (SAM3U_PIOA_BASE+SAM3U_PIO_SCDR_OFFSET)
#define SAM3U_PIOA_OWER (SAM3U_PIOA_BASE+SAM3U_PIO_OWER_OFFSET)
#define SAM3U_PIOA_OWDR (SAM3U_PIOA_BASE+SAM3U_PIO_OWDR_OFFSET)
#define SAM3U_PIOA_OWSR (SAM3U_PIOA_BASE+SAM3U_PIO_OWSR_OFFSET)
#define SAM3U_PIOA_AIMER (SAM3U_PIOA_BASE+SAM3U_PIO_AIMER_OFFSET)
#define SAM3U_PIOA_AIMDR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMDR_OFFSET)
#define SAM3U_PIOA_AIMMR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMMR_OFFSET)
#define SAM3U_PIOA_ESR (SAM3U_PIOA_BASE+SAM3U_PIO_ESR_OFFSET)
#define SAM3U_PIOA_LSR (SAM3U_PIOA_BASE+SAM3U_PIO_LSR_OFFSET)
#define SAM3U_PIOA_ELSR (SAM3U_PIOA_BASE+SAM3U_PIO_ELSR_OFFSET)
#define SAM3U_PIOA_FELLSR (SAM3U_PIOA_BASE+SAM3U_PIO_FELLSR_OFFSET)
#define SAM3U_PIOA_REHLSR (SAM3U_PIOA_BASE+SAM3U_PIO_REHLSR_OFFSET)
#define SAM3U_PIOA_FRLHSR (SAM3U_PIOA_BASE+SAM3U_PIO_FRLHSR_OFFSET)
#define SAM3U_PIOA_LOCKSR (SAM3U_PIOA_BASE+SAM3U_PIO_LOCKSR_OFFSET)
#define SAM3U_PIOA_WPMR (SAM3U_PIOA_BASE+SAM3U_PIO_WPMR_OFFSET)
#define SAM3U_PIOA_WPSR (SAM3U_PIOA_BASE+SAM3U_PIO_WPSR_OFFSET)
#define SAM3U_PIOB_PER (SAM3U_PIOB_BASE+SAM3U_PIO_PER_OFFSET)
#define SAM3U_PIOB_PDR_ (SAM3U_PIOB_BASE+SAM3U_PIO_PDR_OFFSET)
#define SAM3U_PIOB_PSR (SAM3U_PIOB_BASE+SAM3U_PIO_PSR_OFFSET)
#define SAM3U_PIOB_OER (SAM3U_PIOB_BASE+SAM3U_PIO_OER_OFFSET)
#define SAM3U_PIOB_ODR (SAM3U_PIOB_BASE+SAM3U_PIO_ODR_OFFSET)
#define SAM3U_PIOB_OSR (SAM3U_PIOB_BASE+SAM3U_PIO_OSR_OFFSET)
#define SAM3U_PIOB_IFER (SAM3U_PIOB_BASE+SAM3U_PIO_IFER_OFFSET)
#define SAM3U_PIOB_IFDR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDR_OFFSET)
#define SAM3U_PIOB_IFSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFSR_OFFSET)
#define SAM3U_PIOB_SODR (SAM3U_PIOB_BASE+SAM3U_PIO_SODR_OFFSET)
#define SAM3U_PIOB_CODR (SAM3U_PIOB_BASE+SAM3U_PIO_CODR_OFFSET)
#define SAM3U_PIOB_ODSR (SAM3U_PIOB_BASE+SAM3U_PIO_ODSR_OFFSET)
#define SAM3U_PIOB_PDSR (SAM3U_PIOB_BASE+SAM3U_PIO_PDSR_OFFSET)
#define SAM3U_PIOB_IER (SAM3U_PIOB_BASE+SAM3U_PIO_IER_OFFSET)
#define SAM3U_PIOB_IDR (SAM3U_PIOB_BASE+SAM3U_PIO_IDR_OFFSET)
#define SAM3U_PIOB_IMR (SAM3U_PIOB_BASE+SAM3U_PIO_IMR_OFFSET)
#define SAM3U_PIOB_ISR (SAM3U_PIOB_BASE+SAM3U_PIO_ISR_OFFSET)
#define SAM3U_PIOB_MDER (SAM3U_PIOB_BASE+SAM3U_PIO_MDER_OFFSET)
#define SAM3U_PIOB_MDDR (SAM3U_PIOB_BASE+SAM3U_PIO_MDDR_OFFSET)
#define SAM3U_PIOB_MDSR (SAM3U_PIOB_BASE+SAM3U_PIO_MDSR_OFFSET)
#define SAM3U_PIOB_PUDR (SAM3U_PIOB_BASE+SAM3U_PIO_PUDR_OFFSET)
#define SAM3U_PIOB_PUER (SAM3U_PIOB_BASE+SAM3U_PIO_PUER_OFFSET)
#define SAM3U_PIOB_PUSR (SAM3U_PIOB_BASE+SAM3U_PIO_PUSR_OFFSET)
#define SAM3U_PIOB_ABSR (SAM3U_PIOB_BASE+SAM3U_PIO_ABSR_OFFSET)
#define SAM3U_PIOB_SCIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_SCIFSR_OFFSET)
#define SAM3U_PIOB_DIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_DIFSR_OFFSET)
#define SAM3U_PIOB_IFDGSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDGSR_OFFSET)
#define SAM3U_PIOB_SCDR (SAM3U_PIOB_BASE+SAM3U_PIO_SCDR_OFFSET)
#define SAM3U_PIOB_OWER (SAM3U_PIOB_BASE+SAM3U_PIO_OWER_OFFSET)
#define SAM3U_PIOB_OWDR (SAM3U_PIOB_BASE+SAM3U_PIO_OWDR_OFFSET)
#define SAM3U_PIOB_OWSR (SAM3U_PIOB_BASE+SAM3U_PIO_OWSR_OFFSET)
#define SAM3U_PIOB_AIMER (SAM3U_PIOB_BASE+SAM3U_PIO_AIMER_OFFSET)
#define SAM3U_PIOB_AIMDR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMDR_OFFSET)
#define SAM3U_PIOB_AIMMR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMMR_OFFSET)
#define SAM3U_PIOB_ESR (SAM3U_PIOB_BASE+SAM3U_PIO_ESR_OFFSET)
#define SAM3U_PIOB_LSR (SAM3U_PIOB_BASE+SAM3U_PIO_LSR_OFFSET)
#define SAM3U_PIOB_ELSR (SAM3U_PIOB_BASE+SAM3U_PIO_ELSR_OFFSET)
#define SAM3U_PIOB_FELLSR (SAM3U_PIOB_BASE+SAM3U_PIO_FELLSR_OFFSET)
#define SAM3U_PIOB_REHLSR (SAM3U_PIOB_BASE+SAM3U_PIO_REHLSR_OFFSET)
#define SAM3U_PIOB_FRLHSR (SAM3U_PIOB_BASE+SAM3U_PIO_FRLHSR_OFFSET)
#define SAM3U_PIOB_LOCKSR (SAM3U_PIOB_BASE+SAM3U_PIO_LOCKSR_OFFSET)
#define SAM3U_PIOB_WPMR (SAM3U_PIOB_BASE+SAM3U_PIO_WPMR_OFFSET)
#define SAM3U_PIOB_WPSR (SAM3U_PIOB_BASE+SAM3U_PIO_WPSR_OFFSET)
#define SAM3U_PIOC_PER (SAM3U_PIOC_BASE+SAM3U_PIO_PER_OFFSET)
#define SAM3U_PIOC_PDR_ (SAM3U_PIOC_BASE+SAM3U_PIO_PDR_OFFSET)
#define SAM3U_PIOC_PSR (SAM3U_PIOC_BASE+SAM3U_PIO_PSR_OFFSET)
#define SAM3U_PIOC_OER (SAM3U_PIOC_BASE+SAM3U_PIO_OER_OFFSET)
#define SAM3U_PIOC_ODR (SAM3U_PIOC_BASE+SAM3U_PIO_ODR_OFFSET)
#define SAM3U_PIOC_OSR (SAM3U_PIOC_BASE+SAM3U_PIO_OSR_OFFSET)
#define SAM3U_PIOC_IFER (SAM3U_PIOC_BASE+SAM3U_PIO_IFER_OFFSET)
#define SAM3U_PIOC_IFDR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDR_OFFSET)
#define SAM3U_PIOC_IFSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFSR_OFFSET)
#define SAM3U_PIOC_SODR (SAM3U_PIOC_BASE+SAM3U_PIO_SODR_OFFSET)
#define SAM3U_PIOC_CODR (SAM3U_PIOC_BASE+SAM3U_PIO_CODR_OFFSET)
#define SAM3U_PIOC_ODSR (SAM3U_PIOC_BASE+SAM3U_PIO_ODSR_OFFSET)
#define SAM3U_PIOC_PDSR (SAM3U_PIOC_BASE+SAM3U_PIO_PDSR_OFFSET)
#define SAM3U_PIOC_IER (SAM3U_PIOC_BASE+SAM3U_PIO_IER_OFFSET)
#define SAM3U_PIOC_IDR (SAM3U_PIOC_BASE+SAM3U_PIO_IDR_OFFSET)
#define SAM3U_PIOC_IMR (SAM3U_PIOC_BASE+SAM3U_PIO_IMR_OFFSET)
#define SAM3U_PIOC_ISR (SAM3U_PIOC_BASE+SAM3U_PIO_ISR_OFFSET)
#define SAM3U_PIOC_MDER (SAM3U_PIOC_BASE+SAM3U_PIO_MDER_OFFSET)
#define SAM3U_PIOC_MDDR (SAM3U_PIOC_BASE+SAM3U_PIO_MDDR_OFFSET)
#define SAM3U_PIOC_MDSR (SAM3U_PIOC_BASE+SAM3U_PIO_MDSR_OFFSET)
#define SAM3U_PIOC_PUDR (SAM3U_PIOC_BASE+SAM3U_PIO_PUDR_OFFSET)
#define SAM3U_PIOC_PUER (SAM3U_PIOC_BASE+SAM3U_PIO_PUER_OFFSET)
#define SAM3U_PIOC_PUSR (SAM3U_PIOC_BASE+SAM3U_PIO_PUSR_OFFSET)
#define SAM3U_PIOC_ABSR (SAM3U_PIOC_BASE+SAM3U_PIO_ABSR_OFFSET)
#define SAM3U_PIOC_SCIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_SCIFSR_OFFSET)
#define SAM3U_PIOC_DIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_DIFSR_OFFSET)
#define SAM3U_PIOC_IFDGSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDGSR_OFFSET)
#define SAM3U_PIOC_SCDR (SAM3U_PIOC_BASE+SAM3U_PIO_SCDR_OFFSET)
#define SAM3U_PIOC_OWER (SAM3U_PIOC_BASE+SAM3U_PIO_OWER_OFFSET)
#define SAM3U_PIOC_OWDR (SAM3U_PIOC_BASE+SAM3U_PIO_OWDR_OFFSET)
#define SAM3U_PIOC_OWSR (SAM3U_PIOC_BASE+SAM3U_PIO_OWSR_OFFSET)
#define SAM3U_PIOC_AIMER (SAM3U_PIOC_BASE+SAM3U_PIO_AIMER_OFFSET)
#define SAM3U_PIOC_AIMDR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMDR_OFFSET)
#define SAM3U_PIOC_AIMMR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMMR_OFFSET)
#define SAM3U_PIOC_ESR (SAM3U_PIOC_BASE+SAM3U_PIO_ESR_OFFSET)
#define SAM3U_PIOC_LSR (SAM3U_PIOC_BASE+SAM3U_PIO_LSR_OFFSET)
#define SAM3U_PIOC_ELSR (SAM3U_PIOC_BASE+SAM3U_PIO_ELSR_OFFSET)
#define SAM3U_PIOC_FELLSR (SAM3U_PIOC_BASE+SAM3U_PIO_FELLSR_OFFSET)
#define SAM3U_PIOC_REHLSR (SAM3U_PIOC_BASE+SAM3U_PIO_REHLSR_OFFSET)
#define SAM3U_PIOC_FRLHSR (SAM3U_PIOC_BASE+SAM3U_PIO_FRLHSR_OFFSET)
#define SAM3U_PIOC_LOCKSR (SAM3U_PIOC_BASE+SAM3U_PIO_LOCKSR_OFFSET)
#define SAM3U_PIOC_WPMR (SAM3U_PIOC_BASE+SAM3U_PIO_WPMR_OFFSET)
#define SAM3U_PIOC_WPSR (SAM3U_PIOC_BASE+SAM3U_PIO_WPSR_OFFSET)
/* PIO register bit definitions *********************************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
#define PIO(n) (1<<(n)) /* Bit n: PIO n */
/* PIO Write Protect Mode Register */
#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT)
/* PIO Write Protect Status Register */
#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H */
arch/arm/src/sam3u/sam3u_pmc.h
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/****************************************************************************************
* arch/arm/src/sam3u/sam3u_pmc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H
#define __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam3u_memorymap.h"
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* PMC register offsets *****************************************************************/
#define SAM3U_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */
#define SAM3U_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
#define SAM3U_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */
/* 0x000c: Reserved */
#define SAM3U_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */
#define SAM3U_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */
#define SAM3U_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */
#define SAM3U_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
#define SAM3U_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */
#define SAM3U_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
#define SAM3U_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
/* 0x002c: Reserved */
#define SAM3U_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
/* 0x0034-0x003C Reserved */
#define SAM3U_PMC_PCK_OFFSET(n) (0x0040+((n)<<2))
#define SAM3U_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */
#define SAM3U_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */
#define SAM3U_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */
/* 0x004c-0x005c: Reserved */
#define SAM3U_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */
#define SAM3U_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */
#define SAM3U_PMC_SR_OFFSET 0x0068 /* Status Register */
#define SAM3U_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */
#define SAM3U_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */
#define SAM3U_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */
#define SAM3U_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */
/* 0x007c-0x00fc: Reserved */
#define SAM3U_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM3U_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* PMC register adresses ****************************************************************/
#define SAM3U_PMC_SCER (SAM3U_PMC_BASE+SAM3U_PMC_SCER_OFFSET)
#define SAM3U_PMC_SCDR (SAM3U_PMC_BASE+SAM3U_PMC_SCDR_OFFSET)
#define SAM3U_PMC_SCSR (SAM3U_PMC_BASE+SAM3U_PMC_SCSR_OFFSET)
#define SAM3U_PMC_PCER (SAM3U_PMC_BASE+SAM3U_PMC_PCER_OFFSET)
#define SAM3U_PMC_PCDR (SAM3U_PMC_BASE+SAM3U_PMC_PCDR_OFFSET)
#define SAM3U_PMC_PCSR (SAM3U_PMC_BASE+SAM3U_PMC_PCSR_OFFSET)
#define SAM3U_CKGR_UCKR (SAM3U_PMC_BASE+SAM3U_CKGR_UCKR_OFFSET)
#define SAM3U_CKGR_MOR (SAM3U_PMC_BASE+SAM3U_CKGR_MOR_OFFSET)
#define SAM3U_CKGR_MCFR (SAM3U_PMC_BASE+SAM3U_CKGR_MCFR_OFFSET)
#define SAM3U_CKGR_PLLAR (SAM3U_PMC_BASE+SAM3U_CKGR_PLLAR_OFFSET)
#define SAM3U_PMC_MCKR (SAM3U_PMC_BASE+SAM3U_PMC_MCKR_OFFSET)
#define SAM3U_PMC_PCK(n) (SAM3U_PMC_BASE+SAM3U_PMC_PCK_OFFSET(n))
#define SAM3U_PMC_PCK0 (SAM3U_PMC_BASE+SAM3U_PMC_PCK0_OFFSET)
#define SAM3U_PMC_PCK1 (SAM3U_PMC_BASE+SAM3U_PMC_PCK1_OFFSET)
#define SAM3U_PMC_PCK2 (SAM3U_PMC_BASE+SAM3U_PMC_PCK2_OFFSET)
#define SAM3U_PMC_IER (SAM3U_PMC_BASE+SAM3U_PMC_IER_OFFSET)
#define SAM3U_PMC_IDR (SAM3U_PMC_BASE+SAM3U_PMC_IDR_OFFSET)
#define SAM3U_PMC_SR (SAM3U_PMC_BASE+SAM3U_PMC_SR_OFFSET)
#define SAM3U_PMC_IMR (SAM3U_PMC_BASE+SAM3U_PMC_IMR_OFFSET)
#define SAM3U_PMC_FSMR (SAM3U_PMC_BASE+SAM3U_PMC_FSMR_OFFSET)
#define SAM3U_PMC_FSPR (SAM3U_PMC_BASE+SAM3U_PMC_FSPR_OFFSET)
#define SAM3U_PMC_FOCR (SAM3U_PMC_BASE+SAM3U_PMC_FOCR_OFFSET)
#define SAM3U_PMC_WPMR (SAM3U_PMC_BASE+SAM3U_PMC_WPMR_OFFSET)
#define SAM3U_PMC_WPSR (SAM3U_PMC_BASE+SAM3U_PMC_WPSR_OFFSET)
/* PMC register bit definitions *********************************************************/
/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
* Clock Status Register common bit-field definitions
*/
#define PMC_PCK(n) (1 <<((n)+8)
#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */
#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */
#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */
/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
* Peripheral Clock Status Register common bit-field definitions.
*/
#define PMC_PID(n) (1<<(n))
#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */
#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */
#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */
#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */
#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */
#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */
#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */
#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */
#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */
#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */
#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */
#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */
#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */
#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */
#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */
#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */
#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */
#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */
#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */
#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */
#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */
#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */
#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */
#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */
#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */
#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */
#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */
#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */
#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */
#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */
/* PMC UTMI Clock Configuration Register */
#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */
#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */
#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT)
/* PMC Clock Generator Main Oscillator Register */
#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */
#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */
#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */
#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */
#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */
#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT)
#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */
#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT)
#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */
#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT)
#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */
#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */
/* PMC Clock Generator Main Clock Frequency Register */
#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */
#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT)
#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */
/* PMC Clock Generator PLLA Register */
#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */
#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT)
# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */
# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */
# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */
#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT)
#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */
#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT)
# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */
# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */
#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT)
#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */
/* PMC Master Clock Register */
#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */
#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT)
# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */
# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */
# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */
# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */
#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */
#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT)
# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */
# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */
# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */
# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */
# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */
# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */
# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */
#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */
/* PMC Programmable Clock Register (0,1,2) */
#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK)
# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */
# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */
# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */
# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */
# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */
#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */
# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */
# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */
# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */
# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */
# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
* and PMC Interrupt Mask Register common bit-field definitions
*/
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */
#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */
#define PMC_INT_PCKRDY(n) (1<<((n)+8)
#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */
#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */
#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */
#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */
#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */
#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */
#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field
* definitions
*/
#define PMC_FSTI(n) (1<<(n))
#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */
#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */
#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */
#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */
#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */
#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */
#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */
#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */
#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */
#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */
#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */
#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */
#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */
#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */
#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */
#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */
#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */
#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */
#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */
#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */
/* PMC Fault Output Clear Register */
#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */
/* PMC Write Protect Mode Register */
#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT)
/* PMC Write Protect Status Register */
#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H */
arch/arm/src/sam3u/sam3u_pwm.h
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