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SAMA5D4: Fix error in EMAC driver (plus related EMAC/GMAC drivers)

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This commit is contained in:
Gregory Nutt
2014-07-01 11:22:19 -06:00
parent 621ec21bfd
commit 289dc6dc71
4 changed files with 23 additions and 51 deletions
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arch/arm/src/sam34/sam_emac.c
+6 -13
View File
@@ -2289,7 +2289,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
/* Setup the EMAC link speed */
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= (EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
regval &= ~(EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
if (((advertise & lpa) & MII_ADVERTISE_100BASETXFULL) != 0)
{
@@ -2658,8 +2658,6 @@ static void sam_rxreset(struct sam_emac_s *priv)
static void sam_emac_reset(struct sam_emac_s *priv)
{
uint32_t regval;
/* Disable all EMAC interrupts */
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
@@ -2669,10 +2667,9 @@ static void sam_emac_reset(struct sam_emac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Disable RX, TX, and statistics */
/* Make sure that RX and TX are disabled; clear statistics registers */
regval = EMAC_NCR_TXEN | EMAC_NCR_RXEN | EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_EMAC_NCR, regval);
sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT);
/* Disable clocking to the EMAC peripheral */
@@ -2745,15 +2742,11 @@ static int sam_emac_configure(struct sam_emac_s *priv)
sam_emac_enableclk();
/* Disable TX, RX, interrupts, etc. */
/* Disable TX, RX, clear statistics. Disable all interrupts. */
sam_putreg(priv, SAM_EMAC_NCR, 0);
sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT);
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_EMAC_NCR, regval);
/* Clear all status bits in the receive status register. */
regval = (EMAC_RSR_RXOVR | EMAC_RSR_REC | EMAC_RSR_BNA);
@@ -2795,7 +2788,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Enable Rx and Tx, plus the stats register. */
/* Enable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= (EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
arch/arm/src/sama5/sam_emaca.c
+6 -13
View File
@@ -2312,7 +2312,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
/* Setup the EMAC link speed */
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= (EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
regval &= ~(EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
if (((advertise & lpa) & MII_ADVERTISE_100BASETXFULL) != 0)
{
@@ -2708,8 +2708,6 @@ static void sam_rxreset(struct sam_emac_s *priv)
static void sam_emac_reset(struct sam_emac_s *priv)
{
uint32_t regval;
/* Disable all EMAC interrupts */
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
@@ -2719,10 +2717,9 @@ static void sam_emac_reset(struct sam_emac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Disable RX, TX, and statistics */
/* Make sure that RX and TX are disabled; clear statistics registers */
regval = EMAC_NCR_TE | EMAC_NCR_RE | EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_EMAC_NCR, regval);
sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT);
/* Disable clocking to the EMAC peripheral */
@@ -2795,15 +2792,11 @@ static int sam_emac_configure(struct sam_emac_s *priv)
sam_emac_enableclk();
/* Disable TX, RX, interrupts, etc. */
/* Disable TX, RX, clear statistics. Disable all interrupts. */
sam_putreg(priv, SAM_EMAC_NCR, 0);
sam_putreg(priv, SAM_EMAC_NCR, EMAC_NCR_CLRSTAT);
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_ALL);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_EMAC_NCR, regval);
/* Clear all status bits in the receive status register. */
regval = (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA);
@@ -2845,7 +2838,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Enable Rx and Tx, plus the stats register. */
/* Enable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= (EMAC_NCR_RE | EMAC_NCR_TE | EMAC_NCR_WESTAT);
arch/arm/src/sama5/sam_emacb.c
+6 -13
View File
@@ -2768,7 +2768,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
/* Setup the EMAC link speed */
regval = sam_getreg(priv, SAM_EMAC_NCFGR_OFFSET);
regval &= (EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
regval &= ~(EMAC_NCFGR_SPD | EMAC_NCFGR_FD);
if (((advertise & lpa) & MII_ADVERTISE_100BASETXFULL) != 0)
{
@@ -3317,8 +3317,6 @@ static void sam_emac_disableclk(struct sam_emac_s *priv)
static void sam_emac_reset(struct sam_emac_s *priv)
{
uint32_t regval;
/* Disable all EMAC interrupts */
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_ALL);
@@ -3328,10 +3326,9 @@ static void sam_emac_reset(struct sam_emac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Disable RX, TX, and statistics */
/* Make sure that RX and TX are disabled; clear statistics registers */
regval = EMAC_NCR_TXEN | EMAC_NCR_RXEN | EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, EMAC_NCR_CLRSTAT);
/* Disable clocking to the EMAC peripheral */
@@ -3404,15 +3401,11 @@ static int sam_emac_configure(struct sam_emac_s *priv)
sam_emac_enableclk(priv);
/* Disable TX, RX, interrupts, etc. */
/* Disable TX, RX, clear statistics. Disable all interrupts. */
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, 0);
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, EMAC_NCR_CLRSTAT);
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_ALL);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
/* Clear all status bits in the receive status register. */
regval = (EMAC_RSR_RXOVR | EMAC_RSR_REC | EMAC_RSR_BNA);
@@ -3454,7 +3447,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Enable Rx and Tx, plus the stats register. */
/* Enable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= (EMAC_NCR_RXEN | EMAC_NCR_TXEN | EMAC_NCR_WESTAT);
arch/arm/src/sama5/sam_gmac.c
+5 -12
View File
@@ -2762,8 +2762,6 @@ static void sam_rxreset(struct sam_gmac_s *priv)
static void sam_gmac_reset(struct sam_gmac_s *priv)
{
uint32_t regval;
/* Disable all GMAC interrupts */
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
@@ -2773,10 +2771,9 @@ static void sam_gmac_reset(struct sam_gmac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Disable RX, TX, and statistics */
/* Make sure that RX and TX are disabled; clear statistics registers */
regval = GMAC_NCR_TXEN | GMAC_NCR_RXEN | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_GMAC_NCR, regval);
sam_putreg(priv, SAM_GMAC_NCR, GMAC_NCR_CLRSTAT);
/* Disable clocking to the GMAC peripheral */
@@ -2849,15 +2846,11 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
sam_gmac_enableclk();
/* Disable TX, RX, interrupts, etc. */
/* Disable TX, RX, clear statistics. Disable all interrupts. */
sam_putreg(priv, SAM_GMAC_NCR, 0);
sam_putreg(priv, SAM_GMAC_NCR, GMAC_NCR_CLRSTAT);
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
regval = sam_getreg(priv, SAM_GMAC_NCR);
regval |= GMAC_NCR_CLRSTAT;
sam_putreg(priv, SAM_GMAC_NCR, regval);
/* Clear all status bits in the receive status register. */
regval = (GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA | GMAC_RSR_HNO);
@@ -2920,7 +2913,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
sam_rxreset(priv);
sam_txreset(priv);
/* Enable Rx and Tx, plus the stats register. */
/* Enable Rx and Tx, plus the statistics registers. */
regval = sam_getreg(priv, SAM_GMAC_NCR);
regval |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN | GMAC_NCR_WESTAT);