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Fix lots of typos in C comments and Kconfig help text

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This commit is contained in:
Alan Carvalho de Assis
2018-07-08 18:24:45 -06:00
committed by Gregory Nutt
parent 1783d344dc
commit 283b73edc5
106 changed files with 187 additions and 187 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ChangeLog
+3 -3
View File
@@ -7164,7 +7164,7 @@
structures are initialized, they will not behave properly
(2014-4-10).
* arch/arm/src/sama5/sam_twi.c: TWI data sending is fails to increment
the number of byes transferred on first byte sent. from David Sidrane
the number of bytes transferred on first byte sent. From David Sidrane
(2014-4-10).
* configs/sama5d3x-ek/src: The red LED is controlled by PE24 which is
also the camera/ISI interface reset line. So if the a camera is
@@ -10049,7 +10049,7 @@
The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call
that rightfully enables the lsi clock; but the next times, when the
rtc is already setup, the rtc_resume() call does NOT start the lsi
clock! The right place to put LSE/LSI initialisation is inside
clock! The right place to put LSE/LSI initialization is inside
stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked
the possible uses of the LSI and the LSE sources: the LSI can be used
for RTC and/or the IWDG, while the LSE only for the RTC (and to output
@@ -12336,7 +12336,7 @@
* STM32L4: Port foward bugfix from stm32 of oneshot timer. From
ziggurat29 (2016-07-13).
* STM32 and EFM32: I'm using syslog through ITM. In this case
syslog_channel function is call before RAM initialisation in
syslog_channel function is call before RAM initialization in
stm32_clockconfig. But syslog channel uses a global variable that is
reset to default by the RAM initialization. From Pierre-noel
Bouteville (2016-07-14).
Documentation/NXGraphicsSubsystem.html
+1 -1
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@@ -3263,7 +3263,7 @@ int nxf_convert_32bpp(FAR uint32_t *dest, uint16_t height,
<dd>By default, NX builds to use a framebuffer driver (see <code>include/nuttx/video/fb.h</code>).
If this option is defined, NX will build to use an LCD driver (see <code>include/nuttx/lcd/lcd.h</code>).
<dt><code>CONFIG_NX_ANTIALIASING</code>:
<dd>Enable support for ant-aliasing when rendering lines as various
<dd>Enable support for anti-aliasing when rendering lines as various
orientations.
This option is only available for use with frame buffer drivers and
only with 16-, 24-, or 32-bit RGB color formats.
Documentation/NuttShell.html
+1 -1
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@@ -3329,7 +3329,7 @@ nsh&gt;
</p>
<p>
There are several built-in appliations in the <code>apps/</code> repository.
There are several built-in applications in the <code>apps/</code> repository.
No attempt is made here to enumerate all of them.
But a few of the more common, useful built-in applications are listed below.
</p>
Documentation/NuttX.html
+1 -1
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@@ -3216,7 +3216,7 @@ nsh>
<b>Olimexino-STM32</b>.
This port uses the Olimexino STM32 board (STM32F103RBT6).
See the http://www.olimex.com for further information.
Contribued by David Sidrane.
Contributed by David Sidrane.
</p>
</li>
</ol>
Documentation/UsbTrace.html
+1 -1
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@@ -100,7 +100,7 @@
<ol>
<li>8-bits of the trace ID (values associated with the above)</li>
<li>8-bits of additional trace ID data, and</li>
<li>16-bits of additonal data.</li>
<li>16-bits of additional data.</li>
</ol>
<p><b>8-bit Trace Data</b>
The 8-bit trace data depends on the specific event ID. As examples,
Kconfig
+4 -4
View File
@@ -19,7 +19,7 @@ config DEFAULT_SMALL
default n
---help---
When options are present, the default value for certain options will
be the one the results in the smallest size (at a loss of featurs).
be the one the results in the smallest size (at a loss of features).
The default is a fuller feature set at a larger size.
NOTE: This option does not prevent you from overriding the default
@@ -75,7 +75,7 @@ config WINDOWS_CYGWIN
config WINDOWS_UBUNTU
bool "Ubuntu under Windows 10"
---help---
Build natively in an Unbuntu shell under Windoes 10 environment with
Build natively in an Ubuntu shell under Windoes 10 environment with
POSIX style paths (like /mnt/c/Program Files)
config WINDOWS_MSYS
@@ -495,7 +495,7 @@ config DEBUG_AUDIO
depends on AUDIO
---help---
Enable audio device debug features.
Enable low level debug featurs for the audio subsystem and for audio
Enable low level debug features for the audio subsystem and for audio
device drivers. (disabled by default). Support for this debug option
is architecture-specific and may not be available for some MCUs.
@@ -1063,7 +1063,7 @@ config DEBUG_INPUT
depends on INPUT
---help---
Enable input d.
Enable low level evice debug features for the input device drivers
Enable low level device debug features for the input device drivers
such as mice and touchscreens (disabled by default). Support for
this debug option is board-specific and may not be available for
some boards.
ReleaseNotes
+2 -2
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@@ -6292,7 +6292,7 @@ Bugfixes (see the ChangeLog for details). Some of these are very important:
- Fix a case in the UDPHS driver where received status was not being
cleared, causing OUT SETUP commands to fail.
- TWI data sending fails to increment the number of byes transferred
- TWI data sending fails to increment the number of bytes transferred
on first byte sent. from David Sidrane.
- If running from SDRAM, then BOARD_MCK_FREQUENCY is not a constant
and cannot be used in conditional compilation. All drivers fixed
@@ -8783,7 +8783,7 @@ detailed bugfix information):
register lead to rtc_setup() call that rightfully enables the LSI
clock; but the next times, when the rtc is already setup, the
rtc_resume() call does NOT start the LSI clock! The right place to
put LSE/LSI initialisation is inside stm32_stdclockconfig() in
put LSE/LSI initialization is inside stm32_stdclockconfig() in
stm32fxxxxx_rcc.c. Doing this I checked the possible uses of the
LSI and the LSE sources: the LSI can be used for RTC and/or the
IWDG, while the LSE only for the RTC (and to output the MCO1 pin).
arch/Kconfig
+1 -1
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@@ -427,7 +427,7 @@ config ARCH_PGPOOL_VBASE
environment logic.
config ARCH_PGPOOL_SIZE
int "Page pool size (byes)"
int "Page pool size (bytes)"
default 0
---help---
The size of the page pool memory in bytes. This setting is probably
arch/arm/Kconfig
+1 -1
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@@ -734,7 +734,7 @@ config DEBUG_HARDFAULT
---help---
Enables verbose debug output when a hard fault is occurs. This verbose
output is sometimes helpful when debugging difficult hard fault problems,
but may be more than you typcially want to see.
but may be more than you typically want to see.
if ARCH_CORTEXM0
source arch/arm/src/armv6-m/Kconfig
arch/arm/include/imx6/irq.h
+16 -16
View File
@@ -70,22 +70,22 @@
* registers, not the priority set by the sending Cortex-A9 processor.
*/
#define IMX_IRQ_SGI0 0 /* Sofware Generated Interrupt (SGI) 0 */
#define IMX_IRQ_SGI1 1 /* Sofware Generated Interrupt (SGI) 1 */
#define IMX_IRQ_SGI2 2 /* Sofware Generated Interrupt (SGI) 2 */
#define IMX_IRQ_SGI3 3 /* Sofware Generated Interrupt (SGI) 3 */
#define IMX_IRQ_SGI4 4 /* Sofware Generated Interrupt (SGI) 4 */
#define IMX_IRQ_SGI5 5 /* Sofware Generated Interrupt (SGI) 5 */
#define IMX_IRQ_SGI6 6 /* Sofware Generated Interrupt (SGI) 6 */
#define IMX_IRQ_SGI7 7 /* Sofware Generated Interrupt (SGI) 7 */
#define IMX_IRQ_SGI8 8 /* Sofware Generated Interrupt (SGI) 8 */
#define IMX_IRQ_SGI9 9 /* Sofware Generated Interrupt (SGI) 9 */
#define IMX_IRQ_SGI10 10 /* Sofware Generated Interrupt (SGI) 10 */
#define IMX_IRQ_SGI11 11 /* Sofware Generated Interrupt (SGI) 11 */
#define IMX_IRQ_SGI12 12 /* Sofware Generated Interrupt (SGI) 12 */
#define IMX_IRQ_SGI13 13 /* Sofware Generated Interrupt (SGI) 13 */
#define IMX_IRQ_SGI14 14 /* Sofware Generated Interrupt (SGI) 14 */
#define IMX_IRQ_SGI15 15 /* Sofware Generated Interrupt (SGI) 15 */
#define IMX_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */
#define IMX_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */
#define IMX_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */
#define IMX_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */
#define IMX_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */
#define IMX_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */
#define IMX_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */
#define IMX_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */
#define IMX_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */
#define IMX_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */
#define IMX_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */
#define IMX_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */
#define IMX_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */
#define IMX_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */
#define IMX_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */
#define IMX_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */
#define IMX_IRQ_GTM 27 /* Global Timer (GTM) PPI(0) */
#define IMX_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(1) */
arch/arm/src/armv7-a/gic.h
+16 -16
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@@ -563,22 +563,22 @@
* task management.
*/
#define GIC_IRQ_SGI0 0 /* Sofware Generated Interrupt (SGI) 0 */
#define GIC_IRQ_SGI1 1 /* Sofware Generated Interrupt (SGI) 1 */
#define GIC_IRQ_SGI2 2 /* Sofware Generated Interrupt (SGI) 2 */
#define GIC_IRQ_SGI3 3 /* Sofware Generated Interrupt (SGI) 3 */
#define GIC_IRQ_SGI4 4 /* Sofware Generated Interrupt (SGI) 4 */
#define GIC_IRQ_SGI5 5 /* Sofware Generated Interrupt (SGI) 5 */
#define GIC_IRQ_SGI6 6 /* Sofware Generated Interrupt (SGI) 6 */
#define GIC_IRQ_SGI7 7 /* Sofware Generated Interrupt (SGI) 7 */
#define GIC_IRQ_SGI8 8 /* Sofware Generated Interrupt (SGI) 8 */
#define GIC_IRQ_SGI9 9 /* Sofware Generated Interrupt (SGI) 9 */
#define GIC_IRQ_SGI10 10 /* Sofware Generated Interrupt (SGI) 10 */
#define GIC_IRQ_SGI11 11 /* Sofware Generated Interrupt (SGI) 11 */
#define GIC_IRQ_SGI12 12 /* Sofware Generated Interrupt (SGI) 12 */
#define GIC_IRQ_SGI13 13 /* Sofware Generated Interrupt (SGI) 13 */
#define GIC_IRQ_SGI14 14 /* Sofware Generated Interrupt (SGI) 14 */
#define GIC_IRQ_SGI15 15 /* Sofware Generated Interrupt (SGI) 15 */
#define GIC_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */
#define GIC_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */
#define GIC_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */
#define GIC_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */
#define GIC_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */
#define GIC_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */
#define GIC_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */
#define GIC_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */
#define GIC_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */
#define GIC_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */
#define GIC_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */
#define GIC_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */
#define GIC_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */
#define GIC_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */
#define GIC_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */
#define GIC_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */
#define GIC_IRQ_GTM 27 /* Global Timer (GTM) PPI(0) */
#define GIC_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(1) */
arch/arm/src/kinetis/Kconfig
+1 -1
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@@ -1070,7 +1070,7 @@ config KINETIS_UART_SINGLEWIRE
depends on KINETIS_UART || KINETIS_LPUART
---help---
Enable single wire UART and LPUART support. The option enables support
for the TIOCSSINGLEWIRE ioctl in the Kineteis serial drivers.
for the TIOCSSINGLEWIRE ioctl in the Kinetis serial drivers.
endif # KINETIS_SERIALDRIVER || OTHER_SERIALDRIVER
arch/arm/src/lc823450/lc823450_dvfs2.c
+1 -1
View File
@@ -626,7 +626,7 @@ exit_with_error:
/****************************************************************************
* Name: lc823450_dvfs_boost
* boost the sytem clock to MAX (i.e. 160M)
* boost the system clock to MAX (i.e. 160M)
* timeout in msec
****************************************************************************/
arch/arm/src/lpc11xx/Kconfig
+1 -1
View File
@@ -136,7 +136,7 @@ config LPC11_ADC_CHANLIST
matching the LPC11_ADC0_MASK within the board-specific library.
config LPC11_ADC_BURSTMODE
bool "One interrupt at the end of all ADC cconversions"
bool "One interrupt at the end of all ADC conversions"
default n
---help---
Select this if you want to generate only one interrupt once all
arch/arm/src/lpc17xx/Kconfig
+3 -3
View File
@@ -524,7 +524,7 @@ config LPC17_ADC_CHANLIST
matching the LPC17_ADC0_MASK within the board-specific library.
config LPC17_ADC_BURSTMODE
bool "One interrupt at the end of all ADC cconversions"
bool "One interrupt at the end of all ADC conversions"
default n
---help---
Select this if you want to generate only one interrupt once all selected
@@ -656,9 +656,9 @@ menu "Ethernet driver options"
depends on LPC17_ETHERNET
config LPC17_PHY_AUTONEG
bool "Autonegiation"
bool "Autonegotiation"
---help---
Enable auto-negotion
Enable auto-negotiation
config LPC17_PHY_SPEED100
bool "100Mbit/Sec"
arch/arm/src/lpc43xx/Kconfig
+3 -3
View File
@@ -427,7 +427,7 @@ config LPC43_EXTSDRAM1
depends on ARCH_HAVE_EXTSDRAM1
select ARCH_HAVE_EXTSDRAM
---help---
Configure external SDRAM memoryand, if applicable, map then external
Configure external SDRAM memory, if applicable, map then external
SDRAM into the memory map.
if LPC43_EXTSDRAM1
@@ -452,7 +452,7 @@ config LPC43_EXTSDRAM2
depends on ARCH_HAVE_EXTSDRAM2
select ARCH_HAVE_EXTSDRAM
---help---
Configure external SDRAM memoryand, if applicable, map then external
Configure external SDRAM memory, if applicable, map then external
SDRAM into the memory map.
if LPC43_EXTSDRAM2
@@ -477,7 +477,7 @@ config LPC43_EXTSDRAM3
depends on ARCH_HAVE_EXTSDRAM3
select ARCH_HAVE_EXTSDRAM
---help---
Configure external SDRAM memoryand, if applicable, map then external
Configure external SDRAM memory, if applicable, map then external
SDRAM into the memory map.
if LPC43_EXTSDRAM3
arch/arm/src/lpc54xx/lpc54_emc.c
+1 -1
View File
@@ -245,7 +245,7 @@ void lpc54_emc_initialize(FAR const struct emc_config_s *config)
lpc54_reset_emc();
/* Set the EMC sytem configure */
/* Set the EMC system configuration */
putreg32(SYSCON_EMCCLKDIV_DIV(config->clkdiv), LPC54_SYSCON_EMCCLKDIV);
arch/arm/src/lpc54xx/lpc54_ethernet.c
+1 -1
View File
@@ -2884,7 +2884,7 @@ static int lpc54_phy_autonegotiate(struct lpc54_ethdriver_s *priv)
{
if (timeout-- <= 0)
{
nerr("ERROR: Autonegotion timed out\n");
nerr("ERROR: Autonegotiation timed out\n");
return -ETIMEDOUT;
}
arch/arm/src/nuc1xx/chip/nuc_gcr.h
+1 -1
View File
@@ -95,7 +95,7 @@
#define GCR_RSTSRC_LVR (1 << 3) /* Bit 3: Low voltage reset controller */
#define GCR_RSTSRC_BOD (1 << 4) /* Bit 4: Brown-out detection */
#define GCR_RSTSRC_SYS (1 << 5) /* Bit 5: Software set AIRCR:SYSRESETREQ */
#define GCR_RSTSRC_CPU (1 << 7) /* Bit 7: Sofware set CPU_RST */
#define GCR_RSTSRC_CPU (1 << 7) /* Bit 7: Software set CPU_RST */
/* IP Reset control register 1 */
arch/arm/src/sam34/sam_hsmci.c
+1 -1
View File
@@ -1801,7 +1801,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
* Name: sam_blocksetup
*
* Description:
* Some hardward needs to be informed of the selected blocksize.
* Some hardware needs to be informed of the selected blocksize.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
arch/arm/src/sama5/Kconfig
+3 -3
View File
@@ -3242,7 +3242,7 @@ config SAMA5_ADC_DMASAMPLES
2 Buffers * Number_of_ADC_Channels * SAMA5_ADC_DMASAMPLES * sizeof(uint16_t)
So, for example, if you had 8 ADC channels and 8 triggers per DMA
transfer, then the total DMA buffering requirment would be:
transfer, then the total DMA buffering requirement would be:
2 * 8 * 8 * 2 = 256 bytes.
@@ -4969,7 +4969,7 @@ config SAMA5_DDRCS_PGHEAP_OFFSET
you must have excluding this page cache region from the heap ether
by (1) not selecting SAMA5_DDRCS_HEAP, or (2) selecting
SAMA5_DDRCS_HEAP_OFFSET and SAMA5_DDRCS_HEAP_SIZE so that the page
cache region does not overlapy the region of DRAM that is added to
cache region does not overlap the region of DRAM that is added to
the heap.
config SAMA5_DDRCS_PGHEAP_SIZE
@@ -4987,7 +4987,7 @@ config SAMA5_DDRCS_PGHEAP_SIZE
you must have excluding this page cache region from the heap ether
by (1) not selecting SAMA5_DDRCS_HEAP, or (2) selecting
SAMA5_DDRCS_HEAP_OFFSET and SAMA5_DDRCS_HEAP_SIZE so that the page
cache region does not overlapy the region of DRAM that is added to
cache region does not overlap the region of DRAM that is added to
the heap.
endif # SAMA5_DDRCS_PGHEAP
arch/arm/src/sama5/sam_can.c
+1 -1
View File
@@ -602,7 +602,7 @@ static int can_mballoc(FAR struct sam_can_s *priv)
for (i = 0; i < SAM_CAN_NMAILBOXES; i++)
{
/* Is mailbox i availalbe? */
/* Is mailbox i available? */
uint8_t bit = (1 << i);
if ((priv->freemb & bit) != 0)
arch/arm/src/sama5/sam_hsmci.c
+1 -1
View File
@@ -2095,7 +2095,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
* Name: sam_blocksetup
*
* Description:
* Some hardward needs to be informed of the selected blocksize.
* Some hardware needs to be informed of the selected blocksize.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
arch/arm/src/samv7/Kconfig
+1 -1
View File
@@ -1766,7 +1766,7 @@ config SAMV7_HSMCI_UNALIGNED
beginning of a sector and at least a whole sector is being read.
This option is not recommended. There are better ways to handle
the unalaigned case:
the unaligned case:
# CONFIG_SAMV7_HSMCI_UNALIGNED is not set
Just return -EFAULT if unaligned
arch/arm/src/samv7/sam_hsmci.c
+1 -1
View File
@@ -2072,7 +2072,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
* Name: sam_blocksetup
*
* Description:
* Some hardward needs to be informed of the selected blocksize.
* Some hardware needs to be informed of the selected blocksize.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
arch/arm/src/stm32/chip/stm32_dma2d.h
+1 -1
View File
@@ -101,7 +101,7 @@
#define DMA2D_CR_START (1 << 0) /* Start Bit */
#define DMA2D_CR_SUSP (1 << 1) /* Suspend Bit */
#define DMA2D_CR_ABORT (1 << 2) /* Abort Bit */
#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interupt Enable Bit */
#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interrupt Enable Bit */
#define DMA2D_CR_TCIE (1 << 9) /* Transfer Complete Interrupt Enable Bit */
#define DMA2D_CR_TWIE (1 << 10) /* Transfer Watermark Interrupt Enable Bit */
#define DMA2D_CR_CAEIE (1 << 11) /* CLUT Access Error Interrupt Enable Bit */
arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
+3 -3
View File
@@ -1096,7 +1096,7 @@
#define HRTIM_CR2_TDRST (1 << 12) /* Bit 12: Timer D Counter Software Reset*/
#define HRTIM_CR2_TERST (1 << 13) /* Bit 13: Timer E Counter Software Reset*/
/* Common Interupt Status Register */
/* Common Interrupt Status Register */
#define HRTIM_ISR_FLT1 (1 << 0) /* Bit 0: Fault 1 Interrupt Flag */
#define HRTIM_ISR_FLT2 (1 << 1) /* Bit 1: Fault 2 Interrupt Flag */
@@ -1107,7 +1107,7 @@
#define HRTIM_ISR_DLLRDY (1 << 16) /* Bit 16: DLL Ready Interrupt Flag */
#define HRTIM_ISR_BMPER (1 << 17) /* Bit 17: Burst mode Period Interrupt Flag */
/* Common Interupt Clear Register */
/* Common Interrupt Clear Register */
#define HRTIM_ICR_FLT1C (1 << 0) /* Bit 0: Fault 1 Interrupt Flag Clear */
#define HRTIM_ICR_FLT2C (1 << 1) /* Bit 1: Fault 2 Interrupt Flag Clear */
@@ -1118,7 +1118,7 @@
#define HRTIM_ICR_DLLRDYC (1 << 16) /* Bit 16: DLL Ready Interrupt Flag Clear */
#define HRTIM_ICR_BMPERC (1 << 17) /* Bit 17: Burst mode Period Interrupt Flag Clear */
/* Common Interupt Enable Register */
/* Common Interrupt Enable Register */
#define HRTIM_IER_FLT1IE (1 << 0) /* Bit 0: Fault 1 Interrupt Enable */
#define HRTIM_IER_FLT2IE (1 << 1) /* Bit 1: Fault 2 Interrupt Enable */
arch/arm/src/stm32/stm32_ltdc.c
+1 -1
View File
@@ -1977,7 +1977,7 @@ static void stm32_ltdc_lchromakeyenable(FAR struct stm32_ltdc_s *layer,
regval = getreg32(stm32_cr_layer_t[layer->layerno]);
/* Enable/Disble colorkey */
/* Enable/Disable colorkey */
if (enable == true)
{
arch/arm/src/stm32f7/chip/stm32_dma2d.h
+1 -1
View File
@@ -101,7 +101,7 @@
#define DMA2D_CR_START (1 << 0) /* Start Bit */
#define DMA2D_CR_SUSP (1 << 1) /* Suspend Bit */
#define DMA2D_CR_ABORT (1 << 2) /* Abort Bit */
#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interupt Enable Bit */
#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interrupt Enable Bit */
#define DMA2D_CR_TCIE (1 << 9) /* Transfer Complete Interrupt Enable Bit */
#define DMA2D_CR_TWIE (1 << 10) /* Transfer Watermark Interrupt Enable Bit */
#define DMA2D_CR_CAEIE (1 << 11) /* CLUT Access Error Interrupt Enable Bit */
arch/arm/src/stm32f7/stm32_ltdc.c
+1 -1
View File
@@ -1979,7 +1979,7 @@ static void stm32_ltdc_lchromakeyenable(FAR struct stm32_ltdc_s *layer,
regval = getreg32(stm32_cr_layer_t[layer->layerno]);
/* Enable/Disble colorkey */
/* Enable/Disable colorkey */
if (enable == true)
{
arch/arm/src/stm32l4/Kconfig
+1 -1
View File
@@ -707,7 +707,7 @@ config STM32L4_SRAM2_INIT
avoided by first writing to all locations to force the parity into a valid
state.
However, if the SRAM2 is being used for it's battery-backed capability,
this may be undesireable (because it will destroy the contents). In that
this may be undesirable (because it will destroy the contents). In that
case, the board should handle the initialization itself at the appropriate
time.
arch/arm/src/str71x/str71x_eic.h
+2 -2
View File
@@ -48,7 +48,7 @@
* Pre-processor Definitions
************************************************************************************/
/* Enhanced Interupt Controller (EIC) register offsets ******************************/
/* Enhanced Interrupt Controller (EIC) register offsets *****************************/
#define STR71X_EIC_ICR_OFFSET (0x0000) /* 32-bits wide */
#define STR71X_EIC_CICR_OFFSET (0x0004) /* 32-bits wide */
@@ -95,7 +95,7 @@
#define STR71X_EIC_NCHANNELS (32)
#define STR71X_EIC_SIR_BASE (STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET)
/* Enhanced Interupt Controller (EIC) registers *************************************/
/* Enhanced Interrupt Controller (EIC) registers ************************************/
#define STR71X_EIC_ICR (STR71X_EIC_BASE + STR71X_EIC_ICR_OFFSET)
#define STR71X_EIC_CICR (STR71X_EIC_BASE + STR71X_EIC_CICR_OFFSET)
arch/arm/src/str71x/str71x_xti.h
+1 -1
View File
@@ -48,7 +48,7 @@
* Pre-processor Definitions
************************************************************************************/
/* External Interupt Controller (XTI) registers *************************************/
/* External Interrupt Controller (XTI) registers ************************************/
#define STR71X_XTI_SR (STR71X_XTI_BASE + 0x001c) /* 8-bits wide */
#define STR71X_XTI_CTRL (STR71X_XTI_BASE + 0x0024) /* 8-bits wide */
arch/mips/src/pic32mx/Kconfig
+1 -1
View File
@@ -1085,7 +1085,7 @@ config PIC32MX_ETH_PRIORITY
default 28
depends on PIC32MX_ETHERNET
---help---
Ethernet interrupt priority. The is default is the higest priority.
Ethernet interrupt priority. The is default is the highest priority.
config PIC32MX_MULTICAST
bool "Multicast"
arch/mips/src/pic32mz/Kconfig
+1 -1
View File
@@ -412,7 +412,7 @@ config PIC32MZ_ETH_PRIORITY
default 28
depends on PIC32MZ_ETHERNET
---help---
Ethernet interrupt priority. The is default is the higest priority.
Ethernet interrupt priority. The is default is the highest priority.
config PIC32MZ_MULTICAST
bool "Multicast"
arch/renesas/src/sh1/sh1_703x.h
+1 -1
View File
@@ -444,7 +444,7 @@
#define SH1_ICR_IRQ2S (0x0020) /* Bits 5: Interrupt on falling edge of IRQ2 input */
#define SH1_ICR_IRQ1S (0x0040) /* Bits 6: Interrupt on falling edge of IRQ1 input */
#define SH1_ICR_IRQ0S (0x0080) /* Bits 7: Interrupt on falling edge of IRQ0 input */
#define SH1_ICR_NMIE (0x0100) /* Bits 8: Interupt on rising edge of NMI input */
#define SH1_ICR_NMIE (0x0100) /* Bits 8: Interrupt on rising edge of NMI input */
#define SH1_ICR_NMIL (0x8000) /* Bits 15: NMI input level high */
/************************************************************************************
arch/sim/Kconfig
+1 -1
View File
@@ -210,7 +210,7 @@ config SIM_TOUCHSCREEN
config SIM_AJOYSTICK
bool "X11 mouse-based analog joystick emulation"
---help---
Support an X11 mouse-based anallog joystick emulation. Also needs INPUT=y`
Support an X11 mouse-based analog joystick emulation. Also needs INPUT=y
config SIM_NOINPUT
bool "No input device"
audio/Kconfig
+6 -6
View File
@@ -56,7 +56,7 @@ config AUDIO_DRIVER_SPECIFIC_BUFFERS
By default, the Audio system uses the same size and number of buffers
regardless of the specific audio device in use. Specifying 'y' here
adds extra code which allows the lower-level audio device to specify
a partucular size and number of buffers.
a particular size and number of buffers.
endmenu # Audio Buffer Configuration
@@ -149,7 +149,7 @@ config AUDIO_EXCLUDE_PAUSE_RESUME
---help---
Exclude building support for pausing and resuming audio files
once they are submitted. If the sound system is being used to play
short system notification or error type sounds that typicaly only
short system notification or error type sounds that typically only
last a second or two, then there is no need (or chance) to pause or
resume sound playback once it has started.
@@ -158,7 +158,7 @@ config AUDIO_EXCLUDE_STOP
default n
---help---
Exclude building support for stopping audio files once they are
submitted. If the sound system is being used to play short sytem
submitted. If the sound system is being used to play short system
notification or error type sounds that typically only last a second
or two, then there is no need (or chance) to stop the sound
playback once it has started.
@@ -225,16 +225,16 @@ config AUDIO_MIXER
to perform audio channel or device mixing.
config AUDIO_MIDI_SYNTH
bool "Planned - Enable support for the software-based MIDI synthisizer"
bool "Planned - Enable support for the software-based MIDI synthesizer"
default n
---help---
Builds a simple MIDI synthisizer.
Builds a simple MIDI synthesizer.
config AUDIO_OUTPUT_JACK_CONTROL
bool "Planned - Enable support for output jack control"
default n
---help---
Builds a simple MIDI synthisizer.
Builds a simple MIDI synthesizer.
config AUDIO_FONT
bool "Planned - Enable support for the Audio Font"
audio/README.txt
+1 -1
View File
@@ -1,7 +1,7 @@
README
^^^^^^
This directory contains the audio subsytem support for NuttX. The contents of this
This directory contains the audio subsystem support for NuttX. The contents of this
directory are only built if CONFIG_AUDIO is defined in the NuttX configuration file.
Contents
binfmt/Kconfig
+1 -1
View File
@@ -4,7 +4,7 @@
#
config BINFMT_DISABLE
bool "Disble BINFMT support"
bool "Disable BINFMT support"
default n
---help---
By default, support for loadable binary formats is built. This logic
configs/Kconfig
+4 -4
View File
@@ -61,7 +61,7 @@ config ARCH_BOARD_C5471EVM
This port is complete and verified.
config ARCH_BOARD_CLICKER2_STM32
bool "Mikrow Clicker2 STM32"
bool "Mikroe Clicker2 STM32"
depends on ARCH_CHIP_STM32F407VG
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
@@ -289,7 +289,7 @@ config ARCH_BOARD_IMXRT1050_EVK
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
This is the board configuratino for the port of NuttX to the NXP i.MXRT
This is the board configuration for the port of NuttX to the NXP i.MXRT
evaluation kit, MIMXRT1050-EVKB. This board features the MIMXRT1052DVL6A MCU.
config ARCH_BOARD_LC823450_XGEVK
@@ -669,7 +669,7 @@ config ARCH_BOARD_OLIMEXINO_STM32
This port uses the Olimexino STM32 board and a GNU arm-nuttx-elf
toolchain under Linux or Cygwin. See the http://www.olimex.com for
further information. This board features the STMicro STM32F103RBT6 MCU.
Contribued by David Sidrane.
Contributed by David Sidrane.
config ARCH_BOARD_OPEN1788
bool "Wave Share Open1788"
@@ -1519,7 +1519,7 @@ config ARCH_BOARD_Z16F2800100ZCOG
depends on ARCH_CHIP_Z16F2811
select ARCH_HAVE_LEDS
---help---
z16f Microcontroller. This port use the ZiLIG z16f2800100zcog
z16f Microcontroller. This port uses the ZiLOG z16f2800100zcog
development kit and the Zilog ZDS-II Windows command line tools. The
development environment is Cygwin under WinXP.
configs/README.txt
+1 -1
View File
@@ -496,7 +496,7 @@ configs/olimex-stm32-p407
configs/olimexino-stm32
This port uses the Olimexino STM32 board (STM32F103RBT6) and a GNU arm-nuttx-elf
toolchain* under Linux or Cygwin. See the http://www.olimex.com for further\
information. Contribued by David Sidrane.
information. Contributed by David Sidrane.
configs/olimex-strp711
This port uses the Olimex STR-P711 board and a GNU arm-nuttx-elf toolchain* under
configs/esp32-core/Kconfig
+1 -1
View File
@@ -32,7 +32,7 @@ config ESP32CORE_RUN_IRAM
mapping code to run from SPI flash after initial boot. There are at
least two possible approaches you could take: You can add the flash
cache mapping code into nuttx directly, so it is self-contained -
early nuttx initialisation runs from IRAM and enables flash cache,
early nuttx initialization runs from IRAM and enables flash cache,
and then off you go. Or you can use the esp-idf software bootloader
and partition table scheme and have nuttx be an esp-idf "app" which
allows interoperability with the esp-idf system but makes you
configs/freedom-kl25z/src/kl_adxl345.c
+1 -1
View File
@@ -153,7 +153,7 @@ static struct kl_adxl345config_s g_adxl345config =
/****************************************************************************
* Private Functions
****************************************************************************/
/* This is the ADXL345 Interupt handler */
/* This is the ADXL345 Interrupt handler */
int adxl345_interrupt(int irq, FAR void *context)
{
configs/mirtoo/README.txt
+1 -1
View File
@@ -952,7 +952,7 @@ Where <subdir> is one of the following:
NOTES:
a) It takes many seconds to boot the sytem using the NXFFS
a) It takes many seconds to boot the system using the NXFFS
file system because the entire FLASH must be verified on power up
(and longer the first time that NXFFS comes up and has to format the
entire FLASH).
configs/nucleo-144/scripts/f722-flash.ld
+1 -1
View File
@@ -52,7 +52,7 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified NUCLEO-144
* NuttX does not modify these option bytes. On the unmodified NUCLEO-144
* board, the BOOT0 pin is at ground so by default, the STM32F722ZE will
* boot from address 0x0020:0000 in ITCM FLASH.
*
configs/nucleo-144/scripts/f746-flash.ld
+1 -1
View File
@@ -50,7 +50,7 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified NUCLEO-144
* NuttX does not modify these option bytes. On the unmodified NUCLEO-144
* board, the BOOT0 pin is at ground so by default, the STM32F746ZGT6 will
* boot from address 0x0020:0000 in ITCM FLASH.
*
configs/nucleo-144/scripts/f767-flash.ld
+1 -1
View File
@@ -50,7 +50,7 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified NUCLEO-144
* NuttX does not modify these option bytes. On the unmodified NUCLEO-144
* board, the BOOT0 pin is at ground so by default, the STM32F767ZIT6 will
* boot from address 0x0020:0000 in ITCM FLASH.
*
configs/nucleo-144/scripts/memory.ld
+1 -1
View File
@@ -49,7 +49,7 @@
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
* ST programmed value: System bootloader at 0x0010:0000
*
* NuttX does not modify these option byes. On the unmodified STM32F746G
* NuttX does not modify these option bytes. On the unmodified STM32F746G
* DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
* to address 0x0020:0000 in ITCM FLASH.
*
configs/nucleo-h743zi/scripts/flash.ld
+1 -1
View File
@@ -60,7 +60,7 @@
*
* TODO: Check next paragraph with nucleo schematics
*
* NuttX does not modify these option byes. On the unmodified NUCLEO-H743ZI
* NuttX does not modify these option bytes. On the unmodified NUCLEO-H743ZI
* board, the BOOT0 pin is at ground so by default, the STM32 will boot
* to address 0x0800:0000 in FLASH.
*

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