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Add PHY setup for STM3240G-EVAL Ethernet driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4151 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-12-09 17:03:16 +00:00
parent 0166e09b5b
commit 27a51442d7
4 changed files with 515 additions and 36 deletions
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arch/arm/src/stm32/chip/stm32_eth.h
+11 -3
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@@ -245,10 +245,18 @@
#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */
#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */
#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT)
# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
#if 0 /* Per the reference manual */
# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */
# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
#else /* Per the driver example */
# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
# define ETH_MACMIIAR_CR_150_168 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-168 MHz HCLK/102 */
#endif
#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */
#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT)
#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */
arch/arm/src/stm32/stm32_eth.c
+493 -30
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32f40xxx_rcc.c
+8 -2
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@@ -184,8 +184,14 @@ static inline void rcc_enableahb1(void)
#ifdef CONFIG_STM32_ETHMAC
/* Ethernet MAC clocking */
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|
RCC_AHB1ENR_ETHMACRXEN|RCC_AHB1ENR_ETHMACPTPEN);
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
#ifdef CONFIG_STM32_ETH_PTP
/* Precision Time Protocol (PTP) */
regval |= RCC_AHB1ENR_ETHMACPTPEN;
#endif
#endif
#ifdef CONFIG_STM32_OTGHS
arch/mips/src/pic32mx/pic32mx-head.S
+3 -1
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@@ -161,7 +161,9 @@ __reset:
* Name: _gen_exception
*
* Description:
* General Exception Vector Handler. Jumps to _exception_handler
* General Exception Vector Handler. Jumps to _exception_handler. NOTE:
* we set the BEV bit in the status register so all interrupt vectors
* should go through the _bev_exception.
*
* Input Parameters:
* None