mirror of
https://github.com/apache/nuttx.git
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arch/arm/src/stm32l4: Add initial support to STM32L4+ chips
This commit is contained in:
Juha Niskanen
committed by
Gregory Nutt
Gregory Nutt
parent
45e61f1138
commit
2589fc943e
@@ -78,7 +78,11 @@
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* selection.
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*/
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#if defined(CONFIG_STM32L4_STM32L496XX)
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \
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@@ -99,6 +103,37 @@
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# error "Unsupported STM32L4 chip"
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#endif
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 0 /* No QuadSPI1 */
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# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NSWPMI 0 /* No SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4XR */
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#if defined(CONFIG_STM32L4_STM32L4X5)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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@@ -82,6 +82,8 @@
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# include <arch/stm32l4/stm32l4x5xx_irq.h>
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#elif defined(CONFIG_STM32L4_STM32L4X6)
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# include <arch/stm32l4/stm32l4x6xx_irq.h>
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#elif defined(CONFIG_STM32L4_STM32L4XR)
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# include <arch/stm32l4/stm32l4xrxx_irq.h>
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#else
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# error "Unsupported STM32 L4 chip"
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#endif
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@@ -55,7 +55,7 @@
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
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* nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
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*
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* External interrupts (vectors >= 16)
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*/
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@@ -53,7 +53,7 @@
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
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* nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
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*
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* External interrupts (vectors >= 16)
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*/
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@@ -0,0 +1,193 @@
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/****************************************************************************************************
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* arch/arm/include/stm32l4/stm32l4xrxx_irq.h
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*
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* Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
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* Author: Sebastien Lorquet <sebastien@lorquet.fr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
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#ifndef __ARCH_ARM_INCLUDE_STM32L4_STM32L4XRXX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32L4_STM32L4XRXX_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32l4/irq.h which includes this file.
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*
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* External interrupts (vectors >= 16)
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*/
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#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
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#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
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#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
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#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
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#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
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#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
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#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
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#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
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#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
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#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
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#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
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#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
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#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
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#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
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#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
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#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
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#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
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#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
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#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
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#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
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#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
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#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
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#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
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#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
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#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
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#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
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#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
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#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
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#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
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#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
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#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
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#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
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#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
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#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
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#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
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#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
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#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
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#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
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#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
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#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
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#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
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#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
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#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
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#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
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#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
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#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
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/* Reserved */ /* 47: ADC3 global interrupt */
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#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
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#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
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#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
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#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
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#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
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#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
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#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
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#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
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#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
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#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
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#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
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#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
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#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
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#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
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#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
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#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
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#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
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#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
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#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
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#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
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#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
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#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
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#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
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#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
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#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */
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#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
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#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
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#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
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#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
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#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */
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#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
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#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */
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#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
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#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
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#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
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#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
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#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
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#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
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#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
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/* Reserved */ /* 86-89: CAN2 */
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#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
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#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */
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#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */
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#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */
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#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
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#define STM32L4_IRQ_NEXTINTS 95
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/* EXTI interrupts (Do not use IRQ numbers) */
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#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32L4_STM32L4XRXX_IRQ_H */
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@@ -420,6 +420,14 @@ config ARCH_CHIP_STM32L4A6AG
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---help---
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STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM
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config ARCH_CHIP_STM32L4R9AI
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bool "STM32L4R9AI"
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select STM32L4_STM32L4R9XX
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select STM32L4_FLASH_CONFIG_I
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select STM32L4_IO_CONFIG_A
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---help---
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STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM
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endchoice # STM32 L4 Chip Selection
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# Chip product lines
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@@ -487,6 +495,7 @@ config STM32L4_STM32L4X5
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select STM32L4_HAVE_SDMMC1
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select STM32L4_HAVE_OTGFS
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select STM32L4_HAVE_DFSDM1
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select STM32L4_HAVE_QSPI
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||||
|
||||
config STM32L4_STM32L4X6
|
||||
# STM32L4x6 (documented in RM0351)
|
||||
@@ -516,6 +525,37 @@ config STM32L4_STM32L4X6
|
||||
select STM32L4_HAVE_SDMMC1
|
||||
select STM32L4_HAVE_OTGFS
|
||||
select STM32L4_HAVE_LCD
|
||||
select STM32L4_HAVE_QSPI
|
||||
|
||||
config STM32L4_STM32L4XR
|
||||
# STM32L4+ (documented in RM0432)
|
||||
bool
|
||||
default n
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32L4_HAVE_USART1
|
||||
select STM32L4_HAVE_USART2
|
||||
select STM32L4_HAVE_USART3
|
||||
select STM32L4_HAVE_UART4
|
||||
select STM32L4_HAVE_UART5
|
||||
select STM32L4_HAVE_ADC2
|
||||
select STM32L4_HAVE_DAC2
|
||||
select STM32L4_HAVE_FSMC
|
||||
select STM32L4_HAVE_TIM3
|
||||
select STM32L4_HAVE_TIM4
|
||||
select STM32L4_HAVE_TIM5
|
||||
select STM32L4_HAVE_TIM7
|
||||
select STM32L4_HAVE_TIM8
|
||||
select STM32L4_HAVE_TIM17
|
||||
select STM32L4_HAVE_LPTIM1
|
||||
select STM32L4_HAVE_LPTIM2
|
||||
select STM32L4_HAVE_COMP
|
||||
select STM32L4_HAVE_SAI1
|
||||
select STM32L4_HAVE_SAI2
|
||||
select STM32L4_HAVE_SDMMC1
|
||||
select STM32L4_HAVE_OTGFS
|
||||
select STM32L4_HAVE_I2C4
|
||||
select STM32L4_HAVE_DCMI
|
||||
select STM32L4_HAVE_DFSDM1
|
||||
|
||||
# Chip subfamilies:
|
||||
|
||||
@@ -627,6 +667,48 @@ config STM32L4_STM32L4A6XX
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
config STM32L4_STM32L4R5XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
|
||||
config STM32L4_STM32L4S5XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
config STM32L4_STM32L4R7XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
|
||||
config STM32L4_STM32L4S7XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
config STM32L4_STM32L4R9XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
select STM32L4_HAVE_LTDC
|
||||
|
||||
config STM32L4_STM32L4S9XX
|
||||
bool
|
||||
default n
|
||||
select STM32L4_STM32L4XR
|
||||
select STM32L4_HAVE_DMA2D
|
||||
select STM32L4_HAVE_LTDC
|
||||
select STM32L4_HAVE_AES
|
||||
select STM32L4_HAVE_HASH
|
||||
|
||||
choice
|
||||
prompt "Override Flash Size Designator"
|
||||
depends on ARCH_CHIP_STM32L4
|
||||
@@ -640,6 +722,7 @@ choice
|
||||
C 256
|
||||
E 512
|
||||
G 1024
|
||||
I 2048
|
||||
|
||||
This configuration option defaults to using the configuration based on that designator
|
||||
or the default smaller size if there is no last character designator is present in the
|
||||
@@ -668,6 +751,9 @@ config STM32L4_FLASH_OVERRIDE_E
|
||||
config STM32L4_FLASH_OVERRIDE_G
|
||||
bool "G 1024 KB"
|
||||
|
||||
config STM32L4_FLASH_OVERRIDE_I
|
||||
bool "I 2048 KB"
|
||||
|
||||
endchoice # "Override Flash Size Designator"
|
||||
|
||||
# Flash configurations
|
||||
@@ -691,6 +777,11 @@ config STM32L4_FLASH_CONFIG_G
|
||||
default n
|
||||
depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6
|
||||
|
||||
config STM32L4_FLASH_CONFIG_I
|
||||
bool
|
||||
default n
|
||||
depends on STM32L4_STM32L4XR
|
||||
|
||||
# Pin/package configurations
|
||||
|
||||
config STM32L4_IO_CONFIG_K
|
||||
@@ -893,6 +984,10 @@ config STM32L4_HAVE_UART5
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32L4_HAVE_QSPI
|
||||
bool
|
||||
default n
|
||||
|
||||
# These "hidden" settings are the OR of individual peripheral selections
|
||||
# indicating that the general capability is required.
|
||||
|
||||
@@ -1024,6 +1119,7 @@ config STM32L4_FSMC
|
||||
config STM32L4_QSPI
|
||||
bool "QuadSPI"
|
||||
default n
|
||||
depends on STM32L4_HAVE_QSPI
|
||||
---help---
|
||||
The STM32L4 QSPI block is intended to support one serial NOR flash device
|
||||
|
||||
|
||||
@@ -8,7 +8,7 @@ Most code is copied and adapted from the STM32 and STM32F7 ports.
|
||||
|
||||
The various supported STM32L4 families are:
|
||||
|
||||
-------------------------------------------------------------
|
||||
-----------------------------------------------------------------
|
||||
| NuttX config | Manual | Chips
|
||||
|
|
||||
| Not supported | RM0392 | STM32L471xx
|
||||
@@ -24,8 +24,8 @@ The various supported STM32L4 families are:
|
||||
| STM32L4_STM32L4X6 | RM0351 | STM32L476xx, STM32L486xx,
|
||||
| STM32L496xx, STM32L4A6xx
|
||||
|
|
||||
| Not supported | RM0432 | STM32L4Rxxx, STM32L4Sxxx
|
||||
-------------------------------------------------------------
|
||||
| STM32L4_STM32L4XR | RM0432 | STM32L4Rxxx, STM32L4Sxxx (STM32L4+)
|
||||
------------------------------------------------------------------
|
||||
|
||||
[*]: Please avoid depending on CONFIG_STM32L4_STM32L4X1 and
|
||||
CONFIG_STM32L4_STM32L4X2 as the MCUs are of the same subfamily
|
||||
@@ -91,3 +91,13 @@ SAIPLL : works (PLL For Digital Audio interfaces, and other things)
|
||||
SAI : There is some code (Digital Audio interfaces, I2S, SPDIF, etc)
|
||||
HASH : TODO (SHA-1, SHA-224, SHA-256, HMAC)
|
||||
DCMI : TODO (Digital Camera interfaces)
|
||||
|
||||
New peripherals only in STM32L4+:
|
||||
|
||||
DMAMUX1 : TODO
|
||||
DSI : TODO
|
||||
GFXMMU : TODO
|
||||
LTDC : TODO
|
||||
OCTOSPI : TODO
|
||||
OCTOSPIIOM : TODO
|
||||
|
||||
|
||||
@@ -67,10 +67,12 @@
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_G)
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_G) && \
|
||||
!defined(CONFIG_STM32L4_FLASH_CONFIG_I)
|
||||
# define CONFIG_STM32L4_FLASH_OVERRIDE_E
|
||||
# warning "Flash size not defined defaulting to 512KiB (E)"
|
||||
#endif
|
||||
@@ -82,6 +84,7 @@
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_C
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_E
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_G
|
||||
# undef CONFIG_STM32L4_FLASH_CONFIG_I
|
||||
# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_B
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C)
|
||||
@@ -90,6 +93,8 @@
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_E
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_G
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_I)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_I
|
||||
# endif
|
||||
#endif
|
||||
|
||||
@@ -107,6 +112,9 @@
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB */
|
||||
# define STM32L4_FLASH_NPAGES 256
|
||||
# define STM32L4_FLASH_PAGESIZE 8192
|
||||
#else
|
||||
# error "unknown flash configuration!"
|
||||
#endif
|
||||
@@ -129,7 +137,7 @@
|
||||
#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c
|
||||
@@ -150,7 +158,7 @@
|
||||
#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET)
|
||||
@@ -205,7 +213,7 @@
|
||||
#define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT)
|
||||
#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */
|
||||
# define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */
|
||||
#endif
|
||||
@@ -223,7 +231,7 @@
|
||||
|
||||
#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 8-15: Read protect */
|
||||
#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */
|
||||
#endif
|
||||
#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
|
||||
@@ -240,14 +248,14 @@
|
||||
#define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
|
||||
#define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
|
||||
#define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */
|
||||
# define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */
|
||||
#endif
|
||||
#define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
|
||||
#define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
|
||||
#define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
|
||||
# define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
|
||||
#endif
|
||||
|
||||
@@ -43,7 +43,7 @@
|
||||
/* STM32L4XXX Address Blocks ********************************************************/
|
||||
|
||||
#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (96k or 256k) */
|
||||
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
@@ -53,6 +53,8 @@
|
||||
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
|
||||
#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0000000-0xbfffffff: QSPI register block */
|
||||
#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
|
||||
#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xbfffffff: OCTOSPI2 register block */
|
||||
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
|
||||
#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
|
||||
@@ -66,8 +68,9 @@
|
||||
/* 0x00100000-0x07ffffff: Reserved */
|
||||
#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
|
||||
/* 0x08100000-0x0fffffff: Reserved */
|
||||
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 32Kb or 64Kb SRAM2 */
|
||||
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */
|
||||
/* 0x10010000-0x1ffeffff: Reserved */
|
||||
#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */
|
||||
#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
|
||||
#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
@@ -161,6 +164,8 @@
|
||||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32L4_DSI_BASE 0x40016c00
|
||||
#define STM32L4_LTDC_BASE 0x40016800
|
||||
#define STM32L4_DFSDM_BASE 0x40016000
|
||||
#define STM32L4_SAI2_BASE 0x40015800
|
||||
#define STM32L4_SAI1_BASE 0x40015400
|
||||
@@ -171,7 +176,9 @@
|
||||
#define STM32L4_TIM8_BASE 0x40013400
|
||||
#define STM32L4_SPI1_BASE 0x40013000
|
||||
#define STM32L4_TIM1_BASE 0x40012c00
|
||||
#define STM32L4_SDMMC1_BASE 0x40012800
|
||||
#ifndef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x40012800
|
||||
#endif
|
||||
#define STM32L4_FIREWALL_BASE 0x40011c00
|
||||
#define STM32L4_EXTI_BASE 0x40010400
|
||||
#define STM32L4_COMP_BASE 0x40010200
|
||||
@@ -180,16 +187,22 @@
|
||||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32L4_GFXMMU_BASE 0x4002c000
|
||||
#define STM32L4_DMA2D_BASE 0x4002b000
|
||||
#define STM32L4_TSC_BASE 0x40024000
|
||||
#define STM32L4_CRC_BASE 0x40023000
|
||||
#define STM32L4_FLASHIF_BASE 0x40022000
|
||||
#define STM32L4_RCC_BASE 0x40021000
|
||||
#define STM32L4_DMAMUX1_BASE 0x40020800
|
||||
#define STM32L4_DMA2_BASE 0x40020400
|
||||
#define STM32L4_DMA1_BASE 0x40020000
|
||||
|
||||
/* AHB2 Base Addresses **************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x50062400
|
||||
#endif
|
||||
#define STM32L4_OCTOSPIIOM_BASE 0x50061c00
|
||||
#define STM32L4_RNG_BASE 0x50060800
|
||||
#define STM32L4_HASH_BASE 0x50060400
|
||||
#define STM32L4_AES_BASE 0x50060000
|
||||
|
||||
@@ -50,6 +50,8 @@
|
||||
# include "chip/stm32l4x5xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported STM32 L4 pin map"
|
||||
#endif
|
||||
|
||||
@@ -49,6 +49,8 @@
|
||||
# include "chip/stm32l4x5xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_syscfg.h"
|
||||
#else
|
||||
# error "Unsupported STM32 L4 chip"
|
||||
#endif
|
||||
|
||||
@@ -54,7 +54,7 @@
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
@@ -73,27 +73,27 @@
|
||||
|
||||
/* Code Segment Start Address */
|
||||
#define FIREWALL_CSSADD_SHIFT 8
|
||||
#define FIREWALL_CSSADD_MASK (0xFFFF << FIREWALL_CSSADD_SHIFT)
|
||||
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
|
||||
|
||||
/* Code Segment Length */
|
||||
#define FIREWALL_CSSLENG_SHIFT 8
|
||||
#define FIREWALL_CSSLENG_MASK (0x3FFF << FIREWALL_CSSLENG_SHIFT)
|
||||
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Start Address */
|
||||
#define FIREWALL_NVDSADD_SHIFT 8
|
||||
#define FIREWALL_NVDSADD_MASK (0xFFFF << FIREWALL_NVDSADD_SHIFT)
|
||||
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Length */
|
||||
#define FIREWALL_NVDSLENG_SHIFT 8
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3FFF << FIREWALL_NVDSLENG_SHIFT)
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Start Address */
|
||||
#define FIREWALL_VDSADD_SHIFT 6
|
||||
#define FIREWALL_VDSADD_MASK (0x07FF << FIREWALL_VDSADD_SHIFT)
|
||||
#define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Length */
|
||||
#define FIREWALL_VDSLENG_SHIFT 6
|
||||
#define FIREWALL_VDSLENG_MASK (0x07FF << FIREWALL_VDSLENG_SHIFT)
|
||||
#define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT)
|
||||
|
||||
/* Configuration Register */
|
||||
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
|
||||
|
||||
@@ -243,14 +243,14 @@
|
||||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
@@ -262,7 +262,7 @@
|
||||
|
||||
#define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21)
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21) /* Bits 21-22: Main PLL division factor for PLL48M1CLK (48 MHz clock) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
|
||||
@@ -272,7 +272,7 @@
|
||||
|
||||
#define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25)
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25) /* Bits 25-26: Main PLL division factor for PLLCLK (system clock) */
|
||||
#define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
|
||||
@@ -56,7 +56,7 @@
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
@@ -231,12 +231,12 @@
|
||||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLSAI3CLK output enable */
|
||||
|
||||
@@ -54,7 +54,7 @@
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000C
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
@@ -74,39 +74,39 @@
|
||||
/* Code Segment Start Address */
|
||||
|
||||
#define FIREWALL_CSSADD_SHIFT 8
|
||||
#define FIREWALL_CSSADD_MASK (0xFFFF << FIREWALL_CSSADD_SHIFT)
|
||||
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
|
||||
|
||||
/* Code Segment Length */
|
||||
|
||||
#define FIREWALL_CSSLENG_SHIFT 8
|
||||
#define FIREWALL_CSSLENG_MASK (0x3FFF << FIREWALL_CSSLENG_SHIFT)
|
||||
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_NVDSADD_SHIFT 8
|
||||
#define FIREWALL_NVDSADD_MASK (0xFFFF << FIREWALL_NVDSADD_SHIFT)
|
||||
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_NVDSLENG_SHIFT 8
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3FFF << FIREWALL_NVDSLENG_SHIFT)
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_VDSADD_SHIFT 6
|
||||
#if defined(CONFIG_STM32L4_STM32L496XX)
|
||||
#define FIREWALL_VDSADD_MASK (0x0FFF << FIREWALL_VDSADD_SHIFT)
|
||||
# define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT)
|
||||
#else
|
||||
#define FIREWALL_VDSADD_MASK (0x07FF << FIREWALL_VDSADD_SHIFT)
|
||||
# define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_VDSLENG_SHIFT 6
|
||||
#if defined(CONFIG_STM32L4_STM32L496XX)
|
||||
#define FIREWALL_VDSLENG_MASK (0x0FFF << FIREWALL_VDSLENG_SHIFT)
|
||||
# define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT)
|
||||
#else
|
||||
#define FIREWALL_VDSLENG_MASK (0x07FF << FIREWALL_VDSLENG_SHIFT)
|
||||
# define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Configuration Register */
|
||||
|
||||
@@ -244,14 +244,14 @@
|
||||
#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT)
|
||||
# define RCC_PLLCFG_PLLSRC_NONE (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 000: No clock sent to PLLs */
|
||||
# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: MSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 001: HSE selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 010: HSI selected as PLL source */
|
||||
# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 011: HSE selected as PLL source */
|
||||
|
||||
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL (PLL) input clock divider */
|
||||
#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
|
||||
# define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* m = 1..8 */
|
||||
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 6-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
|
||||
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
|
||||
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
@@ -263,7 +263,7 @@
|
||||
|
||||
#define RCC_PLLCFG_PLLQEN (1 << 20) /* Bit 20: Main PLL PLL48M1CLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21)
|
||||
#define RCC_PLLCFG_PLLQ_SHIFT (21) /* Bits 21-22: Main PLL division factor for PLL48M1CLK (48 MHz clock) */
|
||||
#define RCC_PLLCFG_PLLQ_MASK (3 << RCC_PLLCFG_PLLQ_SHIFT)
|
||||
# define RCC_PLLCFG_PLLQ(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLQ_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLQ_2 (0 << RCC_PLLCFG_PLLQ_SHIFT) /* 00: PLLQ = 2 */
|
||||
@@ -273,7 +273,7 @@
|
||||
|
||||
#define RCC_PLLCFG_PLLREN (1 << 24) /* Bit 24: Main PLL PLLCLK output enable */
|
||||
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25)
|
||||
#define RCC_PLLCFG_PLLR_SHIFT (25) /* Bits 25-26: Main PLL division factor for PLLCLK (system clock) */
|
||||
#define RCC_PLLCFG_PLLR_MASK (3 << RCC_PLLCFG_PLLR_SHIFT)
|
||||
# define RCC_PLLCFG_PLLR(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLR_SHIFT) /* n=2,4,6,8 */
|
||||
# define RCC_PLLCFG_PLLR_2 (0 << RCC_PLLCFG_PLLR_SHIFT) /* 00: PLLR = 2 */
|
||||
@@ -285,7 +285,7 @@
|
||||
|
||||
/* PLLSAI1 Configuration register */
|
||||
|
||||
#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI1 PLL (PLLSAI1) VCO multiplier */
|
||||
#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI1 PLL (PLLSAI1) VCO multiplier */
|
||||
#define RCC_PLLSAI1CFG_PLLN_MASK (0x7f << RCC_PLLSAI1CFG_PLLN_SHIFT)
|
||||
# define RCC_PLLSAI1CFG_PLLN(n) ((n) << RCC_PLLSAI1CFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
@@ -317,7 +317,7 @@
|
||||
|
||||
/* PLLSAI2 Configuration register */
|
||||
|
||||
#define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 6-14: SAI2 PLL (PLLSAI2) VCO multiplier */
|
||||
#define RCC_PLLSAI2CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI2 PLL (PLLSAI2) VCO multiplier */
|
||||
#define RCC_PLLSAI2CFG_PLLN_MASK (0x7f << RCC_PLLSAI2CFG_PLLN_SHIFT)
|
||||
# define RCC_PLLSAI2CFG_PLLN(n) ((n) << RCC_PLLSAI2CFG_PLLN_SHIFT) /* n = 8..86 */
|
||||
|
||||
@@ -754,7 +754,7 @@
|
||||
#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */
|
||||
#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */
|
||||
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 8-9: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
@@ -800,7 +800,7 @@
|
||||
|
||||
/* Peripheral Independent Clock Configuration 2 register (only on STM32L496xx/4A6xx) */
|
||||
|
||||
#define RCC_CCIPR2_I2C4SEL_SHIFT (0)
|
||||
#define RCC_CCIPR2_I2C4SEL_SHIFT (0) /* Bits 0-1: I2C4 clock source selection */
|
||||
#define RCC_CCIPR2_I2C4SEL_MASK (3 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_PCLK (0 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
# define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT)
|
||||
|
||||
@@ -0,0 +1,113 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Juha Niskanen <juha.niskanen@haltian.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DBGMCU_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DBGMCU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
|
||||
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
|
||||
#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
|
||||
#define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze register 2 */
|
||||
#define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* MCU identifier */
|
||||
|
||||
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
|
||||
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
|
||||
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
|
||||
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
|
||||
|
||||
/* MCU debug */
|
||||
|
||||
#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */
|
||||
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */
|
||||
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */
|
||||
#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */
|
||||
|
||||
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
|
||||
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
|
||||
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
|
||||
#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
|
||||
#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
|
||||
#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
|
||||
|
||||
/* Debug MCU APB1 freeze register */
|
||||
|
||||
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
|
||||
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
|
||||
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
|
||||
#define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */
|
||||
|
||||
/* Debug MCU APB1 freeze register 2 */
|
||||
|
||||
#define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopper when core is halted */
|
||||
|
||||
/* Debug MCU APB2 freeze register */
|
||||
|
||||
#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXXDBGMCU_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
|
||||
*
|
||||
* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
|
||||
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Code Segment Start Address */
|
||||
|
||||
#define FIREWALL_CSSADD_SHIFT 8
|
||||
#define FIREWALL_CSSADD_MASK (0xffff << FIREWALL_CSSADD_SHIFT)
|
||||
|
||||
/* Code Segment Length */
|
||||
|
||||
#define FIREWALL_CSSLENG_SHIFT 8
|
||||
#define FIREWALL_CSSLENG_MASK (0x3fff << FIREWALL_CSSLENG_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_NVDSADD_SHIFT 8
|
||||
#define FIREWALL_NVDSADD_MASK (0xffff << FIREWALL_NVDSADD_SHIFT)
|
||||
|
||||
/* Non-volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_NVDSLENG_SHIFT 8
|
||||
#define FIREWALL_NVDSLENG_MASK (0x3fff << FIREWALL_NVDSLENG_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Start Address */
|
||||
|
||||
#define FIREWALL_VDSADD_SHIFT 6
|
||||
#define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT)
|
||||
|
||||
/* Volatile Data Segment Length */
|
||||
|
||||
#define FIREWALL_VDSLENG_SHIFT 6
|
||||
#define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT)
|
||||
|
||||
/* Configuration Register */
|
||||
|
||||
#define FIREWALL_CR_FPA (1 << 0) /* Bit 0: Firewall prearm */
|
||||
#define FIREWALL_CR_VDS (1 << 1) /* Bit 1: Volatile data shared */
|
||||
#define FIREWALL_CR_VDE (1 << 2) /* Bit 2: Volatile data execution */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,193 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2014-2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2:0 MEM_MODE: Memory mapping selection */
|
||||
#define SYSCFG_MEMRMP_MASK (7 << SYSCFG_MEMRMP_SHIFT)
|
||||
# define SYSCFG_MEMRMP_FLASH (0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SYSTEM (1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_FMC (2 << SYSCFG_MEMRMP_SHIFT) /* 010: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_SRAM (3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_OCTOSPI1 (4 << SYSCFG_MEMRMP_SHIFT) /* 100: OCTOSPI1 mapped at 0x0000 0000 */
|
||||
# define SYSCFG_MEMRMP_OCTOSPI2 (5 << SYSCFG_MEMRMP_SHIFT) /* 101: OCTOSPI2 mapped at 0x0000 0000 */
|
||||
#define SYSCFG_FBMODE (1 << 8) /* Bit 8: Flash Bank mode selection */
|
||||
|
||||
/* SYSCFG configuration register 1 */
|
||||
|
||||
#define SYSCFG_CFGR1_FWDIS (1 << 0) /* Bit 0: Firewall disable */
|
||||
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
|
||||
#define SYSCFG_CFGR1_ANASWVDD (1 << 9) /* Bit 9: GPIO analog switch control voltage selection */
|
||||
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
|
||||
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
|
||||
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
|
||||
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
|
||||
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
|
||||
#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
|
||||
#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* SYSCFG SRAM2 control and status register */
|
||||
|
||||
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
|
||||
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
|
||||
|
||||
/* SYSCFG configuration register 2 */
|
||||
|
||||
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable (TIMx break enable, see refman) */
|
||||
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable (same) */
|
||||
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable (same) */
|
||||
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */
|
||||
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
|
||||
|
||||
/* SYSCFG SRAM2 write protection register */
|
||||
/* There is one bit per SRAM2 page (0 to 31) */
|
||||
|
||||
/* SYSCFG SRAM2 key register */
|
||||
|
||||
#define SYSCFG_SKR_SHIFT 0
|
||||
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
|
||||
|
||||
/* SYSCFG SRAM2 write protection register 2 */
|
||||
/* There is one bit per SRAM2 page (32 to 63) */
|
||||
|
||||
#endif /* CONFIG_STM32L4_STM32L4XR */
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H */
|
||||
@@ -76,12 +76,12 @@
|
||||
#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \
|
||||
defined(CONFIG_STM32L4_ADC3)
|
||||
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6))
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR))
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# if defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3)
|
||||
# error "Using non-existent ADC"
|
||||
# endif
|
||||
@@ -105,7 +105,7 @@
|
||||
|
||||
/* ADC interrupts ***********************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1
|
||||
#endif
|
||||
|
||||
|
||||
@@ -98,6 +98,12 @@
|
||||
* 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000
|
||||
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
|
||||
*
|
||||
* STM32L4Rxxx have 640 Kib in three banks:
|
||||
*
|
||||
* 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000
|
||||
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
|
||||
* 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000
|
||||
*
|
||||
* In addition, external FSMC SRAM may be available.
|
||||
*/
|
||||
|
||||
@@ -111,6 +117,21 @@
|
||||
#define SRAM2_START STM32L4_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE)
|
||||
|
||||
/* Set the range of SRAM3, requiring a third memory region */
|
||||
|
||||
#ifdef STM32L4_SRAM3_SIZE
|
||||
# define SRAM3_START STM32L4_SRAM3_BASE
|
||||
# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE)
|
||||
# define CONFIG_STM32L4_SRAM3_HEAP
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SRAM3_HEAP)
|
||||
/* TODO: better check here */
|
||||
# if CONFIG_MM_REGIONS < 3
|
||||
# error you need at least 3 memory manager regions to support SRAM2 and SRAM3
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP)
|
||||
# if CONFIG_MM_REGIONS < 3
|
||||
# error you need at least 3 memory manager regions to support SRAM2 and FSMC
|
||||
@@ -328,8 +349,28 @@ void up_addregion(void)
|
||||
|
||||
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
|
||||
|
||||
#endif /* SRAM2 */
|
||||
|
||||
#ifdef CONFIG_STM32L4_SRAM3_HEAP
|
||||
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
/* Allow user-mode access to the SRAM3 heap */
|
||||
|
||||
stm32l4_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END-SRAM3_START);
|
||||
|
||||
#endif
|
||||
|
||||
/* Colorize the heap for debug */
|
||||
|
||||
up_heap_color((FAR void *)SRAM3_START, SRAM3_END-SRAM3_START);
|
||||
|
||||
/* Add the SRAM2 user heap region. */
|
||||
|
||||
kumm_addregion((FAR void *)SRAM3_START, SRAM3_END-SRAM3_START);
|
||||
|
||||
#endif /* SRAM3 */
|
||||
|
||||
#ifdef CONFIG_STM32L4_FSMC_SRAM_HEAP
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
|
||||
|
||||
|
||||
@@ -140,6 +140,7 @@
|
||||
# else
|
||||
# error "No DMA channel for DAC1"
|
||||
# endif
|
||||
# define HAVE_DMA
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_DAC2_DMA
|
||||
# if defined(CONFIG_STM32L4_DMA1)
|
||||
@@ -149,8 +150,8 @@
|
||||
# else
|
||||
# error "No DMA channel for DAC2"
|
||||
# endif
|
||||
# define HAVE_DMA
|
||||
#endif
|
||||
#define HAVE_DMA
|
||||
|
||||
/* Timer configuration. The STM32L4 supports 8 different trigger for DAC
|
||||
* output:
|
||||
|
||||
@@ -51,6 +51,8 @@
|
||||
# include "chip/stm32l4x5xx_dbgmcu.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_dbgmcu.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_dbgmcu.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
@@ -49,8 +49,8 @@
|
||||
* TODO: do we need separate implementation for STM32L4X3?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
#include "stm32l4x6xx_dma.c"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
|
||||
@@ -55,6 +55,8 @@
|
||||
# include "chip/stm32l4x5xx_dma.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_dma.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_dma.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
@@ -53,6 +53,8 @@
|
||||
# include "chip/stm32l4x5xx_firewall.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_firewall.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_firewall.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
@@ -63,8 +63,8 @@
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6))
|
||||
#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR))
|
||||
# error "Unrecognized STM32 chip"
|
||||
#endif
|
||||
|
||||
@@ -85,7 +85,13 @@
|
||||
#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4)
|
||||
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
|
||||
#define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
|
||||
#if FLASH_PAGE_SIZE == 2048
|
||||
# define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
|
||||
#elif FLASH_PAGE_SIZE == 8192
|
||||
# define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */
|
||||
#else
|
||||
# error Unsupported STM32L4_FLASH_PAGESIZE
|
||||
#endif
|
||||
#define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT)
|
||||
|
||||
#define FLASH_CR_PAGE_ERASE FLASH_CR_PER
|
||||
|
||||
@@ -54,8 +54,8 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4_gpio.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
|
||||
@@ -85,6 +85,8 @@
|
||||
# include "stm32l4x5xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "stm32l4x6xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "stm32l4xrxx_rcc.c"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
@@ -51,6 +51,8 @@
|
||||
# include "chip/stm32l4x5xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# include "chip/stm32l4x6xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4xrxx_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
@@ -46,7 +46,7 @@
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6)
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# include "chip/stm32l4_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user