arch: k210: Applied changes doned for fe310 recently.

NOTE: In the future, these code should be moved under common code
once they support both RV32 & RV64 architectures.
This commit is contained in:
Masayuki Ishikawa
2020-01-09 20:47:16 +09:00
committed by Alan Carvalho de Assis
parent dc5d8f7c44
commit 255f3008cf
6 changed files with 32 additions and 20 deletions
+3 -1
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@@ -45,7 +45,9 @@
/* Machine Interrupt Enable bit in mstatus register */
#define MSTATUS_MIE (0x1 << 3)
#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
/* In mie (machine interrupt enable) register */
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/k210/k210_clockconfig.c
* arch/risc-v/src/k210/k210_clockconfig.c
*
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/k210/k210_clockconfig.h
* arch/risc-v/src/k210/k210_clockconfig.h
*
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
+7 -4
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@@ -103,7 +103,6 @@ void up_irqinitialize(void)
/* Attach the ecall interrupt handler */
irq_attach(K210_IRQ_ECALLM, up_swint, NULL);
up_enable_irq(K210_IRQ_ECALLM);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
@@ -191,13 +190,17 @@ void up_enable_irq(int irq)
* Name: up_get_newintctx
*
* Description:
* Return a value for EPIC. But K210 doesn't use EPIC for event control.
* Return initial mstatus when a task is created.
*
****************************************************************************/
uint32_t up_get_newintctx(void)
{
return 0;
/* Set machine previous privilege mode to machine mode.
* Also set machine previous interrupt enable
*/
return (MSTATUS_MPPM | MSTATUS_MPIE);
}
/****************************************************************************
@@ -240,7 +243,7 @@ irqstate_t up_irq_save(void)
void up_irq_restore(irqstate_t flags)
{
/* Machine mode - mstatus */
/* Write flags to mstatus */
asm volatile("csrw mstatus, %0" : /* no output */ : "r" (flags));
}
+19 -12
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@@ -68,12 +68,13 @@ void *k210_dispatch_irq(uint64_t vector, uint64_t *regs)
uint32_t irq = (vector >> (27 + 32)) | (vector & 0xf);
uint64_t *mepc = regs;
/* Firstly, check if the irq is machine external interrupt */
if (K210_IRQ_MEXT == irq)
{
/* Read & write K210_PLIC_CLAIM to clear pending */
uint32_t val = getreg32(K210_PLIC_CLAIM);
putreg32(val, K210_PLIC_CLAIM);
/* Add the value to nuttx irq which is offset to the mext */
irq += val;
}
@@ -85,22 +86,32 @@ void *k210_dispatch_irq(uint64_t vector, uint64_t *regs)
*mepc += 4;
}
/* Acknowledge the interrupt */
up_ack_irq(irq);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
/* Nested interrupts are not supported */
DEBUGASSERT(g_current_regs == NULL);
/* Current regs non-zero indicates that we are processing an interrupt;
* CURRENT_REGS is also used to manage interrupt level context switches.
* g_current_regs is also used to manage interrupt level context switches.
*
* Nested interrupts are not supported
*/
DEBUGASSERT(g_current_regs == NULL);
g_current_regs = regs;
/* Deliver the IRQ */
irq_dispatch(irq, regs);
if (K210_IRQ_MEXT <= irq)
{
/* Then write PLIC_CLAIM to clear pending in PLIC */
putreg32(irq - K210_IRQ_MEXT, K210_PLIC_CLAIM);
}
#endif
/* If a context switch occurred while processing the interrupt then
@@ -112,10 +123,6 @@ void *k210_dispatch_irq(uint64_t vector, uint64_t *regs)
regs = (uint64_t *)g_current_regs;
g_current_regs = NULL;
/* Set machine previous privilege mode to machine mode */
*(regs + REG_INT_CTX_NDX) |= 0x3 << 11;
return regs;
}
+1 -1
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@@ -1,5 +1,5 @@
/****************************************************************************
* arch/risc-v/src/k210/k210_init.c
* arch/risc-v/src/k210/k210_start.c
*
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>