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arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h: Add GPIO register definition file.
This commit is contained in:
Gregory Nutt
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/************************************************************************************
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* arch/arm/src/s32k1xx/chip/s32k1xx_gpio.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_GPIO_H
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#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_GPIO_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <hardware/s32k1xx_memorymap.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#define S32K1XX_GPIOA (0)
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#define S32K1XX_GPIOB (1)
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#define S32K1XX_GPIOC (2)
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#define S32K1XX_GPIOD (3)
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#define S32K1XX_GPIOE (4)
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#define S32K1XX_NGPIO (5)
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/* GPIO Register Offsets *************************************************************/
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#define S32K1XX_GPIO_OFFSET(g) ((g) << 6)
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#define S32K1XX_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output Register */
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#define S32K1XX_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output Register */
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#define S32K1XX_GPIO_PCOR_OFFSET 0x0008 /* Port Clear Output Register */
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#define S32K1XX_GPIO_PTOR_OFFSET 0x000c /* Port Toggle Output Register */
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#define S32K1XX_GPIO_PDIR_OFFSET 0x0010 /* Port Data Input Register */
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#define S32K1XX_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction Register */
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#define S32K1XX_GPIO_PIDR_OFFSET 0x0018 /* Port Input Disable Register */
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/* GPIO Register Addresses ***********************************************************/
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#define S32K1XX_GPIO_BASE(g) (S32K1XX_GPIO_BASE + S32K1XX_GPIO_OFFSET(g))
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#define S32K1XX_GPIO_PDOR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PDOR_OFFSET)
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#define S32K1XX_GPIO_PSOR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PSOR_OFFSET)
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#define S32K1XX_GPIO_PCOR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PCOR_OFFSET)
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#define S32K1XX_GPIO_PTOR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PTOR_OFFSET)
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#define S32K1XX_GPIO_PDIR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PDIR_OFFSET)
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#define S32K1XX_GPIO_PDDR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PDDR_OFFSET)
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#define S32K1XX_GPIO_PIDR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PIDR_OFFSET)
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#define S32K1XX_GPIOA_PDOR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PDOR_OFFSET)
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#define S32K1XX_GPIOA_PSOR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PSOR_OFFSET)
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#define S32K1XX_GPIOA_PCOR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PCOR_OFFSET)
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#define S32K1XX_GPIOA_PTOR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PTOR_OFFSET)
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#define S32K1XX_GPIOA_PDIR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PDIR_OFFSET)
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#define S32K1XX_GPIOA_PDDR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PDDR_OFFSET)
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#define S32K1XX_GPIOA_PIDR (S32K1XX_GPIOA_BASE + S32K1XX_GPIO_PIDR_OFFSET)
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#define S32K1XX_GPIOB_PDOR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PDOR_OFFSET)
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#define S32K1XX_GPIOB_PSOR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PSOR_OFFSET)
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#define S32K1XX_GPIOB_PCOR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PCOR_OFFSET)
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#define S32K1XX_GPIOB_PTOR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PTOR_OFFSET)
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#define S32K1XX_GPIOB_PDIR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PDIR_OFFSET)
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#define S32K1XX_GPIOB_PDDR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PDDR_OFFSET)
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#define S32K1XX_GPIOB_PIDR (S32K1XX_GPIOB_BASE + S32K1XX_GPIO_PIDR_OFFSET)
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#define S32K1XX_GPIOC_PDOR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PDOR_OFFSET)
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#define S32K1XX_GPIOC_PSOR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PSOR_OFFSET)
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#define S32K1XX_GPIOC_PCOR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PCOR_OFFSET)
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#define S32K1XX_GPIOC_PTOR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PTOR_OFFSET)
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#define S32K1XX_GPIOC_PDIR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PDIR_OFFSET)
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#define S32K1XX_GPIOC_PDDR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PDDR_OFFSET)
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#define S32K1XX_GPIOC_PIDR (S32K1XX_GPIOC_BASE + S32K1XX_GPIO_PIDR_OFFSET)
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#define S32K1XX_GPIOD_PDOR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PDOR_OFFSET)
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#define S32K1XX_GPIOD_PSOR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PSOR_OFFSET)
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#define S32K1XX_GPIOD_PCOR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PCOR_OFFSET)
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#define S32K1XX_GPIOD_PTOR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PTOR_OFFSET)
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#define S32K1XX_GPIOD_PDIR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PDIR_OFFSET)
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#define S32K1XX_GPIOD_PDDR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PDDR_OFFSET)
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#define S32K1XX_GPIOD_PIDR (S32K1XX_GPIOD_BASE + S32K1XX_GPIO_PIDR_OFFSET)
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#define S32K1XX_GPIOE_PDOR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PDOR_OFFSET)
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#define S32K1XX_GPIOE_PSOR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PSOR_OFFSET)
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#define S32K1XX_GPIOE_PCOR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PCOR_OFFSET)
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#define S32K1XX_GPIOE_PTOR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PTOR_OFFSET)
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#define S32K1XX_GPIOE_PDIR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PDIR_OFFSET)
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#define S32K1XX_GPIOE_PDDR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PDDR_OFFSET)
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#define S32K1XX_GPIOE_PIDR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PIDR_OFFSET)
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/* GPIO Register Bitfield Definitions ************************************************/
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/* Port Data Output Register */
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#define GPIO_PDOR(n) (1 << (n)) /* Pin n data output, n=0..31 */
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/* Port Set Output Register */
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#define GPIO_PSOR(n) (1 << (n)) /* Pin n set output, n=0..31 */
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/* Port Clear Output Register */
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#define GPIO_PCOR(n) (1 << (n)) /* Pin n clear output, n=0..31 */
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/* Port Toggle Output Register */
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#define GPIO_PTOR(n) (1 << (n)) /* Pin n toggle output, n=0..31 */
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/* Port Data Input Register */
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#define GPIO_PDIR(n) (1 << (n)) /* Pin n data input, n=0..31 */
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/* Port Data Direction Register */
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#define GPIO_PDDR(n) (1 << (n)) /* Pin n data direction, n=0..31 */
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/* Port Input Disable Register */
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#define GPIO_PIDR(n) (1 << (n)) /* Pin n input disable, n=0..31 */
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#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_GPIO_H */
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@@ -106,6 +106,11 @@
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#define S32K1XX_SMC_BASE 0x4007e000 /* System Mode controller */
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#define S32K1XX_RCM_BASE 0x4007f000 /* Reset Control Module */
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#define S32K1XX_GPIO_BASE 0x400ff000 /* GPIO controller */
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# define S32K1XX_GPIOA_BASE 0x400ff000 /* GPIOA controller */
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# define S32K1XX_GPIOB_BASE 0x400ff040 /* GPIOB controller */
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# define S32K1XX_GPIOC_BASE 0x400ff080 /* GPIOC controller */
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# define S32K1XX_GPIOD_BASE 0x400ff0c0 /* GPIOD controller */
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# define S32K1XX_GPIOE_BASE 0x400ff100 /* GPIOE controller */
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#if defined(CONFIG_ARCH_CHIP_S32K14X)
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# define S32K1XX_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell */
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