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https://github.com/apache/nuttx.git
synced 2026-06-07 01:05:54 +08:00
SAMA5 Timer/counter library
This commit is contained in:
Gregory Nutt
@@ -204,3 +204,11 @@ ifeq ($(CONFIG_SAMA5_TSD),y)
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CHIP_CSRCS += sam_tsd.c
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endif
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endif
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ifeq ($(CONFIG_SAMA5_TC0),y)
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CHIP_CSRCS += sam_tc.c
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else
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ifeq ($(CONFIG_SAMA5_TC1),y)
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CHIP_CSRCS += sam_tc.c
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endif
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endif
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@@ -60,12 +60,12 @@
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#define SAM_TC_SR_OFFSET 0x0020 /* Status Register */
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#define SAM_TC_IER_OFFSET 0x0024 /* Interrupt Enable Register */
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#define SAM_TC_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
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#define SAM_TC_IDR_OFFSET 0x002c /* Interrupt Mask Register */
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#define SAM_TC_IMR_OFFSET 0x002c /* Interrupt Mask Register */
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#define SAM_TCn_CCR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CCR_OFFSET)
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#define SAM_TCn_CMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CMR_OFFSET)
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#define SAM_TCn_SMMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_SMMR_OFFSET)
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#define SAM_TCn_SMMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RAB_OFFSET)
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#define SAM_TCn_RAB_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RAB_OFFSET)
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#define SAM_TCn_CV_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_CV_OFFSET)
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#define SAM_TCn_RA_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RA_OFFSET)
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#define SAM_TCn_RB_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_RB_OFFSET)
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@@ -73,12 +73,12 @@
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#define SAM_TCn_SR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_SR_OFFSET)
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#define SAM_TCn_IER_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IER_OFFSET)
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#define SAM_TCn_IDR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IDR_OFFSET)
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#define SAM_TCn_IMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IDR_OFFSET)
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#define SAM_TCn_IMR_OFFSET(n) (SAM_TC_CHAN_OFFSET(n)+SAM_TC_IMR_OFFSET)
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#define SAM_TC0_CCR_OFFSET SAM_TCn_CCR_OFFSET(0)
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#define SAM_TC0_CMR_OFFSET SAM_TCn_CMR_OFFSET(0)
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#define SAM_TC0_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(0)
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#define SAM_TC0_RAB_OFFSET SAM_TCn_SMMR_OFFSET(0)
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#define SAM_TC0_RAB_OFFSET SAM_TCn_RAB_OFFSET(0)
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#define SAM_TC0_CV_OFFSET SAM_TCn_CV_OFFSET(0)
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#define SAM_TC0_RA_OFFSET SAM_TCn_RA_OFFSET(0)
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#define SAM_TC0_RB_OFFSET SAM_TCn_RB_OFFSET(0)
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@@ -91,7 +91,7 @@
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#define SAM_TC1_CCR_OFFSET SAM_TCn_CCR_OFFSET(1)
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#define SAM_TC1_CMR_OFFSET SAM_TCn_CMR_OFFSET(1)
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#define SAM_TC1_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(1)
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#define SAM_TC1_RAB_OFFSET SAM_TCn_SMMR_OFFSET(1)
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#define SAM_TC1_RAB_OFFSET SAM_TCn_RAB_OFFSET(1)
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#define SAM_TC1_CV_OFFSET SAM_TCn_CV_OFFSET(1)
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#define SAM_TC1_RA_OFFSET SAM_TCn_RA_OFFSET(1)
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#define SAM_TC1_RB_OFFSET SAM_TCn_RB_OFFSET(1)
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@@ -104,7 +104,7 @@
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#define SAM_TC2_CCR_OFFSET SAM_TCn_CCR_OFFSET(2)
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#define SAM_TC2_CMR_OFFSET SAM_TCn_CMR_OFFSET(2)
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#define SAM_TC2_SMMR_OFFSET SAM_TCn_SMMR_OFFSET(2)
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#define SAM_TC2_RAB_OFFSET SAM_TCn_SMMR_OFFSET(2)
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#define SAM_TC2_RAB_OFFSET SAM_TCn_RAB_OFFSET(2)
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#define SAM_TC2_CV_OFFSET SAM_TCn_CV_OFFSET(2)
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#define SAM_TC2_RA_OFFSET SAM_TCn_RA_OFFSET(2)
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#define SAM_TC2_RB_OFFSET SAM_TCn_RB_OFFSET(2)
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@@ -142,7 +142,7 @@
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#define SAM_TC0_CCR SAM_TC012_CCR(0)
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#define SAM_TC0_CMR SAM_TC012_CMR(0)
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#define SAM_TC0_SMMR SAM_TC012_SMMR(0)
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#define SAM_TC0_RAB SAM_TC012_SMMR(0)
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#define SAM_TC0_RAB SAM_TC012_RAB(0)
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#define SAM_TC0_CV SAM_TC012_CV(0)
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#define SAM_TC0_RA SAM_TC012_RA(0)
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#define SAM_TC0_RB SAM_TC012_RB(0)
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@@ -155,7 +155,7 @@
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#define SAM_TC1_CCR SAM_TC012_CCR(1)
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#define SAM_TC1_CMR SAM_TC012_CMR(1)
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#define SAM_TC1_SMMR SAM_TC012_SMMR(1)
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#define SAM_TC1_RAB SAM_TC012_SMMR(1)
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#define SAM_TC1_RAB SAM_TC012_RAB(1)
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#define SAM_TC1_CV SAM_TC012_CV(1)
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#define SAM_TC1_RA SAM_TC012_RA(1)
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#define SAM_TC1_RB SAM_TC012_RB(1)
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@@ -168,7 +168,7 @@
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#define SAM_TC2_CCR SAM_TC012_CCR(2)
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#define SAM_TC2_CMR SAM_TC012_CMR(2)
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#define SAM_TC2_SMMR SAM_TC012_SMMR(2)
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#define SAM_TC2_RAB SAM_TC012_SMMR(2)
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#define SAM_TC2_RAB SAM_TC012_RAB(2)
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#define SAM_TC2_CV SAM_TC012_CV(2)
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#define SAM_TC2_RA SAM_TC012_RA(2)
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#define SAM_TC2_RB SAM_TC012_RB(2)
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@@ -204,7 +204,7 @@
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#define SAM_TC3_CCR SAM_TC345_CCR(3)
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#define SAM_TC3_CMR SAM_TC345_CMR(3)
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#define SAM_TC3_SMMR SAM_TC345_SMMR(3)
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#define SAM_TC3_RAB SAM_TC345_SMMR(3)
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#define SAM_TC3_RAB SAM_TC345_RAB(3)
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#define SAM_TC3_CV SAM_TC345_CV(3)
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#define SAM_TC3_RA SAM_TC345_RA(3)
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#define SAM_TC3_RB SAM_TC345_RB(3)
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@@ -217,7 +217,7 @@
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#define SAM_TC4_CCR SAM_TC345_CCR(4)
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#define SAM_TC4_CMR SAM_TC345_CMR(4)
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#define SAM_TC4_SMMR SAM_TC345_SMMR(4)
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#define SAM_TC4_RAB SAM_TC345_SMMR(4)
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#define SAM_TC4_RAB SAM_TC345_RAB(4)
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#define SAM_TC4_CV SAM_TC345_CV(4)
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#define SAM_TC4_RA SAM_TC345_RA(4)
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#define SAM_TC4_RB SAM_TC345_RB(4)
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@@ -230,7 +230,7 @@
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#define SAM_TC5_CCR SAM_TC345_CCR(5)
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#define SAM_TC5_CMR SAM_TC345_CMR(5)
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#define SAM_TC5_SMMR SAM_TC345_SMMR(5)
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#define SAM_TC5_RAB SAM_TC345_SMMR(5)
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#define SAM_TC5_RAB SAM_TC345_RAB(5)
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#define SAM_TC5_CV SAM_TC345_CV(5)
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#define SAM_TC5_RA SAM_TC345_RA(5)
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#define SAM_TC5_RB SAM_TC345_RB(5)
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@@ -398,6 +398,7 @@
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#define TC_INT_LDRAS (1 << 5) /* Bit 5: RA Loading Status */
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#define TC_INT_LDRBS (1 << 6) /* Bit 6: RB Loading Status */
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#define TC_INT_ETRGS (1 << 7) /* Bit 7: External Trigger Status */
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#define TC_INT_ALL (0xff)
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#define TC_SR_CLKSTA (1 << 16) /* Bit 16: Clock Enabling Status */
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#define TC_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror */
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@@ -104,7 +104,7 @@
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# define SAM_SPI0_OFFSET 0x00004000 /* 0x00004000-0x00007fff: SPI0 */
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# define SAM_SSC0_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SSC0 */
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# define SAM_CAN0_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: CAN0 */
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# define SAM_TC012_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC0, TC1, TC2 */
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# define SAM_TC012_OFFSET 0x00010000 /* 0x00010000-0x00013fff: TC channels 0, 1, and 2 */
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# define SAM_TWI0_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TWI0 */
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# define SAM_TWI1_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TWI1 */
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# define SAM_USART0_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: USART0 */
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@@ -123,7 +123,7 @@
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# define SAM_SPI1_OFFSET 0x00008000 /* 0x00008000-0x0000bfff: SPI1 */
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# define SAM_SSC1_OFFSET 0x0000c000 /* 0x0000c000-0x0000ffff: SSC1 */
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# define SAM_CAN1_OFFSET 0x00010000 /* 0x00010000-0x00013fff: CAN1 */
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# define SAM_TC345_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TC3, TC4, TC5 */
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# define SAM_TC345_OFFSET 0x00014000 /* 0x00014000-0x00017fff: TC channels 3, 4, and 5 */
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# define SAM_TSADC_OFFSET 0x00018000 /* 0x00018000-0x0001bfff: TSADC */
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# define SAM_TWI2_OFFSET 0x0001c000 /* 0x0001c000-0x0001ffff: TWI2 */
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# define SAM_USART2_OFFSET 0x00020000 /* 0x00020000-0x00023fff: USART2 */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,191 @@
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/****************************************************************************
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* arch/arm/src/sama5/sam_adc.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_SAM_TC_H
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#define __ARCH_ARM_SRC_SAMA5_SAM_TC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "chip.h"
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#include "chip/sam_tc.h"
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#if defined(CONFIG_SAMA5_TC0) || defined(CONFIG_SAMA5_TC1)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The timer/counter and channel arguments to sam_tc_allocate() */
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#define TC_CHAN0 0
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#define TC_CHAN1 1
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#define TC_CHAN2 2
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#define TC_CHAN3 3
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#define TC_CHAN4 4
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#define TC_CHAN5 5
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/****************************************************************************
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* Public Types
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****************************************************************************/
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typedef void *TCHANDLE;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: sam_tc_allocate
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*
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* Description:
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* Configures a Timer Counter to operate in the given mode. The timer is
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* stopped after configuration and must be restarted with sam_tc_start().
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* All the interrupts of the timer are also disabled.
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*
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* Input Parameters:
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* channel TC channel number (see TC_CHANx definitions)
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* mode Operating mode (TC_CMR value).
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*
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* Returned Value:
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* On success, a non-NULL handle value is returned. This handle may be
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* used with subsequent timer/counter interfaces to manage the timer. A
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* NULL handle value is returned on a failure.
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*
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****************************************************************************/
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TCHANDLE sam_tc_allocate(int channel, int mode);
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/****************************************************************************
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* Name: sam_tc_free
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*
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* Description:
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* Release the handle previously allocated by sam_tc_allocate().
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*
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* Input Parameters:
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* handle Channel handle previously allocated by sam_tc_allocate()
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_tc_free(TCHANDLE handle);
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/****************************************************************************
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* Name: sam_tc_start
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*
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* Description:
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* Reset and Start the TC Channel. Enables the timer clock and performs a
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* software reset to start the counting.
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*
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* Input Parameters:
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* handle Channel handle previously allocated by sam_tc_allocate()
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*
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* Returned Value:
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*
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****************************************************************************/
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void sam_tc_start(TCHANDLE handle);
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/****************************************************************************
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* Name: sam_tc_stop
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*
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* Description:
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* Stop TC Channel. Disables the timer clock, stopping the counting.
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*
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* Input Parameters:
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* handle Channel handle previously allocated by sam_tc_allocate()
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*
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* Returned Value:
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*
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****************************************************************************/
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void sam_tc_stop(TCHANDLE handle);
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/****************************************************************************
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* Name: sam_tc_divisor
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*
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* Description:
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* Finds the best MCK divisor given the timer frequency and MCK. The
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* result is guaranteed to satisfy the following equation:
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*
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* (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
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*
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* with DIV being the highest possible value.
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*
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* Input Parameters:
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*
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* frequency Desired timer frequency.
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* mck Master clock frequency.
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* div Divisor value.
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* tcclks TCCLKS field value for divisor.
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* boardmck Board clock frequency.
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*
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* Returned Value:
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* Zero (OK) if a proper divisor has been found, otherwise a negated errno
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* value indicating the nature of the failure.
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*
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****************************************************************************/
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uint32_t sam_tc_divisor(uint32_t frequency, uint32_t mck, uint32_t *div,
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uint32_t *tcclks, uint32_t boardmck);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* CONFIG_SAMA5_TC0 || CONFIG_SAMA5_TC1 */
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#endif /* __ARCH_ARM_SRC_SAMA5_SAM_TC_H */
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