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SAMA5: Add logic to initialize SAMA5D3x-EK on-board SDRAM
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@@ -46,6 +46,10 @@ ifeq ($(CONFIG_HAVE_CXX),y)
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CSRCS += sam_cxxinitialize.c
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endif
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ifeq ($(CONFIG_SAMA5_DDRCS),y)
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CSRCS += sam_sdram.c
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endif
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ifeq ($(CONFIG_SAMA5_BOOT_CS0FLASH),y)
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CSRCS += sam_norflash.c
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endif
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@@ -1,9 +1,16 @@
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/************************************************************************************
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/****************************************************************************
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* configs/sama5d3x-ek/src/sam_norflash.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Most of this file derives from Atmel sample code for the SAMA5D3x-EK
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* board. That sample code has licensing that is compatible with the NuttX
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* modified BSD license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@@ -14,8 +21,8 @@
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* 3. Neither the name NuttX nor Atmel nor the names of its contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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@@ -31,11 +38,11 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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@@ -49,17 +56,17 @@
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#ifdef CONFIG_SAMA5_BOOT_CS0FLASH
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Private Functions
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Functions
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************************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Name: board_norflash_config
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File diff suppressed because it is too large
Load Diff
@@ -108,6 +108,37 @@
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: board_sdram_config
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*
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* Description:
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* Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR)
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*
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* MT47H64M16HR : 8 Meg x 16 x 8 banks
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* Refresh count: 8K
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* Row address: A[12:0] (8K)
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* Column address A[9:0] (1K)
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* Bank address BA[2:0] a(24,25) (8)
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*
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* This logic was taken from Atmel sample code for the SAMA5D3x-EK.
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*
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* Input Parameters:
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* devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR
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*
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* Assumptions:
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* The DDR memory regions is configured as strongly ordered memory. When we
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* complete initialization of SDRAM and it is ready for use, we will make DRAM
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* into normal memory.
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*
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************************************************************************************/
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#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) && \
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!defined(CONFIG_BOOT_RUNFROMSDRAM)
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void board_sdram_config(uint8_t sdramtype);
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#else
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# define board_sdram_config(t)
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#endif
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/************************************************************************************
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* Name: up_ledinit
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************************************************************************************/
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