Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-02 01:21:26 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Fix Open1788 EMC clocking

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5796 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2013-03-28 13:35:50 +00:00
parent 50546cb1a2
commit 219c13bb1c
2 changed files with 15 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
configs/open1788/include/board.h
+6 -3
View File
@@ -123,11 +123,13 @@
#ifdef CONFIG_LPC17_EMC #ifdef CONFIG_LPC17_EMC
/* EMC clock selection. /* EMC clock selection.
* *
* The EMC uses the CPU clock undivided. * The EMC clock should not be driven above 80MHz. As a result the EMC
* uses the CPU clock divided by two.
*/ */
# define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV1 # define BOARD_EMCCLKSEL_DIVIDER 2
# define LPC17_EMCCLK LPC17_CCLK # define BOARD_EMCCLKSEL_VALUE SYSCON_EMCCLKSEL_CCLK_DIV2
# define LPC17_EMCCLK (LPC17_CCLK / BOARD_EMCCLKSEL_DIVIDER)
#endif #endif
#if defined(CONFIG_LPC17_USBHOST) || (CONFIG_LPC17_USBDEV) #if defined(CONFIG_LPC17_USBHOST) || (CONFIG_LPC17_USBDEV)
@@ -136,6 +138,7 @@
* USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz * USBCLK = PLL1CLK = (SYSCLK * 4) = 48MHz
*/ */
# define BOARD_USBCLKSEL_DIVIDER 1
# define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \ # define BOARD_USBCLKSEL_VALUE (SYSCON_USBCLKSEL_USBDIV_DIV1 | \
SYSCON_USBCLKSEL_USBSEL_PLL1) SYSCON_USBCLKSEL_USBSEL_PLL1)
#endif #endif
configs/open1788/src/lpc17_sdraminitialize.c
+9 -6
View File
@@ -62,15 +62,18 @@
* *
* For example: * For example:
* LPC17_CCLCK = 120,000,000 * LPC17_CCLCK = 120,000,000
* EMCCLKSEL -> use LPC17_CCLK undivided * EMCCLKSEL -> LPC17_CCLK divided by 2
* LPC17_EMCCLK = 120,000,000 * LPC17_EMCCLK = 60,000,000
* LPC17_EMCCLK_MHZ = 120 (rounded) * LPC17_EMCCLK_MHZ = 60 (Rounded to an integer)
* EMC_NSPERCLK = 8 (rounded) * EMC_NSPERCLK = 16.667 (Represented with 4 bits of fraction, 267)
*
* EMC_NS2CLK(63) = ((63 << 4) + 266) / 267 = 4 (actual 3.78)
* EMC_NS2CLK(20) = ((20 << 4) + 266) / 267 = 2 (actual 1.20)
*/ */
#define LPC17_EMCCLK_MHZ ((LPC17_EMCCLK + 500000) / 1000000) #define LPC17_EMCCLK_MHZ ((LPC17_EMCCLK + 500000) / 1000000)
#define EMC_NSPERCLK ((1000 + (LPC17_EMCCLK_MHZ >> 1)) / LPC17_EMCCLK_MHZ) #define EMC_NSPERCLK_B4 (((1000 << 4) + (LPC17_EMCCLK_MHZ >> 1)) / LPC17_EMCCLK_MHZ)
#define EMC_NS2CLK(ns) ((ns + (EMC_NSPERCLK - 1)) / EMC_NSPERCLK) #define EMC_NS2CLK(ns) (((ns << 4) + (EMC_NSPERCLK_B4 - 1)) / EMC_NSPERCLK_B4)
#define MDKCFG_RASCAS0VAL 0x00000303 #define MDKCFG_RASCAS0VAL 0x00000303
/* Set up for 32-bit SDRAM at CS0 */ /* Set up for 32-bit SDRAM at CS0 */