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arch/arm/src/imxrt: IOMUXC logic now uses peripheral clock helpers (I think it was enabling the wrong clocks anyway). Minor updates to eDMA logic.

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This commit is contained in:
Gregory Nutt
2018-05-20 12:02:50 -06:00
parent 9c9c0eb4d5
commit 20f1597fa5
3 changed files with 29 additions and 17 deletions
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arch/arm/src/imxrt/imxrt_edma.c
+14 -4
View File
@@ -518,14 +518,18 @@ DMA_HANDLE imxrt_dmachannel(uint32_t dmamux)
dmach->state = IMXRT_DMA_IDLE;
/* Clear any pending interrupts on the channel */
#warning Missing Logic
/* Disable the channel. */
#warning Missing Logic
DEBUASSERT(chndx == dmach->chan);
regaddr = IMXRT_EDMA_TCD_CSR(chndx);
putreg(0, regaddr);
/* Make sure that the channel is disabled. */
regval8 = EDMA_CERQ(chndx);
putreg8(reqval8, IMXRT_EDMA_CERQ);
/* Set the DMAMUX register associated with this channel */
DEBUASSERT(chndx == dmach->chan);
regaddr = IMXRT_DMAMUX_CHCF(chndx);
putreg32(dmamux, regaddr);
break;
@@ -565,6 +569,7 @@ void imxrt_dmafree(DMA_HANDLE handle)
{
struct imxrt_dmach_s *dmach = (struct imxrt_dmach_s *)handle;
uintptr_t regaddr;
uint8_t regval8;
dmainfo("dmach: %p\n", dmach);
DEBUGASSERT(dmach != NULL && dmach->inuse && dmach->state != IMXRT_DMA_ACTIVE);
@@ -577,6 +582,11 @@ void imxrt_dmafree(DMA_HANDLE handle)
dmach->inuse = false; /* No longer in use */
dmach->state = IMXRT_DMA_IDLE; /* Better not be active! */
/* Make sure that the channel is disabled. */
regval8 = EDMA_CERQ(chndx);
putreg8(reqval8, IMXRT_EDMA_CERQ);
/* Disable the associated DMAMUX */
regaddr = IMXRT_DMAMUX_CHCF(chndx);
arch/arm/src/imxrt/imxrt_iomuxc.c
+9 -6
View File
@@ -49,6 +49,7 @@
#include "up_arch.h"
#include "chip/imxrt_ccm.h"
#include "imxrt_periphclks.h"
#include "imxrt_iomuxc.h"
/****************************************************************************
@@ -231,13 +232,15 @@ int imxrt_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset)
uint32_t regval = 0;
uint32_t value;
/* Enable IOMUXC clock if it is not enabled*/
/* Enable IOMUXC clock if it is not already enabled */
regval = getreg32(IMXRT_CCM_CCGR2);
if ((regval & CCM_CCGRX_CG2_MASK) == 0)
{
putreg32(CCM_CG_ALL << CCM_CCGRX_CG2_SHIFT, IMXRT_CCM_CCGR2);
}
imxrt_clockall_iomuxc();
imxrt_clockall_iomuxc_gpr();
#if 0 /* Are low-power domain, Secure Non-volatile Storage (SNVS) IOMUXC clocks needed? */
imxrt_clockall_iomuxc_snvs();
imxrt_clockall_iomuxc_snvs_gpr();
#endif
/* Select CMOS input or Schmitt Trigger input */
arch/arm/src/imxrt/imxrt_lowputc.c
+6 -7
View File
@@ -123,9 +123,8 @@
* of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
* control input pins. It must always be running when UART is enabled.
*
* The default ipg_clk is 66MHz (max 66.5MHz). ipg_clk is gated by
* CCGR5[CG12], uart_clk_enable. ipg_clk is shared among many modules and
* should not be controlled by the UART logic.
* The default lpuart1 ipg_clk is 66MHz (max 66.5MHz). ipg_clk is shared
* among many modules and should not be controlled by the UART logic.
*
* The module_clock is for all the state machines, writing RxFIFO, reading
* TxFIFO, etc. It must always be running when UART is sending or receiving
@@ -133,11 +132,11 @@
* peripheral_clock without changing configuration of baud rate.
*
* The default ipg_perclk is 80MHz (max 80MHz). ipg_perclk is gated by
* CCGR5[CG13], uart_serial_clk_enable. The clock generation sequence is:
* CCGR5[CG12], lpuart1_clk_enable. The clock generation sequence is:
*
* pll3_sw_clk (480M) -> CCGR5[CG13] -> 3 bit divider cg podf=6 ->
* PLL3_80M (80Mhz) -> CDCDR1: uart_clk_podf ->
* 6 bit divider default=1 -> UART_CLK_ROOT
* pll3_sw_clk (480M) -> CCGR5[CG12] -> 3 bit divider cg podf=6 ->
* PLL3_80M (80Mhz) -> CDCDR1: lpuart1_clk_podf ->
* 6 bit divider default=1 -> LPUART1_CLK_ROOT
*
* REVISIT: This logic assumes that all dividers are at the default value
* and that the value of the ipg_perclk is 80MHz.