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Merged in extent3d/nuttx/i2c (pull request #588)
SAMDL: Added I2S register definitions Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Matt Thompson
committed by
Gregory Nutt
Gregory Nutt
parent
3521aaf944
commit
1f10a9c576
@@ -158,8 +158,8 @@
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# define GCLK_CLKCTRL_ID_ACANA (32 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
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# define GCLK_CLKCTRL_ID_DAC (33 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
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# define GCLK_CLKCTRL_ID_PTC (34 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
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# define GCLK_CLKCTRL_I2S0_PTC (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
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# define GCLK_CLKCTRL_I2S1_PTC (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
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# define GCLK_CLKCTRL_ID_I2S0 (35 << GCLK_CLKCTRL_ID_SHIFT) /* I2S0 */
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# define GCLK_CLKCTRL_ID_I2S1 (36 << GCLK_CLKCTRL_ID_SHIFT) /* I2S1 */
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#endif
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#define GCLK_CLKCTRL_GEN_SHIFT (8) /* Bits 8-11: Generic Clock Generator */
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@@ -0,0 +1,203 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/samd_i2s.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Matt Thompson <matt@extent3d.com>
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*
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* References:
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* "Microchip SAMD21 datasheet"
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2S_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2S_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* I2S register offsets *********************************************************************/
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#define SAM_I2S_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_I2S_CLKCTRL0_OFFSET 0x0004 /* Clock Control 0 register */
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#define SAM_I2S_CLKCTRL1_OFFSET 0x0008 /* Clock Control 1 register */
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#define SAM_I2S_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
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#define SAM_I2S_INTENSET_OFFSET 0x0010 /* Interrupt enable set register */
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#define SAM_I2S_INTFLAG_OFFSET 0x0014 /* Interrupt flag register */
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#define SAM_I2S_SYNCBUSY_OFFSET 0x0018 /* Sync Busy register */
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#define SAM_I2S_SERCTRL0_OFFSET 0x0020 /* Serializer 0 Control register */
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#define SAM_I2S_SERCTRL1_OFFSET 0x0024 /* Serializer 1 Control register */
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#define SAM_I2S_DATA0_OFFSET 0x0030 /* Data 0 register */
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#define SAM_I2S_DATA1_OFFSET 0x0034 /* Data 1 register */
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/* I2S register addresses ******************************************************************/
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#define SAM_I2S_CTRLA (SAM_I2S_BASE+SAM_I2S_CTRLA_OFFSET)
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#define SAM_I2S_CLKCTRL0 (SAM_I2S_BASE+SAM_I2S_CLKCTRL0_OFFSET)
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#define SAM_I2S_CLKCTRL1 (SAM_I2S_BASE+SAM_I2S_CLKCTRL1_OFFSET)
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#define SAM_I2S_INTENCLR (SAM_I2S_BASE+SAM_I2S_INTENCLR_OFFSET)
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#define SAM_I2S_INTENSET (SAM_I2S_BASE+SAM_I2S_INTENSET_OFFSET)
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#define SAM_I2S_INTFLAG (SAM_I2S_BASE+SAM_I2S_INTFLAG_OFFSET)
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#define SAM_I2S_SYNCBUSY (SAM_I2S_BASE+SAM_I2S_SYNCBUSY_OFFSET)
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#define SAM_I2S_SERCTRL0 (SAM_I2S_BASE+SAM_I2S_SERCTRL0_OFFSET)
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#define SAM_I2S_SERCTRL1 (SAM_I2S_BASE+SAM_I2S_SERCTRL1_OFFSET)
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#define SAM_I2S_DATA0 (SAM_I2S_BASE+SAM_I2S_DATA0_OFFSET)
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#define SAM_I2S_DATA1 (SAM_I2S_BASE+SAM_I2S_DATA1_OFFSET)
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/* I2S register bit definitions ************************************************************/
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/* Control A register */
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#define I2S_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */
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#define I2S_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define I2S_CTRLA_CKEN0 (1 << 2) /* Bit 2: Clock Unit 0 Enable */
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#define I2S_CTRLA_CKEN1 (1 << 3) /* Bit 3: Clock Unit 1 Enable */
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#define I2S_CTRLA_SEREN0 (1 << 4) /* Bit 4: Serializer 0 Enable */
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#define I2S_CTRLA_SEREN1 (1 << 5) /* Bit 5: Seriailier 1 Enable */
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/* Clock Unit Control Register */
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#define I2S_CLKCTRL_SLOTSIZE_SHIFT (0) /* Bits [1:0]: Slot Size */
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#define I2S_CLKCTRL_SLOTSIZE_MASK (3 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
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# define I2S_CLKCTRL_SLOTSIZE_8 (0 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
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# define I2S_CLKCTRL_SLOTSIZE_16 (1 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
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# define I2S_CLKCTRL_SLOTSIZE_24 (2 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
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# define I2S_CLKCTRL_SLOTSIZE_32 (3 << I2S_CLKCTRL_SLOTSIZE_SHIFT)
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#define I2S_CLKCTRL_NBSLOTS_SHIFT (2) /* Bit 2: Number of Slots in Frame */
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#define I2S_CLKCTRL_NBSLOTS_MASK (7 << I2S_CLKCTRL_NBSLOTS_SHIFT)
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#define I2S_CLKCTRL_NBSLOTS(n) (((n) & 0x7) << I2S_CLKCTRL_NBSLOTS_SHIFT)
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#define I2S_CLKCTRL_FSWIDTH_SHIFT (5) /* Bits [6:5]: Frame Sync Width */
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#define I2S_CLKCTRL_FSWIDTH_MASK (3 << I2S_CLKCTRL_FSWIDTH_SHIFT)
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# define I2S_CLKCTRL_FSWIDTH_SLOT (0 << I2S_CLKCTRL_FSWIDTH_SHIFT)
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# define I2S_CLKCTRL_FSWIDTH_HALF (1 << I2S_CLKCTRL_FSWIDTH_SHIFT)
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# define I2S_CLKCTRL_FSWIDTH_BIT (2 << I2S_CLKCTRL_FSWIDTH_SHIFT)
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# define I2S_CLKCTRL_FSWIDTH_BURST (3 << I2S_CLKCTRL_FSWIDTH_SHIFT)
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#define I2S_CLKCTRL_BITDELAY (1 << 7) /* Bit 7: Data Delay from Frame Sync */
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#define I2S_CLKCTRL_FSSEL (1 << 8) /* Bit 8: Frame Sync Select */
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#define I2S_CLKCTRL_FSINV (1 << 11) /* Bit 11: Frame Sync Invert */
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#define I2S_CLKCTRL_SCKSEL (1 << 12) /* Bit 12: Serial Clock Select. 0: Divided Master clock, 1: SCKn input pin */
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#define I2S_CLKCTRL_MCKSEL (1 << 16) /* Bit 16: Master Clock Select. 0: GCLK, 1: MCKn input pin */
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#define I2S_CLKCTRL_MCKEN (1 << 18) /* Bit 18: Master Clock Enable */
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#define I2S_CLKCTRL_MCKDIV_SHIFT (19) /* Bits [23:19]: Master Clock Division Factor */
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#define I2S_CLKCTRL_MCKDIV_MASK (0x1f << I2S_CLKCTRL_MCKDIV_SHIFT)
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#define I2S_CLKCTRL_MCKDIV(n) (((n) & 0x1f) << I2S_CLKCTRL_MCKDIV_SHIFT)
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#define I2S_CLKCTRL_MCKOUTDIV_SHIFT (24) /* Bits [28:24]: Master Clock Output Division Factor */
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#define I2S_CLKCTRL_MCKOUTDIV_MASK (0x1f << I2S_CLKCTRL_MCKOUTDIV_SHIFT)
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#define I2S_CLKCTRL_MCKOUTDIV(n) (((n) & 0x1f) << I2S_CLKCTRL_MCKOUTDIV_SHIFT)
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#define I2S_CLKCTRL_FSOUTINV (1 << 29) /* Bit 29: Frame Sync Output Invert */
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#define I2S_CLKCTRL_SCKOUTINV (1 << 30) /* Bit 30: Serial Clock Output Invert */
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#define I2S_CLKCTRL_MCKOUTINV (1 << 31) /* Bit 31: Master Clock Output Invert */
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/* Interrupt register bits */
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#define I2S_INT_RXRDY0 (1 << 0) /* Bit 0: Receive Ready 0 */
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#define I2S_INT_RXRDY1 (1 << 1) /* Bit 1: Receive Ready 1 */
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#define I2S_INT_RXOR0 (1 << 4) /* Bit 4: Receive Overrun 0 */
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#define I2S_INT_RXOR1 (1 << 5) /* Bit 5: Receive Overrun 1 */
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#define I2S_INT_TXRDY0 (1 << 8) /* Bit 8: Transmit Ready 0 */
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#define I2S_INT_TXRDY1 (1 << 9) /* Bit 9: Transmit Ready 1 */
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#define I2S_INT_TXUR0 (1 << 12) /* Bit 12: Transmit Underrun 0 */
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#define I2S_INT_TXUR1 (1 << 13) /* Bit 13: Transmit Underrun 1 */
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#define I2S_INT_ALL (0x3333)
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/* Sync Busy register bits */
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#define I2S_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software Reset Sync Status */
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#define I2S_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable Sync Status */
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#define I2S_SYNCBUSY_CKEN0 (1 << 2) /* Bit 2: Clock Unit 0 Sync Status */
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#define I2S_SYNCBUSY_CKEN1 (1 << 3) /* Bit 3: Clock Unit 1 Sync Status */
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#define I2S_SYNCBUSY_SEREN0 (1 << 4) /* Bit 4: Serializer 0 Enable Sync Status */
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#define I2S_SYNCBUSY_SEREN1 (1 << 5) /* Bit 5: Seriaiizer 1 Enable Sync Status */
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#define I2S_SYNCBUSY_DATA0 (1 << 8) /* Bit 8: Data 0 Sync Status */
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#define I2S_SYNCBUSY_DATA1 (1 << 9) /* Bit 9: Data 1 Sync Status */
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/* Serializer Control register bits */
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#define I2S_SERCTRL_SERMODE_SHIFT (0) /* Bits [1:0]: Seriailizer Mode */
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#define I2S_SERCTRL_SERMODE_MASK (3 << I2S_SERCTRL_SERMODE_SHIFT)
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# define I2S_SERCTRL_SERMODE_RX (0 << I2S_SERCTRL_SERMODE_SHIFT)
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# define I2S_SERCTRL_SERMODE_TX (1 << I2S_SERCTRL_SERMODE_SHIFT)
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# define I2S_SERCTRL_SERMODE_PDM2 (2 << I2S_SERCTRL_SERMODE_SHIFT)
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#define I2S_SERCTRL_TXDEFAULT_SHIFT (2) /* Bits [3:2]: Line Default when Slot Disabled */
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#define I2S_SERCTRL_TXDEFAULT_MASK (3 << I2S_SERCTRL_TXDEFAULT_SHIFT)
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# define I2S_SERCTRL_TXDEFAULT_ZERO (0 << I2S_SERCTRL_TXDEFAULT_SHIFT)
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# define I2S_SERCTRL_TXDEFAULT_ONE (1 << I2S_SERCTRL_TXDEFAULT_SHIFT)
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# define I2S_SERCTRL_TXDEFAULT_HIZ (3 << I2S_SERCTRL_TXDEFAULT_SHIFT)
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#define I2S_SERCTRL_TXSAME (1 << 4) /* Bit 4: Transmit last data when Underrun */
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#define I2S_SERCTRL_CLKSEL (1 << 5) /* Bit 5: Clock Unit Selection. 0: Use Clock 0, 1: Use Clock 1 */
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#define I2S_SERCTRL_SLOTADJ (1 << 7) /* Bit 7: Data slot formatting. 0: Right justified, 1: Left justified */
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#define I2S_SERCTRL_DATASIZE_SHIFT (8) /* Bits [10:8]: Data Word Size */
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#define I2S_SERCTRL_DATASIZE_MASK (7 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_32 (0 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_24 (1 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_20 (2 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_18 (3 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_16 (4 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_16C (5 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_8 (6 << I2S_SERCTRL_DATASIZE_SHIFT)
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# define I2S_SERCTRL_DATASIZE_8C (7 << I2S_SERCTRL_DATASIZE_SHIFT)
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#define I2S_SERCTRL_WORDADJ (1 << 12) /* Bit 12: Data word formatting. 0: Right justified, 1: Left justified */
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#define I2S_SERCTRL_EXTEND_SHIFT (13) /* Bits [14:13]: Data formatting bit extension */
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#define I2S_SERCTRL_EXTEND_MASK (3 << I2S_SERCTRL_EXTEND_SHIFT)
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# define I2S_SERCTRL_EXTEND_ZERO (0 << I2S_SERCTRL_EXTEND_SHIFT)
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# define I2S_SERCTRL_EXTEND_ONE (1 << I2S_SERCTRL_EXTEND_SHIFT)
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# define I2S_SERCTRL_EXTEND_MSBIT (2 << I2S_SERCTRL_EXTEND_SHIFT)
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# define I2S_SERCTRL_EXTEND_LSBIT (3 << I2S_SERCTRL_EXTEND_SHIFT)
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#define I2S_SERCTRL_BITREV (1 << 15) /* Bit 15: Data formatting bit reverse */
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#define I2S_SERCTRL_SLOTDIS_SHIFT (16) /* Bits [23:16]: Slot x Disabled */
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#define I2S_SERCTRL_SLOTDIS_MASK (0xff << I2S_SERCTRL_SLOTDIS_SHIFT)
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#define I2S_SERCTRL_SLOTDIS(n) (((n) & 0xff) << I2C_SERCTRL_SLOTDIS_SHIFT)
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#define I2S_SERCTRL_MONO (1 << 24) /* Bit 24: Mono Mode */
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#define I2S_SERCTRL_DMA (1 << 25) /* Bit 25: Single or Multiple DMA channels */
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#define I2S_SERCTRL_RXLOOP (1 << 26) /* Bit 26: RX Loopback Test Mode */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2S_H */
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@@ -228,7 +228,7 @@
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#define PM_APBCMASK_PTC (1 << 19) /* Bit 19: PTC */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define PM_APBBMASK_I2S (1 << 20) /* Bit 20: Inter IC Sound */
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# define PM_APBCMASK_I2S (1 << 20) /* Bit 20: Inter IC Sound */
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#endif
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/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */
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@@ -107,7 +107,7 @@
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#define sam_ptc_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PTC)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_i2s_enableperiph() sam_apbc_enableperiph(PM_APBBMASK_I2S)
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# define sam_i2s_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_I2S)
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#endif
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#define sam_apba_disableperiph(s) modifyreg32(SAM_PM_APBAMASK,s,0)
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@@ -167,7 +167,7 @@
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#define sam_ptc_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PTC)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_i2s_disableperiph() sam_apbc_disableperiph(PM_APBBMASK_I2S)
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# define sam_i2s_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_I2S)
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#endif
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#define sam_apba_isenabled(s) (getreg32(SAM_PM_APBAMASK) & (s)) != 0)
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@@ -227,7 +227,7 @@
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#define sam_ptc_isenabled() sam_apbc_isenabled(PM_APBCMASK_PTC)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_i2s_isenabled() sam_apbc_isenabled(PM_APBBMASK_I2S)
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# define sam_i2s_isenabled() sam_apbc_isenabled(PM_APBCMASK_I2S)
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#endif
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/****************************************************************************
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