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KSZ80x1 PHY interrupts are active low and should trigger on the falling edge
This commit is contained in:
@@ -435,11 +435,12 @@
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* Speed Mode:100Mbps
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* Speed Mode:100Mbps
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* Nway Auto-Negotiation:Enable
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* Nway Auto-Negotiation:Enable
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*
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*
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* The KSZ8051 PHY interrupt is available on PE30 INT_ETH1
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* The KSZ8051 PHY interrupt is available on PE30 INT_ETH1. The sense of
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* the interrupt is configurable but is, by default, active low.
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*/
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*/
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#define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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#define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN30)
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PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN30)
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#define IRQ_INT_ETH1 SAM_IRQ_PE30
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#define IRQ_INT_ETH1 SAM_IRQ_PE30
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#endif
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#endif
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@@ -454,11 +455,12 @@
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* activity indicators. These signals can be used to connect to a 10/100/1000
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* activity indicators. These signals can be used to connect to a 10/100/1000
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* BaseT RJ45 connector integrated on the main board.
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* BaseT RJ45 connector integrated on the main board.
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*
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*
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* The KSZ9021/31 interrupt is available on PB35 INT_GETH0
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* The KSZ9021/31 interrupt is available on PB35 INT_GETH0. The sense of
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* the interrupt is configurable but is, by default, active low.
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*/
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*/
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#define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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#define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN25)
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PIO_INT_FALLING | PIO_PORT_PIOB | PIO_PIN25)
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#define IRQ_INT_ETH0 SAM_IRQ_PB25
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#define IRQ_INT_ETH0 SAM_IRQ_PB25
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#endif
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#endif
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@@ -562,11 +562,12 @@
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* Speed Mode:100Mbps
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* Speed Mode:100Mbps
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* Nway Auto-Negotiation:Enable
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* Nway Auto-Negotiation:Enable
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*
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*
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* The KSZ8051 PHY interrupt is available on PE30 INT_ETH1
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* The KSZ8051 PHY interrupt is available on PE30 INT_ETH1. The sense of
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* the interrupt is configurable but is, by default, active low.
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*/
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*/
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#define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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#define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN30)
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PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN30)
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#define IRQ_INT_ETH1 SAM_IRQ_PE30
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#define IRQ_INT_ETH1 SAM_IRQ_PE30
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#endif
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#endif
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@@ -581,11 +582,12 @@
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* activity indicators. These signals can be used to connect to a 10/100/1000
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* activity indicators. These signals can be used to connect to a 10/100/1000
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* BaseT RJ45 connector integrated on the main board.
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* BaseT RJ45 connector integrated on the main board.
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*
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*
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* The KSZ9021/31 interrupt is available on PB35 INT_GETH0
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* The KSZ9021/31 interrupt is available on PB35 INT_GETH0. The sense of
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* the interrupt is configurable but is, by default, active low.
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*/
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*/
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#define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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#define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN25)
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PIO_INT_FALLING | PIO_PORT_PIOB | PIO_PIN25)
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#define IRQ_INT_ETH0 SAM_IRQ_PB25
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#define IRQ_INT_ETH0 SAM_IRQ_PB25
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#endif
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#endif
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@@ -744,18 +744,21 @@
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* enabled via LCD_ETH1_CONFIG when an LCD is detected:
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* enabled via LCD_ETH1_CONFIG when an LCD is detected:
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*
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*
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* - LCD_ETH1_CONFIG = 0: LCD 5v disable
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* - LCD_ETH1_CONFIG = 0: LCD 5v disable
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* - LCD_ETH1_CONFIG = 1 & LCD_DETECT# =0: LCD 5v enable
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* - LCD_ETH1_CONFIG = 1 & LCD_DETECT# =0: LCD 5v enable.
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*
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* The sense of KSZ8081 interrupt is configurable but is, by default, active
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* low.
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*/
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*/
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#ifdef CONFIG_SAMA5_EMAC0
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#ifdef CONFIG_SAMA5_EMAC0
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# define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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# define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN1)
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PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN1)
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# define IRQ_INT_ETH0 SAM_IRQ_PE1
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# define IRQ_INT_ETH0 SAM_IRQ_PE1
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#endif
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#endif
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#ifdef CONFIG_SAMA5_EMAC1
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#ifdef CONFIG_SAMA5_EMAC1
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# define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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# define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
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PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN2)
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PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN2)
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# define IRQ_INT_ETH1 SAM_IRQ_PE2
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# define IRQ_INT_ETH1 SAM_IRQ_PE2
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#endif
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#endif
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#endif
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#endif
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