diff --git a/configs/sama5d3-xplained/src/sama5d3-xplained.h b/configs/sama5d3-xplained/src/sama5d3-xplained.h
index c51e0f68361..6d24bc53eb8 100644
--- a/configs/sama5d3-xplained/src/sama5d3-xplained.h
+++ b/configs/sama5d3-xplained/src/sama5d3-xplained.h
@@ -419,27 +419,28 @@
 /* Ethernet */
 
 #ifdef CONFIG_SAMA5_EMACA
- /* ETH1: Ethernet 10/100 (EMAC A) Port
-  *
-  * The main board contains a MICREL PHY device (KSZ8051) operating at 10/100 Mbps.
-  * The board supports MII and RMII interface modes.
-  *
-  * The two independent PHY devices embedded on CM and MB boards are connected to
-  * independent RJ-45 connectors with built-in magnetic and status LEDs.
-  *
-  * At the De-Assertion of Reset:
-  *   PHY ADD[2:0]:001
-  *   CONFIG[2:0]:001,Mode:RMII
-  *   Duplex Mode:Half Duplex
-  *   Isolate Mode:Disable
-  *   Speed Mode:100Mbps
-  *   Nway Auto-Negotiation:Enable
-  *
-  * The KSZ8051 PHY interrupt is available on PE30 INT_ETH1
-  */
+  /* ETH1: Ethernet 10/100 (EMAC A) Port
+   *
+   * The main board contains a MICREL PHY device (KSZ8051) operating at 10/100 Mbps.
+   * The board supports MII and RMII interface modes.
+   *
+   * The two independent PHY devices embedded on CM and MB boards are connected to
+   * independent RJ-45 connectors with built-in magnetic and status LEDs.
+   *
+   * At the De-Assertion of Reset:
+   *   PHY ADD[2:0]:001
+   *   CONFIG[2:0]:001,Mode:RMII
+   *   Duplex Mode:Half Duplex
+   *   Isolate Mode:Disable
+   *   Speed Mode:100Mbps
+   *   Nway Auto-Negotiation:Enable
+   *
+   * The KSZ8051 PHY interrupt is available on PE30 INT_ETH1.  The sense of
+   * the interrupt is configurable but is, by default, active low.
+   */
 
 #define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
-                      PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN30)
+                      PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN30)
 #define IRQ_INT_ETH1 SAM_IRQ_PE30
 
 #endif
@@ -454,11 +455,12 @@
    * activity indicators. These signals can be used to connect to a 10/100/1000
    * BaseT RJ45 connector integrated on the main board.
    *
-   * The KSZ9021/31 interrupt is available on PB35 INT_GETH0
+   * The KSZ9021/31 interrupt is available on PB35 INT_GETH0.  The sense of
+   * the interrupt is configurable but is, by default, active low.
    */
 
 #define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
-                      PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN25)
+                      PIO_INT_FALLING | PIO_PORT_PIOB | PIO_PIN25)
 #define IRQ_INT_ETH0 SAM_IRQ_PB25
 
 #endif
diff --git a/configs/sama5d3x-ek/src/sama5d3x-ek.h b/configs/sama5d3x-ek/src/sama5d3x-ek.h
index 578155cb1ee..697dd3a844a 100644
--- a/configs/sama5d3x-ek/src/sama5d3x-ek.h
+++ b/configs/sama5d3x-ek/src/sama5d3x-ek.h
@@ -546,27 +546,28 @@
 /* Ethernet */
 
 #ifdef CONFIG_SAMA5_EMACA
- /* ETH1: Ethernet 10/100 (EMAC A) Port
-  *
-  * The main board contains a MICREL PHY device (KSZ8051) operating at 10/100 Mbps.
-  * The board supports MII and RMII interface modes.
-  *
-  * The two independent PHY devices embedded on CM and MB boards are connected to
-  * independent RJ-45 connectors with built-in magnetic and status LEDs.
-  *
-  * At the De-Assertion of Reset:
-  *   PHY ADD[2:0]:001
-  *   CONFIG[2:0]:001,Mode:RMII
-  *   Duplex Mode:Half Duplex
-  *   Isolate Mode:Disable
-  *   Speed Mode:100Mbps
-  *   Nway Auto-Negotiation:Enable
-  *
-  * The KSZ8051 PHY interrupt is available on PE30 INT_ETH1
-  */
+  /* ETH1: Ethernet 10/100 (EMAC A) Port
+   *
+   * The main board contains a MICREL PHY device (KSZ8051) operating at 10/100 Mbps.
+   * The board supports MII and RMII interface modes.
+   *
+   * The two independent PHY devices embedded on CM and MB boards are connected to
+   * independent RJ-45 connectors with built-in magnetic and status LEDs.
+   *
+   * At the De-Assertion of Reset:
+   *   PHY ADD[2:0]:001
+   *   CONFIG[2:0]:001,Mode:RMII
+   *   Duplex Mode:Half Duplex
+   *   Isolate Mode:Disable
+   *   Speed Mode:100Mbps
+   *   Nway Auto-Negotiation:Enable
+   *
+   * The KSZ8051 PHY interrupt is available on PE30 INT_ETH1.  The sense of
+   * the interrupt is configurable but is, by default, active low.
+   */
 
 #define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
-                      PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN30)
+                      PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN30)
 #define IRQ_INT_ETH1 SAM_IRQ_PE30
 
 #endif
@@ -581,11 +582,12 @@
    * activity indicators. These signals can be used to connect to a 10/100/1000
    * BaseT RJ45 connector integrated on the main board.
    *
-   * The KSZ9021/31 interrupt is available on PB35 INT_GETH0
+   * The KSZ9021/31 interrupt is available on PB35 INT_GETH0.  The sense of
+   * the interrupt is configurable but is, by default, active low.
    */
 
 #define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
-                      PIO_INT_BOTHEDGES | PIO_PORT_PIOB | PIO_PIN25)
+                      PIO_INT_FALLING | PIO_PORT_PIOB | PIO_PIN25)
 #define IRQ_INT_ETH0 SAM_IRQ_PB25
 
 #endif
diff --git a/configs/sama5d4-ek/src/sama5d4-ek.h b/configs/sama5d4-ek/src/sama5d4-ek.h
index fc49e0b6c34..1b19946ebf6 100644
--- a/configs/sama5d4-ek/src/sama5d4-ek.h
+++ b/configs/sama5d4-ek/src/sama5d4-ek.h
@@ -744,18 +744,21 @@
  * enabled via LCD_ETH1_CONFIG when an LCD is detected:
  *
  * - LCD_ETH1_CONFIG = 0: LCD 5v disable
- * - LCD_ETH1_CONFIG = 1 & LCD_DETECT# =0: LCD 5v enable
+ * - LCD_ETH1_CONFIG = 1 & LCD_DETECT# =0: LCD 5v enable.
+ *
+ * The sense of KSZ8081 interrupt is configurable but is, by default, active
+ * low.
  */
 
 #ifdef CONFIG_SAMA5_EMAC0
 #  define PIO_INT_ETH0 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
-                        PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN1)
+                        PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN1)
 #  define IRQ_INT_ETH0 SAM_IRQ_PE1
 #endif
 
 #ifdef CONFIG_SAMA5_EMAC1
 #  define PIO_INT_ETH1 (PIO_INPUT | PIO_CFG_PULLUP | PIO_CFG_DEGLITCH | \
-                        PIO_INT_BOTHEDGES | PIO_PORT_PIOE | PIO_PIN2)
+                        PIO_INT_FALLING | PIO_PORT_PIOE | PIO_PIN2)
 #  define IRQ_INT_ETH1 SAM_IRQ_PE2
 #endif
 #endif