mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
LPC1788 updates -- OS test configuration now works
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5704 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -78,9 +78,9 @@
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/* Clocking and power control -- Clock dividers */
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#define LPC17_SYSCON_EMCCLKCFG_OFFSET 0x0100 /* EMC Clock Configuration Register */
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#define LPC17_SYSCON_CCLKCFG_OFFSET 0x0104 /* CPU Clock Configuration Register */
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#define LPC17_SYSCON_USBCLKCFG_OFFSET 0x0108 /* USB Clock Configuration Register */
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#define LPC17_SYSCON_EMCCLKSEL_OFFSET 0x0100 /* EMC Clock Selection Register */
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#define LPC17_SYSCON_CCLKSEL_OFFSET 0x0104 /* CPU Clock Selection Register */
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#define LPC17_SYSCON_USBCLKSEL_OFFSET 0x0108 /* USB Clock Selection Register */
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/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */
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@@ -160,9 +160,9 @@
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/* Clocking and power control -- Clock dividers */
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#define LPC17_SYSCON_EMCCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCLKCFG_OFFSET)
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#define LPC17_SYSCON_CCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKCFG_OFFSET)
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#define LPC17_SYSCON_USBCLKCFG (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKCFG_OFFSET)
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#define LPC17_SYSCON_EMCCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_EMCCLKSEL_OFFSET)
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#define LPC17_SYSCON_CCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_CCLKSEL_OFFSET)
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#define LPC17_SYSCON_USBCLKSEL (LPC17_SYSCON_BASE+LPC17_SYSCON_USBCLKSEL_OFFSET)
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/* 0x400f c110 - 0x400f c114: CAN Wake and Sleep Registers */
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@@ -277,28 +277,28 @@
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/* 0: EMC uses same clock as CPU */
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/* 1: EMC uses half the rate of CPU */
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/* Bits 1-31: Reserved */
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/* CPU Clock Configuration register */
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/* CPU Clock Selection register */
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#define SYSCON_CCLKCFG_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */
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#define SYSCON_CCLKCFG_CCLKDIV_MASK (0x1f << SYSCON_CCLKCFG_CCLKDIV_SHIFT)
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# define SYSCON_CCLKCFG_CCLKDIV(n) ((n-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT) /* n = 2 - 31 */
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#define SYSCON_CCLKSEL_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */
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#define SYSCON_CCLKSEL_CCLKDIV_MASK (0x1f << SYSCON_CCLKSEL_CCLKDIV_SHIFT)
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# define SYSCON_CCLKSEL_CCLKDIV(n) ((n-1) << SYSCON_CCLKSEL_CCLKDIV_SHIFT) /* n = 2 - 31 */
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/* Bits 5-7: Reserved */
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#define SYSCON_CCLKCFG_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */
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#define SYSCON_CCLKSEL_CCLKSEL (1 << 8) /* Bit 8: Select input clock to CPU clock divider */
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/* 0: Sysclk used as input to CCLKDIV */
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/* 1: Main PLL used as input to CCLKDIV */
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/* Bits 9-31: Reserved */
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/* USB Clock Configuration register */
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/* USB Clock Selection register */
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#define SYSCON_USBCLKCFG_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */
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#define SYSCON_USBCLKCFG_USBDIV_MASK (0x1f << SYSCON_USBCLKCFG_USBDIV_SHIFT)
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# define SYSCON_USBCLKCFG_USBDIV_DIV1 (1 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
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# define SYSCON_USBCLKCFG_USBDIV_DIV2 (2 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
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# define SYSCON_USBCLKCFG_USBDIV_DIV3 (3 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
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#define SYSCON_USBCLKSEL_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */
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#define SYSCON_USBCLKSEL_USBDIV_MASK (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT)
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# define SYSCON_USBCLKSEL_USBDIV_DIV1 (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
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# define SYSCON_USBCLKSEL_USBDIV_DIV2 (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
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# define SYSCON_USBCLKSEL_USBDIV_DIV3 (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
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/* Bits 5-7: Reserved */
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#define SYSCON_USBCLKCFG_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */
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#define SYSCON_USBCLKCFG_USBSEL_MASK (3 << SYSCON_USBCLKCFG_USBSEL_SHIFT)
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#define SYSCON_USBCLKCFG_USBSEL_PLL0 (1 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */
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#define SYSCON_USBCLKCFG_USBSEL_PLL1 (2 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */
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#define SYSCON_USBCLKSEL_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */
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#define SYSCON_USBCLKSEL_USBSEL_MASK (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT)
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#define SYSCON_USBCLKSEL_USBSEL_PLL0 (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */
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#define SYSCON_USBCLKSEL_USBSEL_PLL1 (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */
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/* 11: unused */
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/* Bits 10-31: Reserved */
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/* CAN0/1 Sleep Clear Register */
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@@ -42,6 +42,10 @@
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#include <nuttx/config.h>
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/* This file is only a thin shell that includes the correct memory map definitions
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* for the selected LPC17xx family.
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*/
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#include <arch/lpc17xx/chip.h>
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#if defined(LPC176x)
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@@ -42,6 +42,10 @@
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#include <nuttx/config.h>
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/* This file is only a thin shell that includes the correct pin configuration
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* definitions for the selected LPC17xx family.
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*/
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#include <arch/lpc17xx/chip.h>
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#if defined(LPC176x)
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@@ -42,6 +42,10 @@
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#include <nuttx/config.h>
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/* This file is only a thin shell that includes the correct pin configuration
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* register definitions for the selected LPC17xx family.
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*/
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#include <arch/lpc17xx/chip.h>
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#if defined(LPC176x)
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@@ -42,6 +42,10 @@
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#include <nuttx/config.h>
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/* This file is only a thin shell that includes the correct system controller
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* register definitions for the selected LPC17xx family.
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*/
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#include <arch/lpc17xx/chip.h>
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#if defined(LPC176x)
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@@ -0,0 +1,221 @@
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_clockconfig.c
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* arch/arm/src/chip/lpc17_clockconfig.c
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*
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* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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||||
*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "lpc17_clockconfig.h"
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#include "chip/lpc17_syscon.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef LPC176x
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# error "The logic in this file applies only to the LPC176x family"
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Name: lpc17_clockconfig
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*
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* Description:
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* Called to initialize the LPC176x. This does whatever setup is needed to put the
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* SoC in a usable state. This includes the initialization of clocking using the
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* settings in board.h.
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*
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* The LPC176x and LPC178x system control block is *nearly* identical but we have
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* found that the LPC178x is more sensitive to the ordering of certain operations.
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* So, although the hardware seems very similar, the safer thing to do is to
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* separate the LPC176x and LPC178x into separate files.
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*
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************************************************************************************/
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void lpc17_clockconfig(void)
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{
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/* Enable the main oscillator (or not) and the frequency range of the main oscillator */
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putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS);
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/* Wait for the main oscillator to be ready. */
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#ifdef CONFIG_LPC17_MAINOSC
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while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
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#endif
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/* Setup up the divider value for the CPU clock. The output of the divider is CCLK.
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* The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK
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* will be further divided to produce peripheral clocks, but that peripheral clock
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* setup is performed in the peripheral device drivers. Here only CCLK is
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* configured.
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*/
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putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG);
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/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
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#ifdef CONFIG_LPC17_PLL0
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/* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
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* a special "feed" sequence must be written to the PLL0FEED register in order
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* for changes to the PLL0CFG register to take effect.
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*/
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putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL);
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putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
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* PLL0FEED register in order for changes to the PLL0CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL0 to lock */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
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/* Enable and connect PLL0 */
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putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC))
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!= (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC));
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#endif /* CONFIG_LPC17_PLL0 */
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/* PLL1 receives its clock input from the main oscillator only and can be used to
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* provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be
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* obtained from PLL0).
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*/
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#ifdef CONFIG_LPC17_PLL1
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/* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed"
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* sequence must be written to the PLL1FEED register in order for changes to the
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* PLL1CFG register to take effect.
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*/
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putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
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* PLL1FEED register in order for changes to the PLL1CON register to take effect.
|
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL1 to lock */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
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/* Enable and connect PLL1 */
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putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC))
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!= (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC));
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#else /* CONFIG_LPC17_PLL1 */
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/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
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putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG);
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#endif /* CONFIG_LPC17_PLL1 */
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/* Disable all peripheral clocks. They must be configured by each device driver
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* when the device driver is initialized.
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*/
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putreg32(0, LPC17_SYSCON_PCLKSEL0);
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putreg32(0, LPC17_SYSCON_PCLKSEL1);
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/* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered
|
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* one at a time by each device driver when the driver is initialized.
|
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*/
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putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP);
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/* Disable CLKOUT */
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putreg32(0, LPC17_SYSCON_CLKOUTCFG);
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/* Configure FLASH */
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#ifdef CONFIG_LPC17_FLASH
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putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
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#endif
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}
|
||||
|
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@@ -0,0 +1,233 @@
|
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/****************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc17_clockconfig.c
|
||||
* arch/arm/src/chip/lpc17_clockconfig.c
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "lpc17_clockconfig.h"
|
||||
#include "chip/lpc17_syscon.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef LPC178x
|
||||
# error "The logic in this file applies only to the LPC178x family"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc17_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the LPC17xx. This does whatever setup is needed to put the
|
||||
* SoC in a usable state. This includes the initialization of clocking using the
|
||||
* settings in board.h.
|
||||
*
|
||||
* The LPC176x and LPC178x system control block is *nearly* identical but we have
|
||||
* found that the LPC178x is more sensitive to the ordering of certain operations.
|
||||
* So, although the hardware seems very similar, the safer thing to do is to
|
||||
* separate the LPC176x and LPC178x into separate files.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc17_clockconfig(void)
|
||||
{
|
||||
/* TODO:
|
||||
*
|
||||
* (1) "Make sure that the PLL output is not already being used. The CCLKSEL,
|
||||
* USBCLKSEL, and SPIFICLKSEL registers must not select the PLL being set up.
|
||||
* Clock dividers included in these registers may also be set up at this time
|
||||
* if writing to any of the noted registers."
|
||||
*
|
||||
* (2) "If the main PLL is being set up, and the main clock source is being changed
|
||||
* (IRC versus main oscillator), change this first by writing the correct
|
||||
* value to the CLKSRCSEL register."
|
||||
*
|
||||
* This is not an issue now because we only setup the clocks on power up, so the
|
||||
* PLL cannot be the select source. However, this could be an issue at some point
|
||||
* later when, for example, we may want to implement reduced power mode with other
|
||||
* clocking.
|
||||
*/
|
||||
|
||||
/* Enable the main oscillator (or not) and the frequency range of the main oscillator */
|
||||
|
||||
putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS);
|
||||
|
||||
/* Wait for the main oscillator to be ready. */
|
||||
|
||||
#ifdef CONFIG_LPC17_MAINOSC
|
||||
while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
|
||||
#endif
|
||||
|
||||
/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
|
||||
|
||||
#ifdef CONFIG_LPC17_PLL0
|
||||
/* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to the
|
||||
* PLLE bit in the PLLCON register. Perform a PLL feed sequence by writing
|
||||
* first the value 0xAA, then the value 0x55 to the PLLFEED register"
|
||||
*
|
||||
* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
|
||||
* a special "feed" sequence must be written to the PLL0FEED register in order
|
||||
* for changes to the PLL0CFG register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL);
|
||||
putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG);
|
||||
putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON);
|
||||
|
||||
/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
|
||||
* PLL0FEED register in order for changes to the PLL0CON register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL0FEED);
|
||||
|
||||
/* (4) "Set up the necessary clock dividers. These may include the CCLKSEL,
|
||||
* PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers.
|
||||
*/
|
||||
|
||||
putreg32(BOARD_CCLKSEL_VALUE, LPC17_SYSCON_CCLKSEL);
|
||||
putreg32(BOARD_PCLKDIV, LPC17_SYSCON_PCLKSEL);
|
||||
|
||||
#ifdef CONFIG_LPC17_EMC
|
||||
putreg32(BOARD_EMCCLKSEL_VALUE, LPC17_SYSCON_EMCCLKSEL);
|
||||
#endif
|
||||
#if defined(CONFIG_LPC17_USBDEV) || defined(CONFIG_LPC17_USBHOST)
|
||||
putreg32(BOARD_USBCLKSEL_VALUE, LPC17_SYSCON_USBCLKSEL);
|
||||
#endif
|
||||
#ifdef CONFIG_LPC17_SPIFI
|
||||
putreg32(BOARD_SPIFICLKSEL_VALUE, LPC17_SPIFICLKSEL_CCLKSEL);
|
||||
#endif
|
||||
|
||||
/* (5) "Wait for the PLL to lock. This may be accomplished by polling the
|
||||
* PLLSTAT register and testing for PLOCK = 1, or by using the PLL lock
|
||||
* interrupt.Wait for PLL0 to lock.
|
||||
*/
|
||||
|
||||
while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
|
||||
|
||||
/* (6) "Connect the PLL by selecting its output in the appropriate places. This
|
||||
* may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers.
|
||||
*/
|
||||
|
||||
#endif /* CONFIG_LPC17_PLL0 */
|
||||
|
||||
/* PLL1 receives its clock input from the main oscillator only and can be used to
|
||||
* provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be
|
||||
* obtained from PLL0).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_PLL1
|
||||
/* (3) "Write PLL new setup values to the PLLCFG register. Write a 1 to the
|
||||
* PLLE bit in the PLLCON register. Perform a PLL feed sequence by writing
|
||||
* first the value 0xAA, then the value 0x55 to the PLLFEED register"
|
||||
*
|
||||
* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed"
|
||||
* sequence must be written to the PLL1FEED register in order for changes to the
|
||||
* PLL1CFG register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG);
|
||||
putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON);
|
||||
|
||||
/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
|
||||
* PLL1FEED register in order for changes to the PLL1CON register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL1FEED);
|
||||
|
||||
/* (4) "Set up the necessary clock dividers. These may include the CCLKSEL,
|
||||
* PCLKSEL, EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers.
|
||||
*/
|
||||
|
||||
/* (5) "Wait for the PLL to lock. This may be accomplished by polling the
|
||||
* PLLSTAT register and testing for PLOCK = 1, or by using the PLL lock
|
||||
* interrupt.Wait for PLL0 to lock.
|
||||
*/
|
||||
|
||||
while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
|
||||
|
||||
/* (6) "Connect the PLL by selecting its output in the appropriate places. This
|
||||
* may include the CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers.
|
||||
*/
|
||||
|
||||
#endif /* CONFIG_LPC17_PLL1 */
|
||||
|
||||
/* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered
|
||||
* one at a time by each device driver when the driver is initialized.
|
||||
*/
|
||||
|
||||
putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP);
|
||||
|
||||
/* Disable CLKOUT */
|
||||
|
||||
putreg32(0, LPC17_SYSCON_CLKOUTCFG);
|
||||
|
||||
/* Configure FLASH */
|
||||
|
||||
#ifdef CONFIG_LPC17_FLASH
|
||||
putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -40,16 +40,28 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
/* This file is only a thin shell that includes the correct clock
|
||||
* configuration logic for the selected LPC17xx family. The correct file
|
||||
* cannot be selected by the make system because it needs the intelligence
|
||||
* that only exists in chip.h that can associate an LPC17xx part number with
|
||||
* an LPC17xx family.
|
||||
*
|
||||
* The LPC176x and LPC178x system control block is *nearly* identical but
|
||||
* we have found that the LPC178x is more sensitive to the ordering of
|
||||
* certain operations. So, although the hardware seems very similar, the
|
||||
* safer thing to do is to separate the LPC176x and LPC178x into separate
|
||||
* files.
|
||||
*/
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
#include <arch/lpc17xx/chip.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "lpc17_clockconfig.h"
|
||||
#include "chip/lpc17_syscon.h"
|
||||
#if defined(LPC176x)
|
||||
# include "chip/lpc176x_clockconfig.c"
|
||||
#elif defined(LPC178x)
|
||||
# include "chip/lpc178x_clockconfig.c"
|
||||
#else
|
||||
# error "Unrecognized LPC17xx family"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -70,156 +82,3 @@
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc17_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the LPC17xx. This does whatever setup is needed to put the
|
||||
* SoC in a usable state. This includes the initialization of clocking using the
|
||||
* settings in board.h.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc17_clockconfig(void)
|
||||
{
|
||||
/* Enable the main oscillator (or not) and the frequency range of the main oscillator */
|
||||
|
||||
putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS);
|
||||
|
||||
/* Wait for the main oscillator to be ready. */
|
||||
|
||||
#ifdef CONFIG_LPC17_MAINOSC
|
||||
while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
|
||||
#endif
|
||||
|
||||
/* Setup up the divider value for the CPU clock. The output of the divider is CCLK.
|
||||
* The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK
|
||||
* will be further divided to produce peripheral clocks, but that peripheral clock
|
||||
* setup is performed in the peripheral device drivers. Here only CCLK is
|
||||
* configured.
|
||||
*/
|
||||
|
||||
putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG);
|
||||
|
||||
/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
|
||||
|
||||
#ifdef CONFIG_LPC17_PLL0
|
||||
/* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
|
||||
* a special "feed" sequence must be written to the PLL0FEED register in order
|
||||
* for changes to the PLL0CFG register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL);
|
||||
putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG);
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL0FEED);
|
||||
|
||||
/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
|
||||
* PLL0FEED register in order for changes to the PLL0CON register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON);
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL0FEED);
|
||||
|
||||
/* Wait for PLL0 to lock */
|
||||
|
||||
while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
|
||||
|
||||
# if defined(LPC176x)
|
||||
/* Enable and connect PLL0 */
|
||||
|
||||
putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL0FEED);
|
||||
|
||||
/* Wait for PLL to report that it is connected and enabled */
|
||||
|
||||
while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC))
|
||||
!= (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC));
|
||||
|
||||
# endif /* LPC176x */
|
||||
#endif /* CONFIG_LPC17_PLL0 */
|
||||
|
||||
/* PLL1 receives its clock input from the main oscillator only and can be used to
|
||||
* provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be
|
||||
* obtained from PLL0).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_PLL1
|
||||
/* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed"
|
||||
* sequence must be written to the PLL1FEED register in order for changes to the
|
||||
* PLL1CFG register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG);
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL1FEED);
|
||||
|
||||
/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
|
||||
* PLL1FEED register in order for changes to the PLL1CON register to take effect.
|
||||
*/
|
||||
|
||||
putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON);
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL1FEED);
|
||||
|
||||
/* Wait for PLL1 to lock */
|
||||
|
||||
while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
|
||||
|
||||
# if defined(LPC176x)
|
||||
/* Enable and connect PLL1 */
|
||||
|
||||
putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
|
||||
putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
|
||||
putreg32(0x55, LPC17_SYSCON_PLL1FEED);
|
||||
|
||||
/* Wait for PLL to report that it is connected and enabled */
|
||||
|
||||
while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC))
|
||||
!= (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC));
|
||||
|
||||
# endif
|
||||
#else /* CONFIG_LPC17_PLL1 */
|
||||
|
||||
/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
|
||||
|
||||
#ifdef LPC176x
|
||||
putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG);
|
||||
#endif
|
||||
#endif /* CONFIG_LPC17_PLL1 */
|
||||
|
||||
/* Disable all peripheral clocks. They must be configured by each device driver
|
||||
* when the device driver is initialized.
|
||||
*/
|
||||
|
||||
#ifdef LPC176x
|
||||
putreg32(0, LPC17_SYSCON_PCLKSEL0);
|
||||
putreg32(0, LPC17_SYSCON_PCLKSEL1);
|
||||
#endif
|
||||
|
||||
/* Set the peripheral clock (PCLK) divider that is used by all APB peripherals. */
|
||||
|
||||
#ifdef LPC178x
|
||||
putreg32(BOARD_PCLKDIV, LPC17_SYSCON_PCLKSEL);
|
||||
#endif
|
||||
|
||||
/* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered
|
||||
* one at a time by each device driver when the driver is initialized.
|
||||
*/
|
||||
|
||||
putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP);
|
||||
|
||||
/* Disable CLKOUT */
|
||||
|
||||
putreg32(0, LPC17_SYSCON_CLKOUTCFG);
|
||||
|
||||
/* Configure FLASH */
|
||||
|
||||
#ifdef CONFIG_LPC17_FLASH
|
||||
putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -855,7 +855,7 @@ static inline uint32_t lpc17_uartdl(uint32_t baud, uint8_t divcode)
|
||||
#else
|
||||
static inline uint32_t lpc17_uartdl(uint32_t baud)
|
||||
{
|
||||
return (uint32_t)BOARD_PCLK / (baud << 4);
|
||||
return (uint32_t)BOARD_PCLK_FREQUENCY / (baud << 4);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user