mirror of
https://github.com/apache/nuttx.git
synced 2026-09-21 13:25:12 +08:00
Squashed commit of the following:
arch/arm/src/imxrt: Add structures to support list of TCDs for Scatter/Gather DMA.
arch/arm/src/imxrt: Add eDMA imxrt_dmach_initconfig().
arch/arm/src/imxrt: Add eDMA imxrt_tcd_instantiate().
arch/arm/src/imxrt: Replacing some of the logic cloned from SAMv7 XDMAC with eDMA logic from NXP sample code. I am thinking that the eDMA is too complex to force into the same pattern as for other MCUs.
arch/arms/src/imxrt/imxrt_edma.c: Add support for in-memory TCDs.
arch/arm/src/imxrt/chip: Add an in-memory representation of the TCD in imxrt_edma.h
This commit is contained in:
Gregory Nutt
@@ -337,25 +337,61 @@ endmenu # Memory Configuration
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menu "eDMA Configuration"
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depends on IMXRT_EDMA
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config IMXRT_EDMA_NTCD
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int "Number of transfer descriptors"
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default 0
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---help---
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Number of pre-allocated transfer descriptors. Needed for scatter-
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gather DMA. Make to be set to zero to disable in-memory TCDs in
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which case only the TCD channel registers will be used and scatter-
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will not be supported.
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config IMXRT_EDMA_ERCA
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bool "Round Robin Channel Arbitration"
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default n
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---help---
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Normally, a fixed priority arbitration is used for channel
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selection. If this option is selected, round robin arbitration is
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used for channel selection.
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config IMXRT_EDMA_HOE
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bool "Halt On Error"
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default y
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---help---
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Any error causes the HALT bit to set. Subsequently, all service
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requests are ignored until the HALT bit is cleared.
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config IMXRT_EDMA_CLM
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bool "Continuous Link Mode"
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default n
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---help---
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By default, A minor loop channel link made to itself goes through
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channel arbitration before being activated again. If this option is
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selected, a minor loop channel link made to itself does not go
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through channel arbitration before being activated again. Upon minor
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loop completion, the channel activates again if that channel has a
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minor loop channel link enabled and the link channel is itself. This
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effectively applies the minor loop offsets and restarts the next
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minor loop.
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config IMXRT_EDMA_EMLIM
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bool "Minor Loop Mapping"
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default n
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---help---
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Normally TCD word 2 is a 32-bit NBYTES field. When this option is
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enabled, TCD word 2 is redefined to include individual enable fields,
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an offset field, and the NBYTES field. The individual enable fields
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allow the minor loop offset to be applied to the source address, the
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destination address, or both. The NBYTES field is reduced when either
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offset is enabled.
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config IMXRT_EDMA_EDBG
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bool "Enable Debug"
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default n
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---help---
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When in debug mode, the DMA stalls the start of a new channel. Executing
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channels are allowed to complete. Channel execution resumes when the
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system exits debug mode or the EDBG bit is cleared
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endmenu # eDMA Global Configuration
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endif # ARCH_CHIP_IMXRT
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@@ -44,7 +44,7 @@
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#include "chip/imxrt_memorymap.h"
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/****************************************************************************************************
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* Pre-processor definitions
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* Pre-processor Definitions
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****************************************************************************************************/
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#define IMXRT_EDMA_NCHANNELS 32
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@@ -103,6 +103,8 @@
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#define IMXRT_EDMA_DCHPRI29_OFFSET 0x011e /* Channel 0 Priority */
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#define IMXRT_EDMA_DCHPRI28_OFFSET 0x011f /* Channel 1 Priority */
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/* Transfer Control Descriptor (TCD) */
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#define IMXRT_EDMA_TCD_OFFSET(n) (0x1000 + ((n) << 5))
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#define IMXRT_EDMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
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#define IMXRT_EDMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
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@@ -566,6 +568,8 @@
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#define IMXRT_EDMA_DCHPRI29 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
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#define IMXRT_EDMA_DCHPRI28 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
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/* Transfer Control Descriptor (TCD) */
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#define IMXRT_EDMA_TCD_BASE(n) (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD_OFFSET(n))
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#define IMXRT_EDMA_TCD_SADDR(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_SADDR_OFFSET)
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#define IMXRT_EDMA_TCD_SOFF(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_SOFF_OFFSET)
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@@ -1125,6 +1129,7 @@
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#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */
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#define EDMA_TCD_ATTR_DSIZE_MASK (7 << EDMA_TCD_ATTR_DSIZE_SHIFT)
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# define EDMA_TCD_ATTR_DSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
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# define EDMA_TCD_ATTR_DSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
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# define EDMA_TCD_ATTR_DSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */
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# define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
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@@ -1135,6 +1140,7 @@
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# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT)
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#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */
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#define EDMA_TCD_ATTR_SSIZE_MASK (7 << EDMA_TCD_ATTR_SSIZE_SHIFT)
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# define EDMA_TCD_ATTR_SSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
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# define EDMA_TCD_ATTR_SSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
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# define EDMA_TCD_ATTR_SSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
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# define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
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@@ -1237,4 +1243,25 @@
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#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
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* on minor-loop complete */
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/* In-memory representation of the 32-byte Transfer Control Descriptor (TCD) */
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struct imxrt_edmatcd_s
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{
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uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
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uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
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uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
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uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
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uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
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uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
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uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
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uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
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uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
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uint16_t csr; /* Offset: 0x001c TCD Control and Status */
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uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
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};
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#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H */
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+503
-16
File diff suppressed because it is too large
Load Diff
+159
-93
@@ -4,6 +4,13 @@
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Portions of the eDMA logic derive from NXP sample code which has a compatible
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* BSD 3-clause license:
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*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@@ -49,94 +56,39 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* eDMA Configuration ***************************************************************/
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/* Flags used to characterize the DMA channel. The naming convention is that one
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* side is the peripheral and the other is memory (however, the interface could still
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* be used if, for example, both sides were memory although the naming would be
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* awkward)
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*
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* .... .... .... .... CCCC GGBA DDSS ..TT
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*
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* REVISIT: Initially, only vanilla Rx/Tx DMA block transfers are supported.
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*/
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/* Transfer type:
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*
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* .... .... .... .... .... .... .... ..TT
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*/
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#define TTYPE_M2M (0) /* Memory-to-memory (not supported) */
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#define TTYPE_M2P (1) /* Memory-to-peripheral (normal Tx) */
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#define TTYPE_P2M (2) /* Peripheral-to-memory (normal Rx) */
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#define TTYPE_P2P (3) /* Peripheral-to-peripheral (not supported) */
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#define TTYPE_2P_MASK (1) /* Transfer to peripheral (M2P or P2P) */
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#define TTYPE_P2_MASK (2) /* Transfer from peripheral (P2M or P2P) */
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#define DMACH_FLAG_TTYPE_SHIFT (0) /* Bits 0-1 Destination transfer size */
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#define DMACH_FLAG_TTYPE_MASK (3 << DMACH_FLAG_TTYPE_SHIFT)
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# define DMACH_FLAG_TTYPE_M2M (TTYPE_M2M << DMACH_FLAG_TTYPE_SHIFT) /* Memory-to-memory */
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# define DMACH_FLAG_TTYPE_M2P (TTYPE_M2P << DMACH_FLAG_TTYPE_SHIFT) /* Memory-to-peripheral */
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# define DMACH_FLAG_TTYPE_P2M (TTYPE_P2M << DMACH_FLAG_TTYPE_SHIFT) /* Peripheral-to-memory */
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# define DMACH_FLAG_TTYPE_P2P (TTYPE_P2P << DMACH_FLAG_TTYPE_SHIFT) /* Peripheral-to-peripheral */
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# define DMACH_FLAG_TTYPE_2P_MASK (TTYPE_2P_MASK << DMACH_FLAG_TTYPE_SHIFT) /* Transfer to peripheral */
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# define DMACH_FLAG_TTYPE_P2_MASK (TTYPE_P2_MASK << DMACH_FLAG_TTYPE_SHIFT) /* Transfer from peripheral */
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/* Source transfer size:
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*
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* .... .... .... .... .... .... ..SS ....
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*/
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#define DMACH_FLAG_SSIZE_SHIFT (4) /* Bits 4-5: Source transfer size */
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#define DMACH_FLAG_SSIZE_MASK (7 << DMACH_FLAG_SSIZE_SHIFT)
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# define DMACH_FLAG_SSIZE_8BIT (TCD_ATTR_SIZE_8BIT << DMACH_FLAG_SSIZE_SHIFT) /* 8-bit */
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# define DMACH_FLAG_SSIZE_16BIT (TCD_ATTR_SIZE_16BIT << DMACH_FLAG_SSIZE_SHIFT) /* 16-bit */
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# define DMACH_FLAG_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << DMACH_FLAG_SSIZE_SHIFT) /* 32-bit */
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# define DMACH_FLAG_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << DMACH_FLAG_SSIZE_SHIFT) /* 64-bit */
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# define DMACH_FLAG_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << DMACH_FLAG_SSIZE_SHIFT) /* 32-byte burst */
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/* Destination transfer size:
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*
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* .... .... .... .... .... .... DD.. ....
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*/
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#define DMACH_FLAG_DSIZE_SHIFT (6) /* Bits 6-7: Destination transfer size */
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#define DMACH_FLAG_DSIZE_MASK (7 << DMACH_FLAG_DSIZE_SHIFT)
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# define DMACH_FLAG_DSIZE_8BIT (TCD_ATTR_SIZE_8BIT << DMACH_FLAG_DSIZE_SHIFT) /* 8-bit */
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# define DMACH_FLAG_DSIZE_16BIT (TCD_ATTR_SIZE_16BIT << DMACH_FLAG_DSIZE_SHIFT) /* 16-bit */
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# define DMACH_FLAG_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << DMACH_FLAG_DSIZE_SHIFT) /* 32-bit */
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# define DMACH_FLAG_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << DMACH_FLAG_DSIZE_SHIFT) /* 64-bit */
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# define DMACH_FLAG_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << DMACH_FLAG_DSIZE_SHIFT) /* 32-byte burst */
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/* Arbitration:
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*
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* .... .... .... .... .... ..BA .... ....
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*/
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#define DMACH_FLAG_CHRR (1 << 8) /* Bit 8: Round Robin Channel Arbitration */
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#define DMACH_FLAG_GRPRR (1 << 8) /* Bit 9: Round Robin Group Arbitration */
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/* DMA Priorities:
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*
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* .... .... .... .... CCCC GG.. .... ....
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*/
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#define DMACH_FLAG_GPPRI_SHIFT (10) /* Bits 10-11: Channel Group Priority */
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#define DMACH_FLAG_GRPPRI_MASK (3 << DMACH_FLAG_GPPRI_SHIFT)
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# define DMACH_FLAG_GRPPRI(n) ((uint32_t)(n) << DMACH_FLAG_GPPRI_SHIFT)
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#define DMACH_FLAG_CHPRI_SHIFT (12) /* Bits 12-15: Channel Arbitration Priority */
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#define DMACH_FLAG_CHPRI_MASK (15 << DMACH_FLAG_CHPRI_SHIFT)
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# define DMACH_FLAG_CHPRI(n) ((uint32_t)(n) << DMACH_FLAG_CHPRI_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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typedef FAR void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
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typedef FAR void *DMACH_HANDLE;
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typedef void (*dma_callback_t)(DMACH_HANDLE handle, void *arg, int result);
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/* eDMA transfer type */
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enum imxrt_edma_xfrtype_e
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{
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eDMA_MEMORY2MEMORY = 0, /* Transfer from memory to memory */
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eDMA_PERIPH2MEMORY, /* Transfer from peripheral to memory */
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eDMA_MEMORY2PERIPH, /* Transfer from memory to peripheral */
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};
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/* This structure holds the source/destination transfer attribute configuration. */
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struct imxrt_edma_xfrconfig_s
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{
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uint32_t saddr; /* Source data address. */
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uint32_t daddr; /* Destination data address. */
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uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in chip/. */
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uint8_t dsize; /* Destination data transfer size. */
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int16_t soff; /* Sign-extended offset for current source address. */
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int16_t doff; /* Sign-extended offset for current destination address. */
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uint16_t iter; /* Major loop iteration count. */
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#ifdef CONFIG_IMXRT_EDMA_EMLIM
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uint16_t nbytes; /* Bytes to transfer in a minor loop */
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#else
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uint32_t nbytes; /* Bytes to transfer in a minor loop */
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#endif
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};
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/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
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@@ -202,7 +154,7 @@ extern "C"
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* Public Function Prototypes
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************************************************************************************/
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/****************************************************************************
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/************************************************************************************
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* Name: imxrt_dmachannel
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*
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* Allocate a DMA channel. This function sets aside a DMA channel,
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@@ -224,9 +176,9 @@ extern "C"
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* If a DMA channel is available, this function returns a non-NULL, void*
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* DMA channel handle. NULL is returned on any failure.
|
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*
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****************************************************************************/
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************************************************************************************/
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|
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DMA_HANDLE imxrt_dmachannel(uint32_t dmamux);
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DMACH_HANDLE imxrt_dmachannel(uint32_t dmamux);
|
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|
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/************************************************************************************
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* Name: imxrt_dmafree
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@@ -240,7 +192,121 @@ DMA_HANDLE imxrt_dmachannel(uint32_t dmamux);
|
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*
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************************************************************************************/
|
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|
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void imxrt_dmafree(DMA_HANDLE handle);
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void imxrt_dmafree(DMACH_HANDLE handle);
|
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|
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/****************************************************************************
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* Name: imxrt_tcd_alloc
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*
|
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* Description:
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* Allocate an in-memory, TCD
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*
|
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****************************************************************************/
|
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#if CONFIG_IMXRT_EDMA_NTCD > 0
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struct imxrt_edmatcd_s *imxrt_tcd_alloc(void);
|
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#endif
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|
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/****************************************************************************
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* Name: imxrt_tcd_free()
|
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*
|
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* Description:
|
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* Free an in-memory, TCD
|
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*
|
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****************************************************************************/
|
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|
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#if CONFIG_IMXRT_EDMA_NTCD > 0
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void imxrt_tcd_free(struct imxrt_edmatcd_s *tcd);
|
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#endif
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|
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/************************************************************************************
|
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* Name: imxrt_dmach_reset
|
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*
|
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* Description:
|
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* Sets all TCD registers to default values..
|
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*
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* NOTE: This function enables the auto stop request feature.
|
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*
|
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************************************************************************************/
|
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|
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void imxrt_dmach_reset(DMACH_HANDLE handle);
|
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|
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/*******************************************************************************
|
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* Name: imxrt_dmach_initconfig
|
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*
|
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* Description:
|
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* This function initializes the transfer configuration structure according
|
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* to the user-provided input configuration.
|
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*
|
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* Input Parameters:
|
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* saddr - eDMA transfer source address.
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* srcwidth - eDMA transfer source address width(bytes).
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* daddr - eDMA transfer destination address.
|
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* destwidth - eDMA transfer destination address width(bytes).
|
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* reqsize - eDMA transfer bytes per channel request.
|
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* nbytes - eDMA transfer bytes to be transferred.
|
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* type - eDMA transfer type.
|
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* config - The user configuration structure of type struct
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* imxrt_edma_xfrconfig_s.
|
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*
|
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* NOTE: The data address and the data width must be consistent. For example,
|
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* if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it
|
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* results in source address error (SAE).
|
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*
|
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* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure.
|
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*
|
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******************************************************************************/
|
||||
|
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int imxrt_dmach_initconfig(void *saddr, uint32_t srcwidth,
|
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void *daddr, uint32_t destwidth,
|
||||
uint32_t reqsize, uint32_t nbytes,
|
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edma_transfer_type_t type,
|
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struct imxrt_edma_xfrconfig_s *config);
|
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|
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/*******************************************************************************
|
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* Name: imxrt_dmach_setconfig
|
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*
|
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* Description:
|
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* This function configures the transfer attribute, including source address,
|
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* destination address, transfer size, address offset, and so on. It also
|
||||
* configures the scatter gather feature if the user supplies the TCD address.
|
||||
*
|
||||
* Example:
|
||||
*
|
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* edma_transfer_t config;
|
||||
* struct imxrt_edmatcd_s tcd;
|
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* config.saddr = ..;
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* config.daddr = ..;
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* ...
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* dmach = imxrt_dmachannel(dmamux);
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* ...
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* tcd = imxrt_tcd_alloc(dmach)
|
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* ...
|
||||
* imxrt_dmach_setconfig(dmach, &config, &tcd);
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - DMA channel handle created by imxrt_dmachannel()
|
||||
* channel - eDMA channel number.
|
||||
* config - Pointer to eDMA transfer configuration structure.
|
||||
* next - Points to a TCD structure previously allocated via
|
||||
* imxrt_tcd_alloc(). 'next' can be NULL if the caller does not
|
||||
* wish to enable scatter/gather feature.
|
||||
*
|
||||
* NOTE: If 'next' is not NULL, it means scatter gather feature is enabled
|
||||
* and DREQ bit is cleared in the previous transfer configuration.
|
||||
* That bit was set in imxrt_dmach_reset().
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef CONFIG_IMXRT_EDMA_NTCD > 0
|
||||
void imxrt_dmach_setconfig(DMACH_HANDLE handle,
|
||||
const struct imxrt_edma_xfrconfig_s *config,
|
||||
struct imxrt_edmatcd_s *next);
|
||||
#else
|
||||
void imxrt_dmach_setconfig(DMACH_HANDLE handle,
|
||||
const struct imxrt_edma_xfrconfig_s *config);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_dmasetup
|
||||
@@ -254,8 +320,8 @@ void imxrt_dmafree(DMA_HANDLE handle);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int imxrt_dmasetup(DMA_HANDLE handle, uint32_t saddr, uint32_t daddr, size_t nbytes,
|
||||
uint32_t chflags);
|
||||
int imxrt_dmasetup(DMACH_HANDLE handle, uint32_t saddr, uint32_t daddr,
|
||||
size_t nbytes, uint32_t chflags);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_dmastart
|
||||
@@ -265,7 +331,7 @@ int imxrt_dmasetup(DMA_HANDLE handle, uint32_t saddr, uint32_t daddr, size_t nby
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int imxrt_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
|
||||
int imxrt_dmastart(DMACH_HANDLE handle, dma_callback_t callback, void *arg);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_dmastop
|
||||
@@ -276,7 +342,7 @@ int imxrt_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void imxrt_dmastop(DMA_HANDLE handle);
|
||||
void imxrt_dmastop(DMACH_HANDLE handle);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_dmasample
|
||||
@@ -287,7 +353,7 @@ void imxrt_dmastop(DMA_HANDLE handle);
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void imxrt_dmasample(DMA_HANDLE handle, struct imxrt_dmaregs_s *regs);
|
||||
void imxrt_dmasample(DMACH_HANDLE handle, struct imxrt_dmaregs_s *regs);
|
||||
#else
|
||||
# define imxrt_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
@@ -1598,6 +1598,12 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
|
||||
|
||||
nxsem_init(&xdmac->chsem, 0, 1);
|
||||
nxsem_init(&xdmac->dsem, 0, SAMV7_NDMACHAN);
|
||||
|
||||
/* The 'dsem' is used for signaling rather than mutual exclusion and,
|
||||
* hence, should not have priority inheritance enabled.
|
||||
*/
|
||||
|
||||
nxsem_setprotocol(&xdmac->dsem, SEM_PRIO_NONE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
Reference in New Issue
Block a user