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Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #63)
Upstream_nucleo 144
This commit is contained in:
Gregory Nutt
@@ -2,7 +2,8 @@
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* arch/arm/include/stm32f7/chip.h
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*
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -478,7 +478,7 @@
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# define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
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# define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
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# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
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# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
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# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
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# endif
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#else
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@@ -1666,7 +1666,6 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
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priv->current = 0;
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}
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}
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}
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/* Restart DMA for the next conversion series */
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+2812
-11
File diff suppressed because it is too large
Load Diff
@@ -151,11 +151,11 @@ ifeq ($(CONFIG_STM32F7_TIM),y)
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CHIP_CSRCS += stm32_tim.c
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endif
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ifeq ($(CONFIG_ADC),y)
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ifeq ($(CONFIG_STM32F7_ADC),y)
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CHIP_CSRCS += stm32_adc.c
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endif
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ifeq ($(CONFIG_RTC),y)
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ifeq ($(CONFIG_STM32F7_RTC),y)
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ifeq ($(CONFIG_RTC_ALARM),y)
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CHIP_CSRCS += stm32_exti_alarm.c
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endif
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@@ -2,7 +2,8 @@
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* arch/arm/src/stm32f7/chip/stm32_adc.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -33,8 +34,8 @@
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
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#define __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
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/****************************************************************************************************
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* Included Files
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@@ -44,452 +45,14 @@
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#include "chip.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/* Register Offsets *********************************************************************************/
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#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
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#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
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#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
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#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
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#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
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#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
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#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
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#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
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#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
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#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
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#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
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#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
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#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
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#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
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#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
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#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
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#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
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#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
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#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
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#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
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#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
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#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
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#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
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/* Register Addresses *******************************************************************************/
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#if STM32F7_NADC > 0
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# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
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# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
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# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
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# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
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# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
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# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
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# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
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# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
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# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
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# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
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# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
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# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
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# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
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# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
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# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
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# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
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# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
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# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
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# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
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# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
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defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "chip/stm32f74xx77xx_adc.h"
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#else
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# error "Unsupported STM32 F7 sub family"
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#endif
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#if STM32F7_NADC > 1
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# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
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# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
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# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
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# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
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# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
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# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
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# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
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# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
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# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
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# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
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# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
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# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
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# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
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# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
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# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
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# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
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# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
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# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
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# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
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# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
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#endif
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#if STM32F7_NADC > 2
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# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
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# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
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# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
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# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
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# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
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# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
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# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
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# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
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# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
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# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
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# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
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# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
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# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
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# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
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# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
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# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
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# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
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# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
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# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
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# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
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#endif
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#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
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#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
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#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
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/* Register Bitfield Definitions ********************************************************************/
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/* ADC status register */
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#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
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#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
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#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
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#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
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#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
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#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
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/* ADC control register 1 */
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#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
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#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
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#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
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#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
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#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
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#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
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#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
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#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
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#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
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#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
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#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
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#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
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#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
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#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
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#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
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#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
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#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
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#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
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#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
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#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
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#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
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/* ADC control register 2 */
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#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
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#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
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#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
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#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
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#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
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#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
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/* Bits 12-15: Reserved */
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#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
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#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
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#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
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#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
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#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
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#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
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#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
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#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
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/* 0110: NA */
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#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
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#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
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#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
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#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
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#define ADC_CR2_JEXTSEL_T3CC3 (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
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#define ADC_CR2_JEXTSEL_T5TRGO (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
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#define ADC_CR2_JEXTSEL_T3CC1 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
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#define ADC_CR2_JEXTSEL_T6TRGO (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
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/* 1111: NA */
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#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
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#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
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#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
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#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
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#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
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#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
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#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
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/* Bit 23: Reserved, must be kept at reset value. */
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#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
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#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
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#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
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#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
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#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
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#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
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#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
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||||
#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
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#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
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||||
#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
|
||||
#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T1TRGO2 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
|
||||
#define ADC_CR2_EXTSEL_T2TRGO (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T4TRGO (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T6TRGO (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
|
||||
/* 1110: NA */
|
||||
#define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
|
||||
|
||||
#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
|
||||
#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
|
||||
#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
|
||||
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#define ADC_SMPR_3 0 /* 000: 3 cycles */
|
||||
#define ADC_SMPR_15 1 /* 001: 15 cycles */
|
||||
#define ADC_SMPR_28 2 /* 010: 28 cycles */
|
||||
#define ADC_SMPR_56 3 /* 011: 56 cycles */
|
||||
#define ADC_SMPR_84 4 /* 100: 84 cycles */
|
||||
#define ADC_SMPR_112 5 /* 101: 112 cycles */
|
||||
#define ADC_SMPR_144 6 /* 110: 144 cycles */
|
||||
#define ADC_SMPR_480 7 /* 111: 480 cycles */
|
||||
|
||||
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
|
||||
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
|
||||
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
|
||||
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
|
||||
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
|
||||
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
|
||||
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
|
||||
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
|
||||
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
|
||||
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
|
||||
|
||||
|
||||
/* ADC injected channel data offset register 1-4 */
|
||||
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_RESERVED (0xff000000)
|
||||
#define ADC_SQR1_FIRST (13)
|
||||
#define ADC_SQR1_LAST (16)
|
||||
#define ADC_SQR1_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
|
||||
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
#define ADC_SQR2_RESERVED (0xc0000000)
|
||||
#define ADC_SQR2_FIRST (7)
|
||||
#define ADC_SQR2_LAST (12)
|
||||
#define ADC_SQR2_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
|
||||
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
#define ADC_SQR3_RESERVED (0xc0000000)
|
||||
#define ADC_SQR3_FIRST (1)
|
||||
#define ADC_SQR3_LAST (6)
|
||||
#define ADC_SQR3_SQ_OFFSET (0)
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (5)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1-4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
|
||||
/* Common status register */
|
||||
|
||||
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
|
||||
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
|
||||
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
|
||||
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
|
||||
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
|
||||
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
|
||||
|
||||
#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
|
||||
#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
|
||||
#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
|
||||
#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
|
||||
#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
|
||||
#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
|
||||
/* Bits 14-15: Reserved, must be kept at reset value. */
|
||||
#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
|
||||
#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
|
||||
#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
|
||||
#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
|
||||
#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
|
||||
#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
|
||||
|
||||
/* Common control register */
|
||||
|
||||
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
|
||||
# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT)
|
||||
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
|
||||
/* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
|
||||
# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
|
||||
/* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
|
||||
# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
|
||||
/* Bits 5-7: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
|
||||
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
|
||||
/* Bit 12 Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
|
||||
|
||||
# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */
|
||||
# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT)
|
||||
# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
|
||||
# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
|
||||
# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
|
||||
# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
|
||||
|
||||
# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
|
||||
# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
|
||||
# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
|
||||
# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
|
||||
# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
|
||||
# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
|
||||
/* Bits 18-21: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */
|
||||
# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
|
||||
/* Bits 24-31 Reserved, must be kept at reset value. */
|
||||
|
||||
/* Data register for dual and triple modes (32-bit data with no named fields) */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H */
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/chip/stm32_i2c.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -43,10 +44,11 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_i2c.h"
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f74xx77xx_i2c.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 part"
|
||||
# error "Unsupported STM32 F7 sub family"
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */
|
||||
|
||||
@@ -34,8 +34,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
|
||||
#define __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -44,215 +44,10 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# define STM32_SPI_CLK_MAX 50000000UL
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# define STM32_SPI_CLK_MAX 54000000UL
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f74xx77xx_spi.h"
|
||||
#else
|
||||
# error "Unsupported STM32 F7 sub family"
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
|
||||
#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 3
|
||||
# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI4_DR (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI4_CRCPR (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 4
|
||||
# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI5_DR (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI5_CRCPR (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 5
|
||||
# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI6_DR (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI6_CRCPR (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
|
||||
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
|
||||
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
|
||||
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
|
||||
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
|
||||
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
|
||||
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
|
||||
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
|
||||
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
|
||||
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
|
||||
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
|
||||
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
|
||||
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
|
||||
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
|
||||
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
|
||||
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
|
||||
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
|
||||
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
|
||||
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
|
||||
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
|
||||
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
|
||||
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
|
||||
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
|
||||
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
|
||||
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
|
||||
#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */
|
||||
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
|
||||
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
|
||||
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
|
||||
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
|
||||
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
|
||||
#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4)
|
||||
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5)
|
||||
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6)
|
||||
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7)
|
||||
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8)
|
||||
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9)
|
||||
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
|
||||
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
|
||||
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
|
||||
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
|
||||
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
|
||||
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
|
||||
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
|
||||
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
|
||||
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
|
||||
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
|
||||
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
|
||||
#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */
|
||||
#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */
|
||||
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
|
||||
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
|
||||
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
|
||||
#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT)
|
||||
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
|
||||
#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT)
|
||||
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
|
||||
|
||||
/* I2S configuration register */
|
||||
|
||||
#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
|
||||
#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
|
||||
#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
|
||||
# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */
|
||||
# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */
|
||||
# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */
|
||||
#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */
|
||||
#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */
|
||||
#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
|
||||
# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
|
||||
# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
|
||||
#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */
|
||||
#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */
|
||||
#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
|
||||
# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */
|
||||
# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */
|
||||
# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */
|
||||
# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */
|
||||
#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */
|
||||
#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */
|
||||
#define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */
|
||||
|
||||
/* I2S prescaler register */
|
||||
|
||||
#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
|
||||
#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
|
||||
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
|
||||
@@ -1,8 +1,9 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -616,7 +617,7 @@
|
||||
#define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */
|
||||
#define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT)
|
||||
# define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT)
|
||||
#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
|
||||
/* Dedicated clocks configuration register 2 */
|
||||
|
||||
|
||||
@@ -1,207 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
#define STM32F7_SPI_CLK_MAX 27000000UL
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NSPI > 0
|
||||
# define STM32F7_SPI1_CR1 (STM32_SPI1_BASE+STM32F7_SPI_CR1_OFFSET)
|
||||
# define STM32F7_SPI1_CR2 (STM32_SPI1_BASE+STM32F7_SPI_CR2_OFFSET)
|
||||
# define STM32F7_SPI1_SR (STM32_SPI1_BASE+STM32F7_SPI_SR_OFFSET)
|
||||
# define STM32F7_SPI1_DR (STM32_SPI1_BASE+STM32F7_SPI_DR_OFFSET)
|
||||
# define STM32F7_SPI1_CRCPR (STM32_SPI1_BASE+STM32F7_SPI_CRCPR_OFFSET)
|
||||
# define STM32F7_SPI1_RXCRCR (STM32_SPI1_BASE+STM32F7_SPI_RXCRCR_OFFSET)
|
||||
# define STM32F7_SPI1_TXCRCR (STM32_SPI1_BASE+STM32F7_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 1
|
||||
# define STM32F7_SPI2_CR1 (STM32_SPI2_BASE+STM32F7_SPI_CR1_OFFSET)
|
||||
# define STM32F7_SPI2_CR2 (STM32_SPI2_BASE+STM32F7_SPI_CR2_OFFSET)
|
||||
# define STM32F7_SPI2_SR (STM32_SPI2_BASE+STM32F7_SPI_SR_OFFSET)
|
||||
# define STM32F7_SPI2_DR (STM32_SPI2_BASE+STM32F7_SPI_DR_OFFSET)
|
||||
# define STM32F7_SPI2_CRCPR (STM32_SPI2_BASE+STM32F7_SPI_CRCPR_OFFSET)
|
||||
# define STM32F7_SPI2_RXCRCR (STM32_SPI2_BASE+STM32F7_SPI_RXCRCR_OFFSET)
|
||||
# define STM32F7_SPI2_TXCRCR (STM32_SPI2_BASE+STM32F7_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 2
|
||||
# define STM32F7_SPI3_CR1 (STM32_SPI3_BASE+STM32F7_SPI_CR1_OFFSET)
|
||||
# define STM32F7_SPI3_CR2 (STM32_SPI3_BASE+STM32F7_SPI_CR2_OFFSET)
|
||||
# define STM32F7_SPI3_SR (STM32_SPI3_BASE+STM32F7_SPI_SR_OFFSET)
|
||||
# define STM32F7_SPI3_DR (STM32_SPI3_BASE+STM32F7_SPI_DR_OFFSET)
|
||||
# define STM32F7_SPI3_CRCPR (STM32_SPI3_BASE+STM32F7_SPI_CRCPR_OFFSET)
|
||||
# define STM32F7_SPI3_RXCRCR (STM32_SPI3_BASE+STM32F7_SPI_RXCRCR_OFFSET)
|
||||
# define STM32F7_SPI3_TXCRCR (STM32_SPI3_BASE+STM32F7_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 3
|
||||
# define STM32F7_SPI4_CR1 (STM32_SPI4_BASE+STM32F7_SPI_CR1_OFFSET)
|
||||
# define STM32F7_SPI4_CR2 (STM32_SPI4_BASE+STM32F7_SPI_CR2_OFFSET)
|
||||
# define STM32F7_SPI4_SR (STM32_SPI4_BASE+STM32F7_SPI_SR_OFFSET)
|
||||
# define STM32F7_SPI4_DR (STM32_SPI4_BASE+STM32F7_SPI_DR_OFFSET)
|
||||
# define STM32F7_SPI4_CRCPR (STM32_SPI4_BASE+STM32F7_SPI_CRCPR_OFFSET)
|
||||
# define STM32F7_SPI4_RXCRCR (STM32_SPI4_BASE+STM32F7_SPI_RXCRCR_OFFSET)
|
||||
# define STM32F7_SPI4_TXCRCR (STM32_SPI4_BASE+STM32F7_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 4
|
||||
# define STM32F7_SPI5_CR1 (STM32_SPI5_BASE+STM32F7_SPI_CR1_OFFSET)
|
||||
# define STM32F7_SPI5_CR2 (STM32_SPI5_BASE+STM32F7_SPI_CR2_OFFSET)
|
||||
# define STM32F7_SPI5_SR (STM32_SPI5_BASE+STM32F7_SPI_SR_OFFSET)
|
||||
# define STM32F7_SPI5_DR (STM32_SPI5_BASE+STM32F7_SPI_DR_OFFSET)
|
||||
# define STM32F7_SPI5_CRCPR (STM32_SPI5_BASE+STM32F7_SPI_CRCPR_OFFSET)
|
||||
# define STM32F7_SPI5_RXCRCR (STM32_SPI5_BASE+STM32F7_SPI_RXCRCR_OFFSET)
|
||||
# define STM32F7_SPI5_TXCRCR (STM32_SPI5_BASE+STM32F7_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 5
|
||||
# define STM32F7_SPI6_CR1 (STM32_SPI6_BASE+STM32F7_SPI_CR1_OFFSET)
|
||||
# define STM32F7_SPI6_CR2 (STM32_SPI6_BASE+STM32F7_SPI_CR2_OFFSET)
|
||||
# define STM32F7_SPI6_SR (STM32_SPI6_BASE+STM32F7_SPI_SR_OFFSET)
|
||||
# define STM32F7_SPI6_DR (STM32_SPI6_BASE+STM32F7_SPI_DR_OFFSET)
|
||||
# define STM32F7_SPI6_CRCPR (STM32_SPI6_BASE+STM32F7_SPI_CRCPR_OFFSET)
|
||||
# define STM32F7_SPI6_RXCRCR (STM32_SPI6_BASE+STM32F7_SPI_RXCRCR_OFFSET)
|
||||
# define STM32F7_SPI6_TXCRCR (STM32_SPI6_BASE+STM32F7_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
|
||||
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
|
||||
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
|
||||
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
|
||||
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
|
||||
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
|
||||
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
|
||||
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
|
||||
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
|
||||
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
|
||||
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
|
||||
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
|
||||
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
|
||||
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
|
||||
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
|
||||
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
|
||||
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
|
||||
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
|
||||
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
|
||||
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
|
||||
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
|
||||
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
|
||||
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
|
||||
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
|
||||
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
|
||||
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
|
||||
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
|
||||
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
|
||||
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
|
||||
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
|
||||
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
|
||||
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_VAL(bits) (((uint32_t)(bits)-1) << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
|
||||
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
|
||||
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
|
||||
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
|
||||
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
|
||||
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
|
||||
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
|
||||
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
|
||||
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
|
||||
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
|
||||
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
|
||||
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
|
||||
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
|
||||
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
|
||||
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
|
||||
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
|
||||
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
|
||||
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
|
||||
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
|
||||
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
|
||||
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
|
||||
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
|
||||
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
|
||||
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,484 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
|
||||
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
|
||||
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
|
||||
|
||||
|
||||
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
|
||||
#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#if STM32F7_NADC > 0
|
||||
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NADC > 1
|
||||
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NADC > 2
|
||||
# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* ADC status register */
|
||||
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
|
||||
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
|
||||
#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
|
||||
#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
|
||||
#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
|
||||
#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
|
||||
#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
|
||||
#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
|
||||
#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
|
||||
#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */
|
||||
#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
|
||||
/* Bits 12-15: Reserved */
|
||||
#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
|
||||
#define ADC_CR2_JEXTSEL_MASK (0x0f << ADC_CR2_JEXTSEL_SHIFT)
|
||||
#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
|
||||
#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
|
||||
#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
|
||||
#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
|
||||
#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
|
||||
#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
|
||||
/* 0110: NA */
|
||||
#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
|
||||
#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
|
||||
#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
|
||||
#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0a << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
|
||||
#define ADC_CR2_JEXTSEL_T3CC3 (0x0b << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
|
||||
#define ADC_CR2_JEXTSEL_T5TRGO (0x0c << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
|
||||
#define ADC_CR2_JEXTSEL_T3CC1 (0x0d << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
|
||||
#define ADC_CR2_JEXTSEL_T6TRGO (0x0e << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
|
||||
/* 1111: Reserved */
|
||||
#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
|
||||
#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
|
||||
#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
|
||||
/* Bit 23: Reserved, must be kept at reset value. */
|
||||
#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
|
||||
#define ADC_CR2_EXTSEL_MASK (0x0f << ADC_CR2_EXTSEL_SHIFT)
|
||||
#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
|
||||
#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
|
||||
#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
|
||||
#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
|
||||
#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
|
||||
#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
|
||||
#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T1TRGO2 (0x0a << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
|
||||
#define ADC_CR2_EXTSEL_T2TRGO (0x0b << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T4TRGO (0x0c << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
|
||||
#define ADC_CR2_EXTSEL_T6TRGO (0x0d << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
|
||||
/* 1110: NA */
|
||||
#define ADC_CR2_EXTSEL_EXTI11 (0x0f << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
|
||||
#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
|
||||
#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
|
||||
#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
|
||||
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#define ADC_SMPR_3 0 /* 000: 3 cycles */
|
||||
#define ADC_SMPR_15 1 /* 001: 15 cycles */
|
||||
#define ADC_SMPR_28 2 /* 010: 28 cycles */
|
||||
#define ADC_SMPR_56 3 /* 011: 56 cycles */
|
||||
#define ADC_SMPR_84 4 /* 100: 84 cycles */
|
||||
#define ADC_SMPR_112 5 /* 101: 112 cycles */
|
||||
#define ADC_SMPR_144 6 /* 110: 144 cycles */
|
||||
#define ADC_SMPR_480 7 /* 111: 480 cycles */
|
||||
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */
|
||||
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
|
||||
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
|
||||
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
|
||||
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
|
||||
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
|
||||
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
|
||||
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
|
||||
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
|
||||
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
|
||||
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
|
||||
|
||||
|
||||
/* ADC injected channel data offset register 1-4 */
|
||||
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_RESERVED (0xff000000)
|
||||
#define ADC_SQR1_FIRST (13)
|
||||
#define ADC_SQR1_LAST (16)
|
||||
#define ADC_SQR1_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
|
||||
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
#define ADC_SQR2_RESERVED (0xc0000000)
|
||||
#define ADC_SQR2_FIRST (7)
|
||||
#define ADC_SQR2_LAST (12)
|
||||
#define ADC_SQR2_SQ_OFFSET (0)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
|
||||
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
#define ADC_SQR3_RESERVED (0xc0000000)
|
||||
#define ADC_SQR3_FIRST (1)
|
||||
#define ADC_SQR3_LAST (6)
|
||||
#define ADC_SQR3_SQ_OFFSET (0)
|
||||
|
||||
/* Offset between SQ bits */
|
||||
|
||||
#define ADC_SQ_OFFSET (5)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1-4 */
|
||||
|
||||
#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */
|
||||
#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT)
|
||||
|
||||
/* Common status register */
|
||||
|
||||
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
|
||||
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
|
||||
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
|
||||
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
|
||||
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
|
||||
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
|
||||
|
||||
#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
|
||||
#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
|
||||
#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
|
||||
#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
|
||||
#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
|
||||
#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
|
||||
/* Bits 14-15: Reserved, must be kept at reset value. */
|
||||
#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
|
||||
#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
|
||||
#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
|
||||
#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
|
||||
#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
|
||||
#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
|
||||
|
||||
/* Common control register */
|
||||
|
||||
# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */
|
||||
# define ADC_CCR_MULTI_MASK (0x1f << ADC_CCR_MULTI_SHIFT)
|
||||
# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */
|
||||
/* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */
|
||||
# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */
|
||||
/* 10001 to 11001: Triple mode (ADC1, 2 and 3) */
|
||||
# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */
|
||||
# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */
|
||||
# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */
|
||||
/* Bits 5-7: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
# define ADC_CCR_DELAY_MASK (0xf << ADC_CCR_DELAY_SHIFT)
|
||||
# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */
|
||||
/* Bit 12 Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */
|
||||
|
||||
# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */
|
||||
# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT)
|
||||
# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */
|
||||
# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */
|
||||
# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */
|
||||
# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */
|
||||
|
||||
# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */
|
||||
# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT)
|
||||
# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */
|
||||
# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */
|
||||
# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */
|
||||
# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */
|
||||
/* Bits 18-21: Reserved, must be kept at reset value. */
|
||||
# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */
|
||||
# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */
|
||||
/* Bits 24-31 Reserved, must be kept at reset value. */
|
||||
|
||||
/* Data register for dual and triple modes (32-bit data with no named fields) */
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H */
|
||||
+82
-67
@@ -1,8 +1,9 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -33,8 +34,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -42,60 +43,74 @@
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32F7_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32F7_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32F7_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32F7_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32F7_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32F7_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32F7_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32F7_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32F7_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32F7_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32F7_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NI2C > 0
|
||||
# define STM32F7_I2C1_CR1 (STM32F7_I2C1_BASE+STM32F7_I2C_CR1_OFFSET)
|
||||
# define STM32F7_I2C1_CR2 (STM32F7_I2C1_BASE+STM32F7_I2C_CR2_OFFSET)
|
||||
# define STM32F7_I2C1_OAR1 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR1_OFFSET)
|
||||
# define STM32F7_I2C1_OAR2 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR2_OFFSET)
|
||||
# define STM32F7_I2C1_TIMINGR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMINGR_OFFSET)
|
||||
# define STM32F7_I2C1_TIMEOUTR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32F7_I2C1_ISR (STM32F7_I2C1_BASE+STM32F7_I2C_ISR_OFFSET)
|
||||
# define STM32F7_I2C1_ICR (STM32F7_I2C1_BASE+STM32F7_I2C_ICR_OFFSET)
|
||||
# define STM32F7_I2C1_PECR (STM32F7_I2C1_BASE+STM32F7_I2C_PECR_OFFSET)
|
||||
# define STM32F7_I2C1_RXDR (STM32F7_I2C1_BASE+STM32F7_I2C_RXDR_OFFSET)
|
||||
# define STM32F7_I2C1_TXDR (STM32F7_I2C1_BASE+STM32F7_I2C_TXDR_OFFSET)
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NI2C > 1
|
||||
# define STM32F7_I2C2_CR1 (STM32F7_I2C2_BASE+STM32F7_I2C_CR1_OFFSET)
|
||||
# define STM32F7_I2C2_CR2 (STM32F7_I2C2_BASE+STM32F7_I2C_CR2_OFFSET)
|
||||
# define STM32F7_I2C2_OAR1 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR1_OFFSET)
|
||||
# define STM32F7_I2C2_OAR2 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR2_OFFSET)
|
||||
# define STM32F7_I2C2_TIMINGR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMINGR_OFFSET)
|
||||
# define STM32F7_I2C2_TIMEOUTR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32F7_I2C2_ISR (STM32F7_I2C2_BASE+STM32F7_I2C_ISR_OFFSET)
|
||||
# define STM32F7_I2C2_ICR (STM32F7_I2C2_BASE+STM32F7_I2C_ICR_OFFSET)
|
||||
# define STM32F7_I2C2_PECR (STM32F7_I2C2_BASE+STM32F7_I2C_PECR_OFFSET)
|
||||
# define STM32F7_I2C2_RXDR (STM32F7_I2C2_BASE+STM32F7_I2C_RXDR_OFFSET)
|
||||
# define STM32F7_I2C2_TXDR (STM32F7_I2C2_BASE+STM32F7_I2C_TXDR_OFFSET)
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NI2C > 2
|
||||
# define STM32F7_I2C3_CR1 (STM32F7_I2C3_BASE+STM32F7_I2C_CR1_OFFSET)
|
||||
# define STM32F7_I2C3_CR2 (STM32F7_I2C3_BASE+STM32F7_I2C_CR2_OFFSET)
|
||||
# define STM32F7_I2C3_OAR1 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR1_OFFSET)
|
||||
# define STM32F7_I2C3_OAR2 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR2_OFFSET)
|
||||
# define STM32F7_I2C3_TIMINGR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMINGR_OFFSET)
|
||||
# define STM32F7_I2C3_TIMEOUTR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32F7_I2C3_ISR (STM32F7_I2C3_BASE+STM32F7_I2C_ISR_OFFSET)
|
||||
# define STM32F7_I2C3_ICR (STM32F7_I2C3_BASE+STM32F7_I2C_ICR_OFFSET)
|
||||
# define STM32F7_I2C3_PECR (STM32F7_I2C3_BASE+STM32F7_I2C_PECR_OFFSET)
|
||||
# define STM32F7_I2C3_RXDR (STM32F7_I2C3_BASE+STM32F7_I2C_RXDR_OFFSET)
|
||||
# define STM32F7_I2C3_TXDR (STM32F7_I2C3_BASE+STM32F7_I2C_TXDR_OFFSET)
|
||||
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NI2C > 3
|
||||
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
@@ -111,7 +126,7 @@
|
||||
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
|
||||
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
|
||||
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
|
||||
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
|
||||
#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT)
|
||||
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
|
||||
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
|
||||
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
|
||||
@@ -119,7 +134,6 @@
|
||||
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
|
||||
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
|
||||
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
|
||||
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
|
||||
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
|
||||
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
|
||||
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
|
||||
@@ -180,15 +194,15 @@
|
||||
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
|
||||
|
||||
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
|
||||
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
|
||||
#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT)
|
||||
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
|
||||
|
||||
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
|
||||
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
|
||||
#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
|
||||
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
|
||||
|
||||
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
|
||||
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
|
||||
#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT)
|
||||
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
|
||||
|
||||
/* Timeout register */
|
||||
@@ -203,18 +217,6 @@
|
||||
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
|
||||
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
|
||||
|
||||
/* Interrupt and Status register and interrupt clear register */
|
||||
/* Common interrupt bits */
|
||||
|
||||
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
|
||||
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
|
||||
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
|
||||
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
|
||||
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
|
||||
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
|
||||
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
|
||||
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
|
||||
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
|
||||
|
||||
/* Fields unique to the Interrupt and Status register */
|
||||
|
||||
@@ -228,6 +230,19 @@
|
||||
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
|
||||
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
|
||||
|
||||
/* Interrupt and Status register and interrupt clear register */
|
||||
/* Common interrupt bits */
|
||||
|
||||
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
|
||||
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
|
||||
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
|
||||
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
|
||||
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
|
||||
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
|
||||
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
|
||||
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
|
||||
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
|
||||
|
||||
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
|
||||
|
||||
#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
|
||||
@@ -245,5 +260,5 @@
|
||||
|
||||
#define I2C_TXDR_MASK (0xff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_I2C_H */
|
||||
|
||||
@@ -0,0 +1,258 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
|
||||
*stm32f74xx77xx
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# define STM32_SPI_CLK_MAX 50000000UL
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# define STM32_SPI_CLK_MAX 54000000UL
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
|
||||
#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 3
|
||||
# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI4_DR (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI4_CRCPR (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 4
|
||||
# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI5_DR (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI5_CRCPR (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NSPI > 5
|
||||
# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI6_DR (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI6_CRCPR (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
|
||||
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
|
||||
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
|
||||
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
|
||||
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
|
||||
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
|
||||
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
|
||||
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
|
||||
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
|
||||
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
|
||||
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
|
||||
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
|
||||
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
|
||||
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
|
||||
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
|
||||
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
|
||||
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
|
||||
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
|
||||
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
|
||||
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
|
||||
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
|
||||
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
|
||||
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
|
||||
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
|
||||
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
|
||||
#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */
|
||||
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
|
||||
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
|
||||
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
|
||||
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
|
||||
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
|
||||
#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT)
|
||||
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4)
|
||||
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5)
|
||||
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6)
|
||||
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7)
|
||||
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8)
|
||||
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9)
|
||||
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
|
||||
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
|
||||
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
|
||||
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
|
||||
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
|
||||
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
|
||||
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
|
||||
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
|
||||
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
|
||||
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
|
||||
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
|
||||
#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */
|
||||
#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */
|
||||
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
|
||||
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
|
||||
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
|
||||
#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT)
|
||||
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
|
||||
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
|
||||
#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT)
|
||||
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
|
||||
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
|
||||
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
|
||||
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
|
||||
|
||||
/* I2S configuration register */
|
||||
|
||||
#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
|
||||
#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
|
||||
#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
|
||||
# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */
|
||||
# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */
|
||||
# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */
|
||||
#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */
|
||||
#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */
|
||||
#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
|
||||
# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
|
||||
# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
|
||||
# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
|
||||
#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */
|
||||
#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */
|
||||
#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
|
||||
# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */
|
||||
# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */
|
||||
# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */
|
||||
# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */
|
||||
#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */
|
||||
#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */
|
||||
#define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */
|
||||
|
||||
/* I2S prescaler register */
|
||||
|
||||
#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
|
||||
#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
|
||||
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H */
|
||||
@@ -34,8 +34,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
|
||||
#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -368,4 +368,4 @@
|
||||
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
|
||||
|
||||
@@ -82,6 +82,7 @@
|
||||
|
||||
|
||||
#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */
|
||||
#define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */
|
||||
#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */
|
||||
#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */
|
||||
|
||||
@@ -145,6 +146,10 @@
|
||||
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
|
||||
#define STM32_SDMMC2_BASE 0x40011c00 /* 0x40011c00-0x40011fff: SDMMC2 */
|
||||
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */
|
||||
# define STM32_ADC1_BASE 0x40012000 /* ADC1 */
|
||||
# define STM32_ADC2_BASE 0x40012100 /* ADC2 */
|
||||
# define STM32_ADC3_BASE 0x40012200 /* ADC3 */
|
||||
# define STM32_ADCCMN_BASE 0x40012300 /* Common */
|
||||
#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
|
||||
#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */
|
||||
@@ -210,5 +215,7 @@
|
||||
* address range
|
||||
*/
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H */
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */
|
||||
|
||||
@@ -638,7 +638,7 @@
|
||||
#define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */
|
||||
#define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT)
|
||||
# define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT)
|
||||
#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */
|
||||
#define RCC_DCKCFGR1_DFSDM1SEL (1 << 25) /* Bit 25: DFSDM1 clock prescaler selection */
|
||||
#define RCC_DCKCFGR1_ADFSDM1SEL (1 << 26) /* Bit 26: DFSDM1 AUDIO clock prescaler selection */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -6,6 +6,7 @@
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Diego Sanchez <dsanchez@nx-engineering.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -60,11 +61,14 @@
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/fs/ioctl.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_tim.h"
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32_adc.h"
|
||||
|
||||
@@ -77,9 +81,10 @@
|
||||
#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \
|
||||
defined(CONFIG_STM32F7_ADC3)
|
||||
|
||||
/* This implementation is for the STM32 F7 only */
|
||||
/* This implementation is for the STM32 F7[4-7] only */
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -1121,7 +1126,6 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Restart DMA for the next conversion series */
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0);
|
||||
@@ -1723,9 +1727,13 @@ struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist,
|
||||
|
||||
priv = (FAR struct stm32_dev_s *)dev->ad_priv;
|
||||
|
||||
DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES);
|
||||
|
||||
priv->cb = NULL;
|
||||
|
||||
DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES);
|
||||
if (cchannels > ADC_MAX_SAMPLES)
|
||||
{
|
||||
cchannels = ADC_MAX_SAMPLES;
|
||||
}
|
||||
priv->cchannels = cchannels;
|
||||
|
||||
memcpy(priv->chanlist, chanlist, cchannels);
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -103,10 +104,6 @@
|
||||
|
||||
/* Up to 3 ADC interfaces are supported */
|
||||
|
||||
#if STM32F7_NADC < 4
|
||||
# undef CONFIG_STM32F7_ADC4
|
||||
#endif
|
||||
|
||||
#if STM32F7_NADC < 3
|
||||
# undef CONFIG_STM32F7_ADC3
|
||||
#endif
|
||||
@@ -758,7 +755,7 @@ extern "C"
|
||||
****************************************************************************/
|
||||
|
||||
struct adc_dev_s;
|
||||
struct adc_dev_s *stm32_adc_initialiize(int intf,
|
||||
struct adc_dev_s *stm32_adc_initialize(int intf,
|
||||
FAR const uint8_t *chanlist,
|
||||
int nchannels);
|
||||
#undef EXTERN
|
||||
|
||||
+224
-138
File diff suppressed because it is too large
Load Diff
+583
-185
File diff suppressed because it is too large
Load Diff
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F7_STM32_UART_H
|
||||
#define __ARCH_ARM_STC_STM32F7_STM32_UART_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -342,4 +342,4 @@ void stm32_serial_dma_poll(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_STM32_UART_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_UART_H */
|
||||
|
||||
@@ -1,8 +1,9 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32f74xxx75xx_rcc.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -827,18 +828,38 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32F7_LTDC
|
||||
/* Configure PLLSAI */
|
||||
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
|
||||
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIP_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIQ_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIR_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR);
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
|
||||
putreg32(regval, STM32_RCC_DCKCFGR);
|
||||
regval = getreg32(STM32_RCC_DCKCFGR1);
|
||||
regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK
|
||||
| RCC_DCKCFGR1_PLLSAIDIVQ_MASK
|
||||
| RCC_DCKCFGR1_PLLSAIDIVR_MASK
|
||||
| RCC_DCKCFGR1_SAI1SEL_MASK
|
||||
| RCC_DCKCFGR1_SAI2SEL_MASK
|
||||
| RCC_DCKCFGR1_TIMPRESEL);
|
||||
|
||||
regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ
|
||||
| STM32_RCC_DCKCFGR1_PLLSAIDIVQ
|
||||
| STM32_RCC_DCKCFGR1_PLLSAIDIVR
|
||||
| STM32_RCC_DCKCFGR1_SAI1SRC
|
||||
| STM32_RCC_DCKCFGR1_SAI2SRC
|
||||
| STM32_RCC_DCKCFGR1_TIMPRESRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR1);
|
||||
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
@@ -852,6 +873,68 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
|
||||
|
||||
/* Configure PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLI2SCFGR);
|
||||
regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SP_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR);
|
||||
putreg32(regval, STM32_RCC_PLLI2SCFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR2);
|
||||
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
|
||||
| RCC_DCKCFGR2_USART2SEL_MASK
|
||||
| RCC_DCKCFGR2_UART4SEL_MASK
|
||||
| RCC_DCKCFGR2_UART5SEL_MASK
|
||||
| RCC_DCKCFGR2_USART6SEL_MASK
|
||||
| RCC_DCKCFGR2_UART7SEL_MASK
|
||||
| RCC_DCKCFGR2_UART8SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C1SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C2SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C3SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C4SEL_MASK
|
||||
| RCC_DCKCFGR2_LPTIM1SEL_MASK
|
||||
| RCC_DCKCFGR2_CECSEL_MASK
|
||||
| RCC_DCKCFGR2_CK48MSEL_MASK
|
||||
| RCC_DCKCFGR2_SDMMCSEL_MASK);
|
||||
|
||||
regval |= ( STM32_RCC_DCKCFGR2_USART1SRC
|
||||
| STM32_RCC_DCKCFGR2_USART2SRC
|
||||
| STM32_RCC_DCKCFGR2_UART4SRC
|
||||
| STM32_RCC_DCKCFGR2_UART5SRC
|
||||
| STM32_RCC_DCKCFGR2_USART6SRC
|
||||
| STM32_RCC_DCKCFGR2_UART7SRC
|
||||
| STM32_RCC_DCKCFGR2_UART8SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C1SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C2SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C3SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C4SRC
|
||||
| STM32_RCC_DCKCFGR2_LPTIM1SRC
|
||||
| STM32_RCC_DCKCFGR2_CECSRC
|
||||
| STM32_RCC_DCKCFGR2_CK48MSRC
|
||||
| STM32_RCC_DCKCFGR2_SDMMCSRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR2);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
@@ -224,6 +224,7 @@ static inline void rcc_enableahb1(void)
|
||||
/* USB OTG HS */
|
||||
|
||||
regval |= RCC_AHB1ENR_OTGHSEN;
|
||||
|
||||
#endif /* CONFIG_STM32F7_OTGHS */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
@@ -823,18 +824,41 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32F7_LTDC
|
||||
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI)
|
||||
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIP_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIQ_MASK
|
||||
| RCC_PLLSAICFGR_PLLSAIR_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR);
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
|
||||
putreg32(regval, STM32_RCC_DCKCFGR);
|
||||
regval = getreg32(STM32_RCC_DCKCFGR1);
|
||||
regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK
|
||||
| RCC_DCKCFGR1_PLLSAIDIVQ_MASK
|
||||
| RCC_DCKCFGR1_PLLSAIDIVR_MASK
|
||||
| RCC_DCKCFGR1_SAI1SEL_MASK
|
||||
| RCC_DCKCFGR1_SAI2SEL_MASK
|
||||
| RCC_DCKCFGR1_TIMPRESEL
|
||||
| RCC_DCKCFGR1_DFSDM1SEL
|
||||
| RCC_DCKCFGR1_ADFSDM1SEL);
|
||||
|
||||
regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ
|
||||
| STM32_RCC_DCKCFGR1_PLLSAIDIVQ
|
||||
| STM32_RCC_DCKCFGR1_PLLSAIDIVR
|
||||
| STM32_RCC_DCKCFGR1_SAI1SRC
|
||||
| STM32_RCC_DCKCFGR1_SAI2SRC
|
||||
| STM32_RCC_DCKCFGR1_TIMPRESRC
|
||||
| STM32_RCC_DCKCFGR1_DFSDM1SRC
|
||||
| STM32_RCC_DCKCFGR1_ADFSDM1SRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR1);
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
@@ -848,6 +872,72 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
|
||||
|
||||
/* Configure PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLI2SCFGR);
|
||||
regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SP_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SQ_MASK
|
||||
| RCC_PLLI2SCFGR_PLLI2SR_MASK);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIP
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR);
|
||||
putreg32(regval, STM32_RCC_PLLI2SCFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR2);
|
||||
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
|
||||
| RCC_DCKCFGR2_USART2SEL_MASK
|
||||
| RCC_DCKCFGR2_UART4SEL_MASK
|
||||
| RCC_DCKCFGR2_UART5SEL_MASK
|
||||
| RCC_DCKCFGR2_USART6SEL_MASK
|
||||
| RCC_DCKCFGR2_UART7SEL_MASK
|
||||
| RCC_DCKCFGR2_UART8SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C1SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C2SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C3SEL_MASK
|
||||
| RCC_DCKCFGR2_I2C4SEL_MASK
|
||||
| RCC_DCKCFGR2_LPTIM1SEL_MASK
|
||||
| RCC_DCKCFGR2_CECSEL_MASK
|
||||
| RCC_DCKCFGR2_CK48MSEL_MASK
|
||||
| RCC_DCKCFGR2_SDMMCSEL_MASK
|
||||
| RCC_DCKCFGR2_SDMMC2SEL_MASK
|
||||
| RCC_DCKCFGR2_DSISELL_MASK);
|
||||
|
||||
regval |= ( STM32_RCC_DCKCFGR2_USART1SRC
|
||||
| STM32_RCC_DCKCFGR2_USART2SRC
|
||||
| STM32_RCC_DCKCFGR2_UART4SRC
|
||||
| STM32_RCC_DCKCFGR2_UART5SRC
|
||||
| STM32_RCC_DCKCFGR2_USART6SRC
|
||||
| STM32_RCC_DCKCFGR2_UART7SRC
|
||||
| STM32_RCC_DCKCFGR2_UART8SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C1SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C2SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C3SRC
|
||||
| STM32_RCC_DCKCFGR2_I2C4SRC
|
||||
| STM32_RCC_DCKCFGR2_LPTIM1SRC
|
||||
| STM32_RCC_DCKCFGR2_CECSRC
|
||||
| STM32_RCC_DCKCFGR2_CK48MSRC
|
||||
| STM32_RCC_DCKCFGR2_SDMMCSRC
|
||||
| STM32_RCC_DCKCFGR2_SDMMC2SRC
|
||||
| STM32_RCC_DCKCFGR2_DSISRC);
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR2);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
+1
-1
@@ -1013,7 +1013,7 @@ config ARCH_BOARD_STM32F746_WS
|
||||
Waveshare STM32F746 development board featuring the STM32F746IG MCU.
|
||||
|
||||
config ARCH_BOARD_STM32L476VG_DISCO
|
||||
bool "STMicro STM32F746VG-Discovery board"
|
||||
bool "STMicro STM32L476VG -Discovery board"
|
||||
depends on ARCH_CHIP_STM32L476RG
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
|
||||
@@ -111,7 +111,7 @@
|
||||
*
|
||||
* PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz
|
||||
* SYSCLK = 432 MHz / 2 = 216 MHz
|
||||
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz
|
||||
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
|
||||
@@ -125,6 +125,7 @@
|
||||
|
||||
/* Configure factors for PLLSAI clock */
|
||||
|
||||
#define CONFIG_STM32F7_PLLSAI 1
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
|
||||
@@ -132,16 +133,20 @@
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register */
|
||||
|
||||
#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI
|
||||
#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI
|
||||
#define STM32_RCC_DCKCFGR_TIMPRE 0
|
||||
#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL
|
||||
#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
|
||||
|
||||
/* Configure factors for PLLI2S clock */
|
||||
|
||||
#define CONFIG_STM32F7_PLLI2S 1
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
@@ -149,11 +154,24 @@
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register 2 */
|
||||
|
||||
#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI
|
||||
#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ
|
||||
|
||||
|
||||
/* Several prescalers allow the configuration of the two AHB buses, the
|
||||
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
|
||||
@@ -311,20 +329,27 @@
|
||||
* USART8: has no remap
|
||||
*/
|
||||
|
||||
/* DMA channels *************************************************************/
|
||||
/* ADC */
|
||||
|
||||
#define ADC1_DMA_CHAN DMAMAP_ADC1_1
|
||||
#define ADC2_DMA_CHAN DMAMAP_ADC2_1
|
||||
#define ADC3_DMA_CHAN DMAMAP_ADC3_1
|
||||
|
||||
/* SPI
|
||||
*
|
||||
*
|
||||
* PA6 MISO CN12-13
|
||||
* PA7 MOSI CN12-15
|
||||
* PA5 SCK CN12-11
|
||||
* PA6 SPI1_MISO CN12-13
|
||||
* PA7 SPI1_MOSI CN12-15
|
||||
* PA5 SPI1_SCK CN12-11
|
||||
*
|
||||
* PB14 MISO CN12-28
|
||||
* PB15 MOSI CN12-26
|
||||
* PB10 SCK CN12-25
|
||||
* PB14 SPI2_MISO CN12-28
|
||||
* PB15 SPI2_MOSI CN12-26
|
||||
* PB13 SPI2_SCK CN12-30
|
||||
*
|
||||
* PB4 MISO CN12-27
|
||||
* PB5 MOSI CN12-29
|
||||
* PB3 SCK CN12-31
|
||||
* PB4 SPI3_MISO CN12-27
|
||||
* PB5 SPI3_MOSI CN12-29
|
||||
* PB3 SPI3_SCK CN12-31
|
||||
*/
|
||||
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
@@ -333,12 +358,35 @@
|
||||
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3
|
||||
|
||||
#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
|
||||
#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
|
||||
#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
|
||||
|
||||
/* I2C
|
||||
*
|
||||
*
|
||||
* PB8 I2C1_SCL CN12-3
|
||||
* PB9 I2C1_SDA CN12-5
|
||||
|
||||
* PB10 I2C2_SCL CN11-51
|
||||
* PB11 I2C2_SDA CN12-18
|
||||
*
|
||||
* PA8 I2C3_SCL CN12-23
|
||||
* PC9 I2C3_SDA CN12-1
|
||||
*
|
||||
*/
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
||||
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
|
||||
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
||||
|
||||
/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
|
||||
*
|
||||
* STM32 F7 BOARD LAN8742A
|
||||
|
||||
@@ -56,6 +56,9 @@ endif
|
||||
ifeq ($(CONFIG_SPI),y)
|
||||
CSRCS += stm32_spi.c
|
||||
endif
|
||||
ifeq ($(CONFIG_ADC),y)
|
||||
CSRCS += stm32_adc.c
|
||||
endif
|
||||
|
||||
ifeq ($(HAVE_SDIO),y)
|
||||
CSRCS += stm32_sdio.c
|
||||
|
||||
@@ -185,5 +185,19 @@ void stm32_dma_alloc_init(void);
|
||||
int stm32_dma_alloc_init(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_adc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called at application startup time to initialize the ADC functionality.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
int board_adc_initialize(void);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */
|
||||
|
||||
@@ -0,0 +1,188 @@
|
||||
/************************************************************************************
|
||||
* configs/nucleo-144/src/stm32_adc.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_adc.h"
|
||||
#include "nucleo-144.h"
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* Up to 3 ADC interfaces are supported */
|
||||
|
||||
#if STM32F7_NADC < 3
|
||||
# undef CONFIG_STM32F7_ADC3
|
||||
#endif
|
||||
|
||||
#if STM32F7_NADC < 2
|
||||
# undef CONFIG_STM32F7_ADC2
|
||||
#endif
|
||||
|
||||
#if STM32F7_NADC < 1
|
||||
# undef CONFIG_STM32F7_ADC1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3)
|
||||
#ifndef CONFIG_STM32F7_ADC1
|
||||
# warning "Channel information only available for ADC1"
|
||||
#endif
|
||||
|
||||
/* The number of ADC channels in the conversion list */
|
||||
|
||||
#define ADC1_NCHANNELS 1
|
||||
|
||||
/************************************************************************************
|
||||
* Private Data
|
||||
************************************************************************************/
|
||||
/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0
|
||||
* ADC123_IN10
|
||||
*/
|
||||
|
||||
/* Identifying number of each ADC channel: Variable Resistor.
|
||||
*
|
||||
* {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15};
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32F7_ADC1
|
||||
static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1};
|
||||
|
||||
/* Configurations of pins used byte each ADC channels
|
||||
*
|
||||
* {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5,
|
||||
* GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10,
|
||||
* GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15};
|
||||
*/
|
||||
|
||||
static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0};
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following interface to work with
|
||||
* examples/adc.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int board_adc_setup(void)
|
||||
{
|
||||
return board_adc_initialize();
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_adc_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called at application startup time to initialize the ADC functionality.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int board_adc_initialize(void)
|
||||
{
|
||||
#ifdef CONFIG_STM32F7_ADC1
|
||||
static bool initialized = false;
|
||||
struct adc_dev_s *adc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Check if we have already initialized */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < ADC1_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0" */
|
||||
|
||||
ret = adc_register("/dev/adc0", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Now we are initialized */
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
return OK;
|
||||
#else
|
||||
return -ENOSYS;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */
|
||||
#endif /* CONFIG_ADC */
|
||||
@@ -122,6 +122,55 @@
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
|
||||
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
|
||||
|
||||
/* Configure factors for PLLSAI clock */
|
||||
|
||||
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register */
|
||||
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
|
||||
|
||||
/* Configure factors for PLLI2S clock */
|
||||
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register 2 */
|
||||
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ
|
||||
|
||||
|
||||
/* Several prescalers allow the configuration of the two AHB buses, the
|
||||
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
|
||||
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
|
||||
@@ -165,14 +214,6 @@
|
||||
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* FLASH wait states
|
||||
*
|
||||
* --------- ---------- -----------
|
||||
|
||||
@@ -154,6 +154,53 @@
|
||||
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
|
||||
#endif
|
||||
|
||||
/* Configure factors for PLLSAI clock */
|
||||
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register */
|
||||
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
|
||||
|
||||
/* Configure factors for PLLI2S clock */
|
||||
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register 2 */
|
||||
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ
|
||||
|
||||
/* Several prescalers allow the configuration of the two AHB buses, the
|
||||
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
|
||||
* frequency of the two AHB buses is 216 MHz while the maximum frequency of
|
||||
|
||||
@@ -20,7 +20,7 @@ CONFIG_WINDOWS_CYGWIN=y
|
||||
#
|
||||
# Build Configuration
|
||||
#
|
||||
# CONFIG_APPS_DIR="../apps"
|
||||
CONFIG_APPS_DIR="../apps"
|
||||
CONFIG_BUILD_FLAT=y
|
||||
# CONFIG_BUILD_2PASS is not set
|
||||
|
||||
@@ -80,6 +80,7 @@ CONFIG_ARCH="arm"
|
||||
# CONFIG_ARCH_CHIP_DM320 is not set
|
||||
# CONFIG_ARCH_CHIP_EFM32 is not set
|
||||
# CONFIG_ARCH_CHIP_IMX1 is not set
|
||||
# CONFIG_ARCH_CHIP_IMX6 is not set
|
||||
# CONFIG_ARCH_CHIP_KINETIS is not set
|
||||
# CONFIG_ARCH_CHIP_KL is not set
|
||||
# CONFIG_ARCH_CHIP_LM is not set
|
||||
@@ -98,6 +99,7 @@ CONFIG_ARCH="arm"
|
||||
# CONFIG_ARCH_CHIP_SAMV7 is not set
|
||||
# CONFIG_ARCH_CHIP_STM32 is not set
|
||||
CONFIG_ARCH_CHIP_STM32F7=y
|
||||
# CONFIG_ARCH_CHIP_STM32L4 is not set
|
||||
# CONFIG_ARCH_CHIP_STR71X is not set
|
||||
# CONFIG_ARCH_CHIP_TMS570 is not set
|
||||
# CONFIG_ARCH_CHIP_MOXART is not set
|
||||
@@ -119,14 +121,16 @@ CONFIG_ARCH_CORTEXM7=y
|
||||
# CONFIG_ARCH_CORTEXR7F is not set
|
||||
CONFIG_ARCH_FAMILY="armv7-m"
|
||||
CONFIG_ARCH_CHIP="stm32f7"
|
||||
# CONFIG_ARM_TOOLCHAIN_IAR is not set
|
||||
CONFIG_ARM_TOOLCHAIN_GNU=y
|
||||
# CONFIG_ARMV7M_USEBASEPRI is not set
|
||||
CONFIG_ARCH_HAVE_CMNVECTOR=y
|
||||
CONFIG_ARMV7M_CMNVECTOR=y
|
||||
# CONFIG_ARMV7M_LAZYFPU is not set
|
||||
CONFIG_ARCH_HAVE_FPU=y
|
||||
CONFIG_ARCH_HAVE_DPFPU=y
|
||||
# CONFIG_ARCH_HAVE_DPFPU is not set
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
|
||||
CONFIG_ARM_HAVE_MPU_UNIFIED=y
|
||||
# CONFIG_ARM_MPU is not set
|
||||
|
||||
@@ -142,34 +146,134 @@ CONFIG_ARMV7M_HAVE_ITCM=y
|
||||
CONFIG_ARMV7M_HAVE_DTCM=y
|
||||
# CONFIG_ARMV7M_ITCM is not set
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
|
||||
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y
|
||||
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set
|
||||
# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
|
||||
CONFIG_ARMV7M_HAVE_STACKCHECK=y
|
||||
# CONFIG_ARMV7M_STACKCHECK is not set
|
||||
# CONFIG_ARMV7M_ITMSYSLOG is not set
|
||||
# CONFIG_SERIAL_TERMIOS is not set
|
||||
# CONFIG_USART6_RS485 is not set
|
||||
# CONFIG_SERIAL_DISABLE_REORDERING is not set
|
||||
|
||||
#
|
||||
# STM32 F7 Configuration Options
|
||||
#
|
||||
# CONFIG_ARCH_CHIP_STM32F745 is not set
|
||||
CONFIG_ARCH_CHIP_STM32F746=y
|
||||
# CONFIG_ARCH_CHIP_STM32F756 is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F745VG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F745VE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F745IG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F745IE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F745ZE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F745ZG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746BG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746VG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746VE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746BE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746ZG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746IE is not set
|
||||
CONFIG_ARCH_CHIP_STM32F746NG=y
|
||||
# CONFIG_ARCH_CHIP_STM32F746NE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746ZE is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F746IG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F756NG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F756BG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F756IG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F756VG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F756ZG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765NI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765VI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765VG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765BI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765NG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765ZG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765ZI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765IG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765BG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F765II is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767NG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767IG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767VG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767ZG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767NI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767VI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767BG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767ZI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F767II is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769BI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769II is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769BG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769NI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769AI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769NG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F769IG is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F777ZI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F777VI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F777NI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F777BI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F777II is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F778AI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F779II is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F779NI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F779BI is not set
|
||||
# CONFIG_ARCH_CHIP_STM32F779AI is not set
|
||||
CONFIG_STM32F7_STM32F74XX=y
|
||||
# CONFIG_STM32F7_STM32F75XX is not set
|
||||
# CONFIG_STM32F7_FLASH_512KB is not set
|
||||
CONFIG_STM32F7_FLASH_1024KB=y
|
||||
# CONFIG_STM32F7_STM32F76XX is not set
|
||||
# CONFIG_STM32F7_STM32F77XX is not set
|
||||
# CONFIG_STM32F7_IO_CONFIG_V is not set
|
||||
# CONFIG_STM32F7_IO_CONFIG_I is not set
|
||||
# CONFIG_STM32F7_IO_CONFIG_Z is not set
|
||||
CONFIG_STM32F7_IO_CONFIG_N=y
|
||||
# CONFIG_STM32F7_IO_CONFIG_B is not set
|
||||
# CONFIG_STM32F7_IO_CONFIG_A is not set
|
||||
# CONFIG_STM32F7_STM32F745XX is not set
|
||||
CONFIG_STM32F7_STM32F746XX=y
|
||||
# CONFIG_STM32F7_STM32F756XX is not set
|
||||
# CONFIG_STM32F7_STM32F765XX is not set
|
||||
# CONFIG_STM32F7_STM32F767XX is not set
|
||||
# CONFIG_STM32F7_STM32F768XX is not set
|
||||
# CONFIG_STM32F7_STM32F768AX is not set
|
||||
# CONFIG_STM32F7_STM32F769XX is not set
|
||||
# CONFIG_STM32F7_STM32F769AX is not set
|
||||
# CONFIG_STM32F7_STM32F777XX is not set
|
||||
# CONFIG_STM32F7_STM32F778XX is not set
|
||||
# CONFIG_STM32F7_STM32F778AX is not set
|
||||
# CONFIG_STM32F7_STM32F779XX is not set
|
||||
# CONFIG_STM32F7_STM32F779AX is not set
|
||||
# CONFIG_STM32F7_FLASH_CONFIG_E is not set
|
||||
# CONFIG_STM32F7_FLASH_CONFIG_I is not set
|
||||
CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y
|
||||
# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set
|
||||
# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set
|
||||
# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set
|
||||
|
||||
#
|
||||
# STM32 Peripheral Support
|
||||
#
|
||||
CONFIG_STM32F7_HAVE_LTDC=y
|
||||
CONFIG_STM32F7_HAVE_FSMC=y
|
||||
CONFIG_STM32F7_HAVE_ETHRNET=y
|
||||
CONFIG_STM32F7_HAVE_RNG=y
|
||||
CONFIG_STM32F7_HAVE_SPI5=y
|
||||
CONFIG_STM32F7_HAVE_SPI6=y
|
||||
# CONFIG_STM32F7_HAVE_SDMMC2 is not set
|
||||
# CONFIG_STM32F7_HAVE_ADC1_DMA is not set
|
||||
# CONFIG_STM32F7_HAVE_ADC2_DMA is not set
|
||||
# CONFIG_STM32F7_HAVE_ADC3_DMA is not set
|
||||
# CONFIG_STM32F7_HAVE_CAN3 is not set
|
||||
CONFIG_STM32F7_HAVE_DCMI=y
|
||||
# CONFIG_STM32F7_HAVE_DSIHOST is not set
|
||||
CONFIG_STM32F7_HAVE_DMA2D=y
|
||||
# CONFIG_STM32F7_HAVE_JPEG is not set
|
||||
# CONFIG_STM32F7_HAVE_CRYP is not set
|
||||
# CONFIG_STM32F7_HAVE_HASH is not set
|
||||
# CONFIG_STM32F7_HAVE_DFSDM1 is not set
|
||||
# CONFIG_STM32F7_ADC is not set
|
||||
# CONFIG_STM32F7_CAN is not set
|
||||
# CONFIG_STM32F7_DAC is not set
|
||||
@@ -177,34 +281,34 @@ CONFIG_STM32F7_HAVE_LTDC=y
|
||||
# CONFIG_STM32F7_I2C is not set
|
||||
# CONFIG_STM32F7_SAI is not set
|
||||
# CONFIG_STM32F7_SPI is not set
|
||||
# CONFIG_STM32F7_TIM is not set
|
||||
CONFIG_STM32F7_USART=y
|
||||
# CONFIG_STM32F7_ADC1 is not set
|
||||
# CONFIG_STM32F7_ADC2 is not set
|
||||
# CONFIG_STM32F7_ADC3 is not set
|
||||
# CONFIG_STM32F7_BKPSRAM is not set
|
||||
# CONFIG_STM32F7_CAN1 is not set
|
||||
# CONFIG_STM32F7_CAN2 is not set
|
||||
# CONFIG_STM32F7_CEC is not set
|
||||
# CONFIG_STM32F7_CRC is not set
|
||||
# CONFIG_STM32F7_CRYP is not set
|
||||
# CONFIG_STM32F7_DMA1 is not set
|
||||
# CONFIG_STM32F7_DMA2 is not set
|
||||
# CONFIG_STM32F7_DAC1 is not set
|
||||
# CONFIG_STM32F7_DAC2 is not set
|
||||
# CONFIG_STM32F7_DCMI is not set
|
||||
# CONFIG_STM32F7_DMA2D is not set
|
||||
# CONFIG_STM32F7_ETHMAC is not set
|
||||
# CONFIG_STM32F7_FSMC is not set
|
||||
# CONFIG_STM32F7_I2C1 is not set
|
||||
# CONFIG_STM32F7_I2C2 is not set
|
||||
# CONFIG_STM32F7_I2C3 is not set
|
||||
# CONFIG_STM32F7_I2C4 is not set
|
||||
# CONFIG_STM32F7_LPTIM1 is not set
|
||||
# CONFIG_STM32F7_LTDC is not set
|
||||
# CONFIG_STM32F7_DMA2D is not set
|
||||
# CONFIG_STM32F7_OTGFS is not set
|
||||
# CONFIG_STM32F7_OTGHS is not set
|
||||
# CONFIG_STM32F7_QUADSPI is not set
|
||||
# CONFIG_STM32F7_SAI1 is not set
|
||||
# CONFIG_STM32F7_RNG is not set
|
||||
# CONFIG_STM32F7_SAI1 is not set
|
||||
# CONFIG_STM32F7_SAI2 is not set
|
||||
# CONFIG_STM32F7_SDMMC1 is not set
|
||||
# CONFIG_STM32F7_SPDIFRX is not set
|
||||
@@ -228,7 +332,6 @@ CONFIG_STM32F7_USART=y
|
||||
# CONFIG_STM32F7_TIM12 is not set
|
||||
# CONFIG_STM32F7_TIM13 is not set
|
||||
# CONFIG_STM32F7_TIM14 is not set
|
||||
# CONFIG_STM32F7_TIM15 is not set
|
||||
# CONFIG_STM32F7_USART1 is not set
|
||||
# CONFIG_STM32F7_USART2 is not set
|
||||
# CONFIG_STM32F7_USART3 is not set
|
||||
@@ -239,8 +342,18 @@ CONFIG_STM32F7_USART6=y
|
||||
# CONFIG_STM32F7_UART8 is not set
|
||||
# CONFIG_STM32F7_IWDG is not set
|
||||
# CONFIG_STM32F7_WWDG is not set
|
||||
|
||||
#
|
||||
# U[S]ART Configuration
|
||||
#
|
||||
# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set
|
||||
# CONFIG_STM32F7_USART_BREAKS is not set
|
||||
# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
|
||||
|
||||
#
|
||||
# Timer Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# Architecture Options
|
||||
#
|
||||
@@ -452,6 +565,8 @@ CONFIG_SPI_EXCHANGE=y
|
||||
# CONFIG_SPI_BITBANG is not set
|
||||
# CONFIG_SPI_HWFEATURES is not set
|
||||
# CONFIG_SPI_CRCGENERATION is not set
|
||||
# CONFIG_SPI_CS_CONTROL is not set
|
||||
# CONFIG_SPI_CS_DELAY_CONTROL is not set
|
||||
# CONFIG_I2S is not set
|
||||
|
||||
#
|
||||
@@ -466,7 +581,12 @@ CONFIG_SPI_EXCHANGE=y
|
||||
# CONFIG_BCH is not set
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_IOEXPANDER is not set
|
||||
|
||||
#
|
||||
# LCD Driver Support
|
||||
#
|
||||
# CONFIG_LCD is not set
|
||||
# CONFIG_SLCD is not set
|
||||
|
||||
#
|
||||
# LED Support
|
||||
@@ -474,6 +594,7 @@ CONFIG_SPI_EXCHANGE=y
|
||||
# CONFIG_USERLED is not set
|
||||
# CONFIG_RGBLED is not set
|
||||
# CONFIG_PCA9635PW is not set
|
||||
# CONFIG_NCP5623C is not set
|
||||
# CONFIG_MMCSD is not set
|
||||
# CONFIG_MODEM is not set
|
||||
# CONFIG_MTD is not set
|
||||
@@ -508,10 +629,6 @@ CONFIG_USART6_SERIALDRIVER=y
|
||||
# CONFIG_USART7_SERIALDRIVER is not set
|
||||
# CONFIG_USART8_SERIALDRIVER is not set
|
||||
# CONFIG_OTHER_UART_SERIALDRIVER is not set
|
||||
|
||||
#
|
||||
# USART Configuration
|
||||
#
|
||||
CONFIG_MCU_SERIAL=y
|
||||
CONFIG_STANDARD_SERIAL=y
|
||||
# CONFIG_SERIAL_IFLOWCONTROL is not set
|
||||
@@ -655,11 +772,14 @@ CONFIG_ARCH_LOWPUTC=y
|
||||
CONFIG_LIB_SENDFILE_BUFSIZE=512
|
||||
# CONFIG_ARCH_ROMGETC is not set
|
||||
# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
|
||||
CONFIG_ARCH_HAVE_TLS=y
|
||||
# CONFIG_TLS is not set
|
||||
# CONFIG_LIBC_NETDB is not set
|
||||
|
||||
#
|
||||
# Non-standard Library Support
|
||||
#
|
||||
# CONFIG_LIB_CRC64_FAST is not set
|
||||
# CONFIG_LIB_KBDCODEC is not set
|
||||
# CONFIG_LIB_SLCDCODEC is not set
|
||||
|
||||
@@ -703,10 +823,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
|
||||
# CONFIG_EXAMPLES_FTPD is not set
|
||||
# CONFIG_EXAMPLES_HELLO is not set
|
||||
# CONFIG_EXAMPLES_HELLOXX is not set
|
||||
# CONFIG_EXAMPLES_JSON is not set
|
||||
# CONFIG_EXAMPLES_HIDKBD is not set
|
||||
# CONFIG_EXAMPLES_KEYPADTEST is not set
|
||||
# CONFIG_EXAMPLES_IGMP is not set
|
||||
# CONFIG_EXAMPLES_JSON is not set
|
||||
# CONFIG_EXAMPLES_KEYPADTEST is not set
|
||||
# CONFIG_EXAMPLES_MEDIA is not set
|
||||
# CONFIG_EXAMPLES_MM is not set
|
||||
# CONFIG_EXAMPLES_MODBUS is not set
|
||||
@@ -715,18 +835,18 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
|
||||
CONFIG_EXAMPLES_NSH=y
|
||||
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_EXAMPLES_NULL is not set
|
||||
# CONFIG_EXAMPLES_NX is not set
|
||||
# CONFIG_EXAMPLES_NXTERM is not set
|
||||
# CONFIG_EXAMPLES_NXFFS is not set
|
||||
# CONFIG_EXAMPLES_NXHELLO is not set
|
||||
# CONFIG_EXAMPLES_NXIMAGE is not set
|
||||
# CONFIG_EXAMPLES_NX is not set
|
||||
# CONFIG_EXAMPLES_NXLINES is not set
|
||||
# CONFIG_EXAMPLES_NXTERM is not set
|
||||
# CONFIG_EXAMPLES_NXTEXT is not set
|
||||
# CONFIG_EXAMPLES_OSTEST is not set
|
||||
# CONFIG_EXAMPLES_PCA9635 is not set
|
||||
# CONFIG_EXAMPLES_PIPE is not set
|
||||
# CONFIG_EXAMPLES_PPPD is not set
|
||||
# CONFIG_EXAMPLES_POSIXSPAWN is not set
|
||||
# CONFIG_EXAMPLES_PPPD is not set
|
||||
# CONFIG_EXAMPLES_RGBLED is not set
|
||||
# CONFIG_EXAMPLES_RGMP is not set
|
||||
# CONFIG_EXAMPLES_SENDMAIL is not set
|
||||
@@ -734,17 +854,16 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_EXAMPLES_SERIALRX is not set
|
||||
# CONFIG_EXAMPLES_SERLOOP is not set
|
||||
# CONFIG_EXAMPLES_SLCD is not set
|
||||
# CONFIG_EXAMPLES_SMART_TEST is not set
|
||||
# CONFIG_EXAMPLES_SMART is not set
|
||||
# CONFIG_EXAMPLES_SMART_TEST is not set
|
||||
# CONFIG_EXAMPLES_SMP is not set
|
||||
# CONFIG_EXAMPLES_TCPECHO is not set
|
||||
# CONFIG_EXAMPLES_TELNETD is not set
|
||||
# CONFIG_EXAMPLES_TIFF is not set
|
||||
# CONFIG_EXAMPLES_TOUCHSCREEN is not set
|
||||
# CONFIG_EXAMPLES_WEBSERVER is not set
|
||||
# CONFIG_EXAMPLES_USBSERIAL is not set
|
||||
# CONFIG_EXAMPLES_USBTERM is not set
|
||||
# CONFIG_EXAMPLES_WATCHDOG is not set
|
||||
# CONFIG_EXAMPLES_WEBSERVER is not set
|
||||
|
||||
#
|
||||
# File System Utilities
|
||||
@@ -766,8 +885,8 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# Interpreters
|
||||
#
|
||||
# CONFIG_INTERPRETERS_FICL is not set
|
||||
# CONFIG_INTERPRETERS_PCODE is not set
|
||||
# CONFIG_INTERPRETERS_MICROPYTHON is not set
|
||||
# CONFIG_INTERPRETERS_PCODE is not set
|
||||
|
||||
#
|
||||
# FreeModBus
|
||||
@@ -778,6 +897,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# Network Utilities
|
||||
#
|
||||
# CONFIG_NETUTILS_CODECS is not set
|
||||
# CONFIG_NETUTILS_ESP8266 is not set
|
||||
# CONFIG_NETUTILS_FTPC is not set
|
||||
# CONFIG_NETUTILS_JSON is not set
|
||||
# CONFIG_NETUTILS_SMTP is not set
|
||||
@@ -890,12 +1010,12 @@ CONFIG_NSH_CONSOLE=y
|
||||
#
|
||||
# System Libraries and NSH Add-Ons
|
||||
#
|
||||
# CONFIG_SYSTEM_FREE is not set
|
||||
# CONFIG_SYSTEM_CLE is not set
|
||||
# CONFIG_SYSTEM_CUTERM is not set
|
||||
# CONFIG_SYSTEM_INSTALL is not set
|
||||
# CONFIG_SYSTEM_FREE is not set
|
||||
# CONFIG_SYSTEM_HEX2BIN is not set
|
||||
# CONFIG_SYSTEM_HEXED is not set
|
||||
# CONFIG_SYSTEM_INSTALL is not set
|
||||
# CONFIG_SYSTEM_RAMTEST is not set
|
||||
CONFIG_READLINE_HAVE_EXTMATCH=y
|
||||
CONFIG_SYSTEM_READLINE=y
|
||||
@@ -903,6 +1023,6 @@ CONFIG_READLINE_ECHO=y
|
||||
# CONFIG_READLINE_TABCOMPLETION is not set
|
||||
# CONFIG_READLINE_CMD_HISTORY is not set
|
||||
# CONFIG_SYSTEM_SUDOKU is not set
|
||||
# CONFIG_SYSTEM_VI is not set
|
||||
# CONFIG_SYSTEM_UBLOXMODEM is not set
|
||||
# CONFIG_SYSTEM_VI is not set
|
||||
# CONFIG_SYSTEM_ZMODEM is not set
|
||||
|
||||
Reference in New Issue
Block a user