mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
Fixe to kernel build and syscalls.
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5738 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -110,12 +110,14 @@ static void dispatch_syscall(void)
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{
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__asm__ __volatile__
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(
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" push {r4}\n" /* Save R4 */
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" push {r4, r5}\n" /* Save R4 and R5 */
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" mov r5, lr\n" /* Save lr in R5 */
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" ldr r4, =g_stublookup\n" /* R4=The base of the stub lookup table */
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" lsl r0, r0, #2\n" /* R0=Offset of the stub for this syscall */
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" ldr r4, [r4, r0]\n" /* R4=Address of the stub for this syscall */
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" blx r5\n" /* Call the stub (modifies R14) */
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" pop {r4}\n" /* Restore R4 */
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" blx r5\n" /* Call the stub (modifies lr) */
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" mov lr, r5\n" /* Restore lr */
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" pop {r4, r5}\n" /* Restore R4 and R5*/
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" mov r2, r0\n" /* R2=Saves return value in R0 */
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" mov r0, #3\n" /* R0=SYS_syscall_return */
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" svc 0" /* Return from the syscall */
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@@ -321,7 +323,8 @@ int up_svcall(int irq, FAR void *context)
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current_regs[REG_R12], current_regs[REG_R13], current_regs[REG_R14], current_regs[REG_R15]);
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#ifdef CONFIG_NUTTX_KERNEL
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svcdbg("xPSR: %08x BASEPRI: %08x EXEC_RETURN: %08x\n",
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current_regs[REG_XPSR], current_regs[REG_BASEPRI], current_regs[REG_EXC_RETURN]);
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current_regs[REG_XPSR], current_regs[REG_BASEPRI],
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current_regs[REG_EXC_RETURN]);
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#else
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svcdbg("xPSR: %08x BASEPRI: %08x\n",
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current_regs[REG_XPSR], current_regs[REG_BASEPRI]);
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@@ -112,9 +112,13 @@ static void dispatch_syscall(void)
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{
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__asm__ __volatile__
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(
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" push {r4}\n" /* Save R4 */
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" mov r4, lr\n" /* Save lr in R4 */
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" ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
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" ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this syscall */
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" blx ip\n" /* Call the stub (modifies R14)*/
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" blx ip\n" /* Call the stub (modifies lr)*/
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" mov lr, r4\n" /* Restore lr */
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" pop {r4}\n" /* Restore r4 */
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" mov r2, r0\n" /* R2=Saved return value in R0 */
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" mov r0, #3\n" /* R0=SYS_syscall_return */
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" svc 0" /* Return from the syscall */
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@@ -152,7 +156,7 @@ int up_svcall(int irq, FAR void *context)
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regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
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regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
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#ifdef REG_EXC_RETURN
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svcdbg(" PSR: %08x LR: %08x\n", regs[REG_XPSR], current_regs[REG_EXC_RETURN]);
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svcdbg(" PSR: %08x LR: %08x\n", regs[REG_XPSR], regs[REG_EXC_RETURN]);
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#else
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svcdbg(" PSR: %08x\n", regs[REG_XPSR]);
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#endif
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@@ -265,7 +269,7 @@ int up_svcall(int irq, FAR void *context)
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rtcb->xcp.sysreturn = 0;
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/* The return value must be in R0-R1. dispatch_syscall() temporarily
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* moved the value for R0 to R2.
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* moved the value for R0 into R2.
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*/
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current_regs[REG_R0] = current_regs[REG_R2];
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@@ -322,7 +326,12 @@ int up_svcall(int irq, FAR void *context)
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svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
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current_regs[REG_R8], current_regs[REG_R9], current_regs[REG_R10], current_regs[REG_R11],
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current_regs[REG_R12], current_regs[REG_R13], current_regs[REG_R14], current_regs[REG_R15]);
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svcdbg(" PSR=%08x\n", current_regs[REG_XPSR]);
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#ifdef REG_EXC_RETURN
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svcdbg(" PSR: %08x LR: %08x\n",
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current_regs[REG_XPSR], current_regs[REG_EXC_RETURN]);
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#else
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svcdbg(" PSR: %08x\n", current_regs[REG_XPSR]);
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#endif
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}
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else
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{
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@@ -300,10 +300,18 @@ void up_addregion(void)
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*/
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#ifdef LPC17_AHB_HEAPBASE
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#if defined(CONFIG_NUTTX_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Yes... Add the AHB SRAM heap region. */
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/* Yes.. allow user-mode access to the AHB SRAM user heap memory */
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lpc17_mpu_uheap((uintptr_t)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
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#endif
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/* Add the AHB SRAM user heap region. */
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kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
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kmm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
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#endif
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}
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#endif
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@@ -1546,7 +1546,7 @@ static void lpc17_widebus(FAR struct sdio_dev_s *dev, bool wide)
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static void lpc17_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
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{
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uint32_t clock;
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uint32_t clkcr;
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switch (rate)
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{
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@@ -1554,39 +1554,39 @@ static void lpc17_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
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default:
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case CLOCK_SDIO_DISABLED:
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clock = LPC17_CLCKCR_INIT;
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clkcr = LPC17_CLCKCR_INIT;
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return;
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/* Enable in initial ID mode clocking (<400KHz) */
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case CLOCK_IDMODE:
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clock = (LPC17_CLCKCR_INIT | SDCARD_CLOCK_CLKEN);
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clkcr = (LPC17_CLCKCR_INIT | SDCARD_CLOCK_CLKEN);
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break;
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/* Enable in MMC normal operation clocking */
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case CLOCK_MMC_TRANSFER:
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clock = (SDCARD_CLOCK_MMCXFR | SDCARD_CLOCK_CLKEN);
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clkcr = (SDCARD_CLOCK_MMCXFR | SDCARD_CLOCK_CLKEN);
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break;
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/* SD normal operation clocking (wide 4-bit mode) */
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case CLOCK_SD_TRANSFER_4BIT:
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#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
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clock = (SDCARD_CLOCK_SDWIDEXFR | SDCARD_CLOCK_CLKEN);
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clkcr = (SDCARD_CLOCK_SDWIDEXFR | SDCARD_CLOCK_CLKEN);
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break;
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#endif
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/* SD normal operation clocking (narrow 1-bit mode) */
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case CLOCK_SD_TRANSFER_1BIT:
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clock = (SDCARD_CLOCK_SDXFR | SDCARD_CLOCK_CLKEN);
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clkcr = (SDCARD_CLOCK_SDXFR | SDCARD_CLOCK_CLKEN);
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break;
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}
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/* Set the new clock frequency along with the clock enable/disable bit */
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lpc17_setclock(clock);
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lpc17_setclock(clkcr);
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}
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/****************************************************************************
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@@ -124,4 +124,3 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SDCARD_H */
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@@ -198,22 +198,22 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
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#if CONFIG_MM_REGIONS > 1
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void up_addregion(void)
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{
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/* Add the region */
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kmm_addregion((FAR void*)SAM3U_INTSRAM1_BASE, CONFIG_SAM3U_SRAM1_SIZE);
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/* Allow user access to the heap memory */
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sam3u_mpu_uheap(SAM3U_INTSRAM1_BASE, CONFIG_SAM3U_SRAM1_SIZE);
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/* Add the region */
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#if CONFIG_MM_REGIONS > 2
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kmm_addregion((FAR void*)SAM3U_NFCSRAM_BASE, CONFIG_SAM3U_NFCSRAM_SIZE);
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kumm_addregion((FAR void*)SAM3U_INTSRAM1_BASE, CONFIG_SAM3U_SRAM1_SIZE);
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#if CONFIG_MM_REGIONS > 2
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/* Allow user access to the heap memory */
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sam3u_mpu_uheap(SAM3U_NFCSRAM_BASE, CONFIG_SAM3U_NFCSRAM_SIZE);
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/* Add the region */
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kumm_addregion((FAR void*)SAM3U_NFCSRAM_BASE, CONFIG_SAM3U_NFCSRAM_SIZE);
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#endif
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}
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#endif
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