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arch/stm32: Fix stm32-capture if timer don't support GTIM_CCER_CC1NP

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Fix: Some STM32 chips don't support GTIM_CCER_CC1NP; use HAVE_GTIM_CCXNP guards to exclude it. Adds/updates #ifdef HAVE_GTIM_CCXNP guards so GTIM_CCER_CC1NP is only included when supported, preventing register writes on chips without it.

Signed-off-by: Alexey Matveev <tippet@yandex.ru>
This commit is contained in:
Alexey Matveev
2026-01-17 22:44:28 +03:00
committed by Xiang Xiao
parent 3129c06390
commit 1b993875b5
1 changed files with 8 additions and 1 deletions
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arch/arm/src/stm32/stm32_capture.c
+8 -1
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@@ -1126,7 +1126,11 @@ static int stm32_cap_setchannel(struct stm32_cap_dev_s *dev,
case STM32_CAP_EDGE_BOTH:
ccer_en_bit = GTIM_CCER_CC1E;
#ifdef HAVE_GTIM_CCXNP
regval = GTIM_CCER_CC1P | GTIM_CCER_CC1NP;
#else
regval = GTIM_CCER_CC1P;
#endif
break;
default:
@@ -1134,8 +1138,11 @@ static int stm32_cap_setchannel(struct stm32_cap_dev_s *dev,
}
/* Shift all CCER bits to corresponding channel */
#ifdef HAVE_GTIM_CCXNP
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
#else
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P);
#endif
mask <<= GTIM_CCER_CCXBASE(channel);
regval <<= GTIM_CCER_CCXBASE(channel);
ccer_en_bit <<= GTIM_CCER_CCXBASE(channel);