mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 08:36:24 +08:00
SAMDL: Added SAMD DAC header file. Fixed SAMD EVSYS header. Added SAMD TC header file. Fixed some minor typos
This commit is contained in:
Matt Thompson
@@ -0,0 +1,136 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/samdl/chip/saml_dac.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References:
|
||||
* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
|
||||
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAMD21
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
/* DAC register offsets ********************************************************************/
|
||||
|
||||
#define SAM_DAC_CTRLA_OFFSET 0x0000 /* Control A Register */
|
||||
#define SAM_DAC_CTRLB_OFFSET 0x0001 /* Control B Register */
|
||||
#define SAM_DAC_EVCTRL_OFFSET 0x0002 /* Event Control Register */
|
||||
#define SAM_DAC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
|
||||
#define SAM_DAC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
|
||||
#define SAM_DAC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
|
||||
#define SAM_DAC_STATUS_OFFSET 0x0007 /* Status Register */
|
||||
#define SAM_DAC_DATA0_OFFSET 0x0008 /* Data DAC0 Register */
|
||||
#define SAM_DAC_DATA1_OFFSET 0x0009 /* Data DAC1 Register */
|
||||
#define SAM_DAC_DATABUF0_OFFSET 0x000C /* Data Buffer DAC0 Register */
|
||||
#define SAM_DAC_DATABUF1_OFFSET 0x000D /* Data Buffer DAC1 Register */
|
||||
|
||||
/* DAC register addresses ******************************************************************/
|
||||
|
||||
#define SAM_DAC_CTRLA (SAM_DAC_BASE+SAM_DAC_CTRLA_OFFSET)
|
||||
#define SAM_DAC_CTRLB (SAM_DAC_BASE+SAM_DAC_CTRLB_OFFSET)
|
||||
#define SAM_DAC_EVCTRL (SAM_DAC_BASE+SAM_DAC_EVCTRL_OFFSET)
|
||||
#define SAM_DAC_INTENCLR (SAM_DAC_BASE+SAM_DAC_INTENCLR_OFFSET)
|
||||
#define SAM_DAC_INTENSET (SAM_DAC_BASE+SAM_DAC_INTENSET_OFFSET)
|
||||
#define SAM_DAC_INTFLAG (SAM_DAC_BASE+SAM_DAC_INTFLAG_OFFSET)
|
||||
#define SAM_DAC_STATUS (SAM_DAC_BASE+SAM_DAC_STATUS_OFFSET)
|
||||
#define SAM_DAC_DATA0 (SAM_DAC_BASE+SAM_DAC_DATA0_OFFSET)
|
||||
#define SAM_DAC_DATA1 (SAM_DAC_BASE+SAM_DAC_DATA1_OFFSET)
|
||||
#define SAM_DAC_DATABUF0 (SAM_DAC_BASE+SAM_DAC_DATABUF0_OFFSET)
|
||||
#define SAM_DAC_DATABUF1 (SAM_DAC_BASE+SAM_DAC_DATABUF1_OFFSET)
|
||||
|
||||
/* DAC register bit definitions ************************************************************/
|
||||
|
||||
/* Control A Register */
|
||||
|
||||
#define DAC_CTRLA_SWRTS (1 << 0) /* Bit 0: Software reset */
|
||||
#define DAC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable DAC controller */
|
||||
#define DAC_CTRLA_RUNSTDBY (1 << 2) /* Bit 1: Run in standby */
|
||||
|
||||
/* Control B Register */
|
||||
|
||||
#define DAC_CTRLB_EOEN (1 << 0) /* Bit 0: External Output Enable (to Vout) */
|
||||
#define DAC_CTRLB_IOEN (1 << 1) /* Bit 1: Internal Output Enable (to analog comparator) */
|
||||
#define DAC_CTRLB_LEFTADJ (1 << 2) /* Bit 2: Left-Adjusted Data */
|
||||
#define DAC_CTRLB_VPD (1 << 3) /* Bit 3: Voltage Pump Disabled */
|
||||
#define DAC_CTRLB_BDWP (1 << 4) /* Bit 4: Bypass DATABUF Write protection */
|
||||
#define DAC_CTRLB_REFSEL_SHIFT (6) /* Bit 7:6: Reference selection */
|
||||
#define DAC_CTRLB_REFSEL_MASK (3 << DAC_CTRLB_REFSEL_SHIFT)
|
||||
# define DAC_CTRLB_REFSEL_INTREF (0 << DAC_CTRLB_REFSEL_SHIFT) /* Internal voltage reference */
|
||||
# define DAC_CTRLB_REFSEL_VDDANA (1 << DAC_CTRLB_REFSEL_SHIFT) /* Analog voltage supply */
|
||||
# define DAC_CTRLB_REFSEL_VREFA (2 << DAC_CTRLB_REFSEL_SHIFT) /* External voltage reference */
|
||||
|
||||
/* Event Control Register */
|
||||
|
||||
#define DAC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event input */
|
||||
#define DAC_EVCTRL_EMPTYEO (1 << 1) /* Bit 1: Data buffer empty event output */
|
||||
|
||||
/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set
|
||||
* Register, and Interrupt Flag Status and Clear Register
|
||||
*/
|
||||
|
||||
#define DAC_INT_UNDERRUN (1 << 0) /* Bit 0: Underrun interrupt */
|
||||
#define DAC_INT_EMPTY (1 << 1) /* Bit 1: Data buffer empty interrupt */
|
||||
#define DAC_INT_SYNCRDY (1 << 2) /* Bit 2: Sync ready */
|
||||
#define DAC_INT_ALL 0x07
|
||||
|
||||
/* Status Register */
|
||||
|
||||
#define DAC_STATUS_SYNCBUSY (1 << 7) /* Bit 0: Sync busy */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_DAC_H */
|
||||
@@ -68,9 +68,9 @@
|
||||
#define SAM_EVSYS_CTRL (SAM_EVSYS_BASE+SAM_EVSYS_CTRL_OFFSET)
|
||||
#define SAM_EVSYS_CHANNEL (SAM_EVSYS_BASE+SAM_EVSYS_CHANNEL_OFFSET)
|
||||
#define SAM_EVSYS_USER (SAM_EVSYS_BASE+SAM_EVSYS_USER_OFFSET)
|
||||
#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET
|
||||
#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET
|
||||
#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET
|
||||
#define SAM_EVSYS_CHSTATUS (SAM_EVSYS_BASE+SAM_EVSYS_CHSTATUS_OFFSET)
|
||||
#define SAM_EVSYS_INTENCLR (SAM_EVSYS_BASE+SAM_EVSYS_INTENCLR_OFFSET)
|
||||
#define SAM_EVSYS_INTENSET (SAM_EVSYS_BASE+SAM_EVSYS_INTENSET_OFFSET)
|
||||
#define SAM_EVSYS_INTFLAG (SAM_EVSYS_BASE+SAM_EVSYS_INTFLAG_OFFSET)
|
||||
|
||||
/* EVSYS register bit definitions ***********************************************************/
|
||||
@@ -302,12 +302,14 @@
|
||||
|
||||
/* Channel status register */
|
||||
|
||||
#define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
|
||||
#define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
|
||||
# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
|
||||
#define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
|
||||
#define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
|
||||
# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAMD20
|
||||
# define EVSYS_CHSTATUS_USRRDY_SHIFT (0) /* Bits 0-7: User Ready for Channel n, n=0-7 */
|
||||
# define EVSYS_CHSTATUS_USRRDY_MASK (0xff << EVSYS_CHSTATUS_USRRDY_SHIFT)
|
||||
# define EVSYS_CHSTATUS_USRRDY(n) (1 << (n))
|
||||
# define EVSYS_CHSTATUS_CHBUSY_SHIFT (8) /* Bits 8-15: Channel Busy n, n=0-7 */
|
||||
# define EVSYS_CHSTATUS_CHBUSY_MASK (0xff << EVSYS_CHSTATUS_CHBUSY_SHIFT)
|
||||
# define EVSYS_CHSTATUS_CHBUSY(n) (1 << ((n) + 8))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAMD21
|
||||
# define EVSYS_CHSTATUS_USRRDYH_SHIFT (16) /* Bits 16-19: User Ready for Channel n, n=8-11 */
|
||||
@@ -320,12 +322,14 @@
|
||||
|
||||
/* Interrupt enable clear, interrupt enable set, and interrupt flag status and clear registers */
|
||||
|
||||
#define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
|
||||
#define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
|
||||
# define EVSYS_INT_OVR(n) (1 << (n))
|
||||
#define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
|
||||
#define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
|
||||
# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAMD20
|
||||
# define EVSYS_INT_OVR_SHIFT (0) /* Bits 0-7: Overrun channel n interrupt, n=0-7 */
|
||||
# define EVSYS_INT_OVR_MASK (0xff << EVSYS_INT_OVR_SHIFT)
|
||||
# define EVSYS_INT_OVR(n) (1 << (n))
|
||||
# define EVSYS_INT_EVD_SHIFT (8) /* Bits 8-15: Event detected channel n interrupt, n=0-7 */
|
||||
# define EVSYS_INT_EVD_MASK (0xff << EVSYS_INT_EVD_SHIFT)
|
||||
# define EVSYS_INT_EVD(n) (1 << ((n) + 8))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAMD21
|
||||
# define EVSYS_INT_OVR_SHIFT (16) /* Bits 16-19: Overrun channel n interrupt, n=8-11 */
|
||||
|
||||
@@ -0,0 +1,249 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/samdl/chip/samd_tc.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Matt Thompson <matt@extent3d.com>
|
||||
*
|
||||
* References:
|
||||
* "Microchip SAMD21 datasheet"
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAMD21
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
/* TC register offsets *********************************************************************/
|
||||
|
||||
#define SAM_TC_CTRLA_OFFSET 0x0000 /* Control A register */
|
||||
#define SAM_TC_READREQ_OFFSET 0x0002 /* Read request register */
|
||||
#define SAM_TC_CTRLBCLR_OFFSET 0x0004 /* Control B clear register */
|
||||
#define SAM_TC_CTRLBSET_OFFSET 0x0005 /* Control B clear register */
|
||||
#define SAM_TC_CTRLC_OFFSET 0x0006 /* Control C register */
|
||||
#define SAM_TC_DBGCTRL_OFFSET 0x0008 /* Debug control register */
|
||||
#define SAM_TC_EVCTRL_OFFSET 0x000A /* Event control register */
|
||||
#define SAM_TC_INTENCLR_OFFSET 0x000C /* Interrupt enable clear register */
|
||||
#define SAM_TC_INTENSET_OFFSET 0x000D /* Interrupt enable set register */
|
||||
#define SAM_TC_INTFLAG_OFFSET 0x000E /* Interrupt flag register */
|
||||
#define SAM_TC_STATUS_OFFSET 0x000F /* Status register */
|
||||
#define SAM_TC_COUNT_OFFSET 0x0010 /* Count register */
|
||||
#define SAM_TC_CC0_OFFSET 0x0018 /* Capture Compare 0 register */
|
||||
#define SAM_TC_CC1_OFFSET 0x001C /* Capture Compare 1 register */
|
||||
|
||||
/* TC register addresses *******************************************************************/
|
||||
|
||||
#define SAM_TC3_CTRLA (SAM_TC3_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC3_READREQ (SAM_TC3_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC3_CTRLBCLR (SAM_TC3_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC3_CTRLBSET (SAM_TC3_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC3_CTRLC (SAM_TC3_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC3_DBGCTRL (SAM_TC3_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC3_EVCTRL (SAM_TC3_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC3_INTENCLR (SAM_TC3_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC3_INTENSET (SAM_TC3_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC3_INTFLAG (SAM_TC3_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC3_STATUS (SAM_TC3_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC3_COUNT (SAM_TC3_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC3_CC0 (SAM_TC3_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC3_CC1 (SAM_TC3_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC4_CTRLA (SAM_TC4_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC4_READREQ (SAM_TC4_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC4_CTRLBCLR (SAM_TC4_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC4_CTRLBSET (SAM_TC4_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC4_CTRLC (SAM_TC4_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC4_DBGCTRL (SAM_TC4_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC4_EVCTRL (SAM_TC4_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC4_INTENCLR (SAM_TC4_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC4_INTENSET (SAM_TC4_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC4_INTFLAG (SAM_TC4_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC4_STATUS (SAM_TC4_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC4_COUNT (SAM_TC4_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC4_CC0 (SAM_TC4_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC4_CC1 (SAM_TC4_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC5_CTRLA (SAM_TC5_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC5_READREQ (SAM_TC5_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC5_CTRLBCLR (SAM_TC5_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC5_CTRLBSET (SAM_TC5_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC5_CTRLC (SAM_TC5_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC5_DBGCTRL (SAM_TC5_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC5_EVCTRL (SAM_TC5_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC5_INTENCLR (SAM_TC5_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC5_INTENSET (SAM_TC5_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC5_INTFLAG (SAM_TC5_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC5_STATUS (SAM_TC5_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC5_COUNT (SAM_TC5_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC5_CC0 (SAM_TC5_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC5_CC1 (SAM_TC5_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC6_CTRLA (SAM_TC6_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC6_READREQ (SAM_TC6_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC6_CTRLBCLR (SAM_TC6_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC6_CTRLBSET (SAM_TC6_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC6_CTRLC (SAM_TC6_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC6_DBGCTRL (SAM_TC6_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC6_EVCTRL (SAM_TC6_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC6_INTENCLR (SAM_TC6_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC6_INTENSET (SAM_TC6_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC6_INTFLAG (SAM_TC6_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC6_STATUS (SAM_TC6_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC6_COUNT (SAM_TC6_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC6_CC0 (SAM_TC6_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC6_CC1 (SAM_TC6_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
#define SAM_TC7_CTRLA (SAM_TC7_BASE+SAM_TC_CTRLA_OFFSET)
|
||||
#define SAM_TC7_READREQ (SAM_TC7_BASE+SAM_TC_READREQ_OFFSET)
|
||||
#define SAM_TC7_CTRLBCLR (SAM_TC7_BASE+SAM_TC_CTRLBCLR_OFFSET)
|
||||
#define SAM_TC7_CTRLBSET (SAM_TC7_BASE+SAM_TC_CTRLBSET_OFFSET)
|
||||
#define SAM_TC7_CTRLC (SAM_TC7_BASE+SAM_TC_CTRLC_OFFSET)
|
||||
#define SAM_TC7_DBGCTRL (SAM_TC7_BASE+SAM_TC_DBGCTRL_OFFSET)
|
||||
#define SAM_TC7_EVCTRL (SAM_TC7_BASE+SAM_TC_EVCTRL_OFFSET)
|
||||
#define SAM_TC7_INTENCLR (SAM_TC7_BASE+SAM_TC_INTENCLR_OFFSET)
|
||||
#define SAM_TC7_INTENSET (SAM_TC7_BASE+SAM_TC_INTENSET_OFFSET)
|
||||
#define SAM_TC7_INTFLAG (SAM_TC7_BASE+SAM_TC_INTFLAG_OFFSET)
|
||||
#define SAM_TC7_STATUS (SAM_TC7_BASE+SAM_TC_STATUS_OFFSET)
|
||||
#define SAM_TC7_COUNT (SAM_TC7_BASE+SAM_TC_COUNT_OFFSET)
|
||||
#define SAM_TC7_CC0 (SAM_TC7_BASE+SAM_TC_CC0_OFFSET)
|
||||
#define SAM_TC7_CC1 (SAM_TC7_BASE+SAM_TC_CC1_OFFSET)
|
||||
|
||||
/* TC register bit definitions *************************************************************/
|
||||
|
||||
/* Control A register */
|
||||
|
||||
#define TC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
|
||||
#define TC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
|
||||
#define TC_CTRLA_MODE_SHIFT (2)
|
||||
#define TC_CTRLA_MODE_MASK (3 << TC_CTRLA_SHIFT)
|
||||
# define TC_CTRLA_MODE_COUNT16 (0 << TC_CTRLA_SHIFT)
|
||||
# define TC_CTRLA_MODE_COUNT8 (1 << TC_CTRLA_SHIFT)
|
||||
# define TC_CTRLA_MODE_COUNT32 (2 << TC_CTRLA_SHIFT)
|
||||
#define TC_CTRLA_WAVEGEN_SHIFT (5)
|
||||
#define TC_CTRLA_WAVEGEN_MASK (3 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_NFRQ (0 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_MFRQ (1 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_NPWM (2 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
# define TC_CTRLA_WAVEGEN_MPWM (3 << TC_CTRLA_WAVEGEN_SHIFT)
|
||||
#define TC_CTRLA_PRESCALER_SHIFT (8)
|
||||
#define TC_CTRLA_PRESCALER_MASK (7 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV1 (0 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV2 (1 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV4 (2 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV8 (3 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV16 (4 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV64 (5 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV256 (6 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
# define TC_CTRLA_PRESCALER_DIV1024 (7 << TC_CTRLA_PRESCALER_SHIFT)
|
||||
#define TC_CTRLA_RUNSTDBY (1 << 11)
|
||||
#define TC_CTRLA_PRESCSYNC_SHIFT (12)
|
||||
#define TC_CTRLA_PRESCSYNC_MASK (3 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
# define TC_CTRLA_PRESCSYNC_GCLK (0 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
# define TC_CTRLA_PRESCSYNC_PRESC (1 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
# define TC_CTRLA_PRESCSYNC_RESYNC (2 << TC_CTRLA_PRESCSYNC_SHIFT)
|
||||
|
||||
/* Read Request register */
|
||||
|
||||
#define TC_READREQ_ADDR_SHIFT (0)
|
||||
#define TC_READREQ_ADDR_MASK (0x1F << TC_READREQ_ADDR_SHIFT)
|
||||
#define TC_READREQ_RCONT (1 << 14)
|
||||
#define TC_READREQ_RREQ (1 << 15)
|
||||
|
||||
/* Control B Set/Clear register */
|
||||
|
||||
#define TC_CTRLB_DIR (1 << 0)
|
||||
#define TC_CTRLB_ONESHOT (1 << 2)
|
||||
#define TC_CTRLB_CMD_SHIFT (6)
|
||||
#define TC_CTRLB_CMD_MASK (3 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
# define TC_CTRLB_CMD_NONE (0 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
# define TC_CTRLB_CMD_RETRIGGER (1 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
# define TC_CTRLB_CMD_STOP (2 << TC_CTRLBCLR_CMD_SHIFT)
|
||||
|
||||
/* Control C register */
|
||||
|
||||
#define TC_CTRLC_INVEN0 (1 << 0)
|
||||
#define TC_CTRLC_INVEN1 (1 << 1)
|
||||
#define TC_CTRLC_CPTEN0 (1 << 4)
|
||||
#define TC_CTRLC_CPTEN1 (1 << 5)
|
||||
|
||||
/* Debug control register */
|
||||
|
||||
#define TC_DBGCTRL_DBGRUN (1 << 0)
|
||||
|
||||
/* Event control register */
|
||||
|
||||
#define TC_EVCTRL_EVACT_SHIFT (0)
|
||||
#define TC_EVCTRL_EVACT_MASK (7 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_OFF (0 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_RETRIGGER (1 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_COUNT (2 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_START (3 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_PPW (5 << TC_EVCTRL_EVACT_SHIFT)
|
||||
# define TC_EVCTRL_EVACT_PWP (6 << TC_EVCTRL_EVACT_SHIFT)
|
||||
|
||||
/* Interrupt register bits */
|
||||
|
||||
#define TC_INT_OVF (1 << 0)
|
||||
#define TC_INT_ERR (1 << 1)
|
||||
#define TC_INT_SYNCRDY (1 << 3)
|
||||
#define TC_INT_MC0 (1 << 4)
|
||||
#define TC_INT_MC1 (1 << 5)
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define TC_STATUS_STOP (1 << 3)
|
||||
#define TC_STATUS_SLAVE (1 << 4)
|
||||
#define TC_STATUS_SYNCBUSY (1 << 7)
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_TC_H */
|
||||
@@ -0,0 +1,77 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samdl/sam_dac.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Matt Thompson <matt@extent3d.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_SAM_DAC_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_SAM_DAC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "sam_config.h"
|
||||
#include "sam_port.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_dac.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_dac.h"
|
||||
#else
|
||||
# error Unrecognized SAMD/L architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_DAC_H */
|
||||
@@ -0,0 +1,76 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samdl/sam_evsys.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Matt Thompson <matt@extent3d.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H
|
||||
#define __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "sam_config.h"
|
||||
#include "sam_port.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_evsys.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_evsys.h"
|
||||
#else
|
||||
# error Unrecognized SAMD/L architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_EVSYS_H */
|
||||
@@ -75,7 +75,7 @@
|
||||
#define sam_apbc_enableperiph(s) modifyreg32(SAM_PM_APBCMASK,0,s)
|
||||
|
||||
#define sam_pac2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PAC2)
|
||||
#define sam_devsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_evsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_sercom_enableperiph(n) sam_apbc_enableperiph(PM_APBCMASK_SERCOM(n))
|
||||
#define sam_sercom0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM0)
|
||||
#define sam_sercom1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM1)
|
||||
@@ -135,7 +135,7 @@
|
||||
#define sam_apbc_disableperiph(s) modifyreg32(SAM_PM_APBCMASK,s,0)
|
||||
|
||||
#define sam_pac2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PAC2)
|
||||
#define sam_devsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_evsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
|
||||
#define sam_sercom_disableperiph(n) sam_apbc_disableperiph(PM_APBCMASK_SERCOM(n))
|
||||
#define sam_sercom0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM0)
|
||||
#define sam_sercom1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM1)
|
||||
@@ -195,7 +195,7 @@
|
||||
#define sam_apbc_isenabled(s) (getreg32(SAM_PM_APBCMASK) & (s)) != 0)
|
||||
|
||||
#define sam_pac2_isenabled() sam_apbc_isenabled(PM_APBCMASK_PAC2)
|
||||
#define sam_devsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
|
||||
#define sam_evsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
|
||||
#define sam_sercom_isenabled(n) sam_apbc_isenabled(PM_APBCMASK_SERCOM(n))
|
||||
#define sam_sercom0_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM0)
|
||||
#define sam_sercom1_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM1)
|
||||
|
||||
Reference in New Issue
Block a user