mirror of
https://github.com/apache/nuttx.git
synced 2026-09-22 14:24:40 +08:00
arch/nrf53: initial support for rptun
This commit is contained in:
raiden00pl
Xiang Xiao
@@ -68,6 +68,10 @@ config NRF53_ENABLE_APPROTECT
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# Peripheral Selection
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config NRF53_IPC
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bool
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default y if RPTUN
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config NRF53_UART
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bool
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default n
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@@ -42,6 +42,14 @@ ifeq ($(CONFIG_NRF53_APPCORE),y)
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CHIP_CSRCS += nrf53_cpunet.c
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endif
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ifeq ($(CONFIG_NRF53_IPC),y)
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CHIP_CSRCS += nrf53_ipc.c
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endif
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ifeq ($(CONFIG_RPTUN),y)
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CHIP_CSRCS += nrf53_rptun.c
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endif
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ifeq ($(CONFIG_NRF53_SOFTDEVICE_CONTROLLER),y)
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NRFXLIB_UNPACK := sdk-nrfxlib
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@@ -0,0 +1,68 @@
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/****************************************************************************
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* arch/arm/src/nrf53/hardware/nrf53_ipc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_IPC_H
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#define __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_IPC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "nrf53_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define NRF53_IPC_CHANS 16
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/* Register offsets *********************************************************/
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#define NRF53_IPC_TASKS_SEND_OFFSET(n) (0x000 + (0x4 * n)) /* Trigger events on IPC channel enabled in SEND_CNF[n] */
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#define NRF53_IPC_SUBSCRIBE_SEND_OFFSET(n) (0x080 + (0x4 * n)) /* Subscribe configuration for task SEND[n] */
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#define NRF53_IPC_EVENTS_RECEIVE_OFFSET(n) (0x100 + (0x4 * n)) /* Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */
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#define NRF53_IPC_PUBLISH_RECEIVE_OFFSET(n) (0x180 + (0x4 * n)) /* Publish configuration for event RECEIVE[n] */
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#define NRF53_IPC_INTEN_OFFSET (0x300) /* Enable or disable interrupt */
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#define NRF53_IPC_INTENSET_OFFSET (0x304) /* Enable interrupt */
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#define NRF53_IPC_INTENCLR_OFFSET (0x308) /* Disable interrupt */
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#define NRF53_IPC_INTPEND_OFFSET (0x30C) /* Pending interrupts */
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#define NRF53_IPC_SEND_CNF_OFFSET(n) (0x510 + (0x4 * n)) /* Send event configuration for TASKS_SEND[n] */
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#define NRF53_IPC_RECEIVE_CNF_OFFSET(n) (0x590 + (0x4 * n)) /* Receive event configuration for EVENTS_RECEIVE[n] */
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#define NRF53_IPC_GPMEM_OFFSET(n) (0x610 + (0x4 * n)) /* General purpose memory */
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/* Register definitions *****************************************************/
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#define NRF53_IPC_TASKS_SEND(n) (NRF53_IPC_BASE + NRF53_IPC_TASKS_SEND_OFFSET(n))
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#define NRF53_IPC_SUBSCRIBE_SEND(n) (NRF53_IPC_BASE + NRF53_IPC_SUBSCRIBE_SEND_OFFSET(n))
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#define NRF53_IPC_EVENTS_RECEIVE(n) (NRF53_IPC_BASE + NRF53_IPC_EVENTS_RECEIVE_OFFSET(n))
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#define NRF53_IPC_INTEN (NRF53_IPC_BASE + NRF53_IPC_INTEN_OFFSET)
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#define NRF53_IPC_INTENSET (NRF53_IPC_BASE + NRF53_IPC_INTENSET_OFFSET)
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#define NRF53_IPC_INTENCLR (NRF53_IPC_BASE + NRF53_IPC_INTENCLR_OFFSET)
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#define NRF53_IPC_INTPEND (NRF53_IPC_BASE + NRF53_IPC_INTPEND_OFFSET)
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#define NRF53_IPC_SEND_CNF(n) (NRF53_IPC_BASE + NRF53_IPC_SEND_CNF_OFFSET(n))
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#define NRF53_IPC_RECEIVE_CNF(n) (NRF53_IPC_BASE + NRF53_IPC_RECEIVE_CNF_OFFSET(n))
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#define NRF53_IPC_GPMEM(n) (NRF53_IPC_BASE + NRF53_IPC_GPMEM_OFFSET(n))
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/* Register bit definitions *************************************************/
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#define IPC_CHAN_ID(x) (1 << x) /* Channel ID */
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_IPC_H */
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@@ -34,29 +34,29 @@
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/* Register offsets *********************************************************/
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#define NRF53_SPU_EVENTS_RAMACCERR_OFFSET 0x100 /* A security violation has been detected for the RAM memory space */
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#define NRF53_SPU_EVENTS_FLASHACCERR_OFFSET 0x104 /* A security violation has been detected for the FLASH memory space */
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#define NRF53_SPU_EVENTS_PERIPHACCERR_OFFSET 0x108 /* A security violation has been detected on one or several peripherals */
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#define NRF53_SPU_PUBLISH_RAMACCERR_OFFSET 0x180 /* Publish configuration for event RAMACCERR */
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#define NRF53_SPU_PUBLISH_FLASHACCERR_OFFSET 0x184 /* Publish configuration for event FLASHACCERR */
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#define NRF53_SPU_PUBLISH_PERIPHACCERR_OFFSET 0x188 /* Publish configuration for event PERIPHACCERR */
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#define NRF53_SPU_INTEN_OFFSET 0x300 /* Enable or disable interrupt */
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#define NRF53_SPU_INTSEL_OFFSET 0x304 /* Enable interrupt */
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#define NRF53_SPU_INTCLR_OFFSET 0x308 /* Disable interrupt */
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#define NRF53_SPU_CAP_OFFSET 0x400 /* Show implemented features for the current device */
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#define NRF53_SPU_CPULOCK_OFFSET 0x404 /* Configure bits to lock down CPU features at runtime */
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#define NRF53_SPU_EXTDOMAIN_OFFSET 0x440 /* Access for bus access generated from the external domain n */
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#define NRF53_SPU_DPPIPERM_OFFSET 0x480 /* Select between secure and non-secure attribute for the DPPI channels. */
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#define NRF53_SPU_DPPILOCK_OFFSET 0x484 /* Prevent further modification of the corresponding PERM register */
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#define NRF53_SPU_GPIOPORTPERM_OFFSET 0x4C0 /* Select between secure and non-secure attribute for pins 0 to 31 of port n. */
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#define NRF53_SPU_GPIOPORTLOCK_OFFSET 0x4C4 /* Prevent further modification of the corresponding PERM register */
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#define NRF53_SPU_FLASHNSCREGION_OFFSET 0x500 /* Define which flash region can contain the non-secure callable (NSC) region n */
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#define NRF53_SPU_FLASHNSCSIZE_OFFSET 0x504 /* Define the size of the non-secure callable (NSC) region n */
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#define NRF53_SPU_RAMNSCREGION_OFFSET 0x540 /* Define which RAM region can contain the non-secure callable (NSC) region n */
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#define NRF53_SPU_RAMNSCSIZE_OFFSET 0x544 /* Define the size of the non-secure callable (NSC) region n */
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#define NRF53_SPU_FLASHREGIONPERM_OFFSET 0x600 /* Access permissions for flash region n */
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#define NRF53_SPU_RAMREGIONPERM_OFFSET 0x700 /* Access permissions for RAM region n */
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#define NRF53_SPU_PERIPHIDPERM_OFFSET 0x800 /* List capabilities and access permissions for the peripheral with ID n */
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#define NRF53_SPU_EVENTS_RAMACCERR_OFFSET 0x100 /* A security violation has been detected for the RAM memory space */
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#define NRF53_SPU_EVENTS_FLASHACCERR_OFFSET 0x104 /* A security violation has been detected for the FLASH memory space */
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#define NRF53_SPU_EVENTS_PERIPHACCERR_OFFSET 0x108 /* A security violation has been detected on one or several peripherals */
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#define NRF53_SPU_PUBLISH_RAMACCERR_OFFSET 0x180 /* Publish configuration for event RAMACCERR */
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#define NRF53_SPU_PUBLISH_FLASHACCERR_OFFSET 0x184 /* Publish configuration for event FLASHACCERR */
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#define NRF53_SPU_PUBLISH_PERIPHACCERR_OFFSET 0x188 /* Publish configuration for event PERIPHACCERR */
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#define NRF53_SPU_INTEN_OFFSET 0x300 /* Enable or disable interrupt */
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#define NRF53_SPU_INTSEL_OFFSET 0x304 /* Enable interrupt */
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#define NRF53_SPU_INTCLR_OFFSET 0x308 /* Disable interrupt */
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#define NRF53_SPU_CAP_OFFSET 0x400 /* Show implemented features for the current device */
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#define NRF53_SPU_CPULOCK_OFFSET 0x404 /* Configure bits to lock down CPU features at runtime */
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#define NRF53_SPU_EXTDOMAIN_OFFSET(n) (0x440 + (0x4 * n)) /* Access for bus access generated from the external domain n */
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#define NRF53_SPU_DPPIPERM_OFFSET(n) (0x480 + (0x4 * n)) /* Select between secure and non-secure attribute for the DPPI channels. */
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#define NRF53_SPU_DPPILOCK_OFFSET(n) (0x484 + (0x4 * n)) /* Prevent further modification of the corresponding PERM register */
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#define NRF53_SPU_GPIOPORTPERM_OFFSET(n) (0x4C0 + (0x4 * n)) /* Select between secure and non-secure attribute for pins 0 to 31 of port n. */
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#define NRF53_SPU_GPIOPORTLOCK_OFFSET(n) (0x4C4 + (0x4 * n)) /* Prevent further modification of the corresponding PERM register */
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#define NRF53_SPU_FLASHNSCREGION_OFFSET(n) (0x500 + (0x4 * n)) /* Define which flash region can contain the non-secure callable (NSC) region n */
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#define NRF53_SPU_FLASHNSCSIZE_OFFSET(n) (0x504 + (0x4 * n)) /* Define the size of the non-secure callable (NSC) region n */
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#define NRF53_SPU_RAMNSCREGION_OFFSET(n) (0x540 + (0x4 * n)) /* Define which RAM region can contain the non-secure callable (NSC) region n */
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#define NRF53_SPU_RAMNSCSIZE_OFFSET(n) (0x544 + (0x4 * n)) /* Define the size of the non-secure callable (NSC) region n */
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#define NRF53_SPU_FLASHREGIONPERM_OFFSET(n) (0x600 + (0x4 * n)) /* Access permissions for flash region n */
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#define NRF53_SPU_RAMREGIONPERM_OFFSET(n) (0x700 + (0x4 * n)) /* Access permissions for RAM region n */
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#define NRF53_SPU_PERIPHIDPERM_OFFSET(n) (0x800 + (0x4 * n)) /* List capabilities and access permissions for the peripheral with ID n */
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/* Register definitions *****************************************************/
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@@ -71,21 +71,35 @@
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#define NRF53_SPU_INTCLR (NRF53_SPU_BASE + NRF53_SPU_INTCLR_OFFSET)
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#define NRF53_SPU_CAP (NRF53_SPU_BASE + NRF53_SPU_CAP_OFFSET)
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#define NRF53_SPU_CPULOCK (NRF53_SPU_BASE + NRF53_SPU_CPULOCK_OFFSET)
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#define NRF53_SPU_EXTDOMAIN (NRF53_SPU_BASE + NRF53_SPU_EXTDOMAIN_OFFSET)
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#define NRF53_SPU_DPPIPERM (NRF53_SPU_BASE + NRF53_SPU_DPPIPERM_OFFSET)
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#define NRF53_SPU_DPPILOCK (NRF53_SPU_BASE + NRF53_SPU_DPPILOCK_OFFSET)
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#define NRF53_SPU_GPIOPORTPERM (NRF53_SPU_BASE + NRF53_SPU_GPIOPORTPERM_OFFSET)
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#define NRF53_SPU_GPIOPORTLOCK (NRF53_SPU_BASE + NRF53_SPU_GPIOPORTLOCK_OFFSET)
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#define NRF53_SPU_FLASHNSCREGION (NRF53_SPU_BASE + NRF53_SPU_FLASHNSCREGION_OFFSET)
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#define NRF53_SPU_FLASHNSCSIZE (NRF53_SPU_BASE + NRF53_SPU_FLASHNSCSIZE_OFFSET)
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#define NRF53_SPU_RAMNSCREGION (NRF53_SPU_BASE + NRF53_SPU_RAMNSCREGION_OFFSET)
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#define NRF53_SPU_RAMNSCSIZE (NRF53_SPU_BASE + NRF53_SPU_RAMNSCSIZE_OFFSET)
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#define NRF53_SPU_FLASHREGIONPERM (NRF53_SPU_BASE + NRF53_SPU_FLASHREGIONPERM_OFFSET)
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#define NRF53_SPU_RAMREGIONPERM (NRF53_SPU_BASE + NRF53_SPU_RAMREGIONPERM_OFFSET)
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#define NRF53_SPU_PERIPHIDPERM (NRF53_SPU_BASE + NRF53_SPU_PERIPHIDPERM_OFFSET)
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#define NRF53_SPU_EXTDOMAIN(n) (NRF53_SPU_BASE + NRF53_SPU_EXTDOMAIN_OFFSET(n))
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#define NRF53_SPU_DPPIPERM(n) (NRF53_SPU_BASE + NRF53_SPU_DPPIPERM_OFFSET(n))
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#define NRF53_SPU_DPPILOCK(n) (NRF53_SPU_BASE + NRF53_SPU_DPPILOCK_OFFSET(n))
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#define NRF53_SPU_GPIOPORTPERM(n) (NRF53_SPU_BASE + NRF53_SPU_GPIOPORTPERM_OFFSET(n))
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#define NRF53_SPU_GPIOPORTLOCK(n) (NRF53_SPU_BASE + NRF53_SPU_GPIOPORTLOCK_OFFSET(n))
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#define NRF53_SPU_FLASHNSCREGION(n) (NRF53_SPU_BASE + NRF53_SPU_FLASHNSCREGION_OFFSET(n))
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#define NRF53_SPU_FLASHNSCSIZE(n) (NRF53_SPU_BASE + NRF53_SPU_FLASHNSCSIZE_OFFSET(n))
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#define NRF53_SPU_RAMNSCREGION(n) (NRF53_SPU_BASE + NRF53_SPU_RAMNSCREGION_OFFSET(n))
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#define NRF53_SPU_RAMNSCSIZE(n) (NRF53_SPU_BASE + NRF53_SPU_RAMNSCSIZE_OFFSET(n))
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#define NRF53_SPU_FLASHREGIONPERM(n) (NRF53_SPU_BASE + NRF53_SPU_FLASHREGIONPERM_OFFSET(n))
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#define NRF53_SPU_RAMREGIONPERM(n) (NRF53_SPU_BASE + NRF53_SPU_RAMREGIONPERM_OFFSET(n))
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#define NRF53_SPU_PERIPHIDPERM(n) (NRF53_SPU_BASE + NRF53_SPU_PERIPHIDPERM_OFFSET(n))
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/* Register bit definitions *************************************************/
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/* TODO */
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#define SPU_RAM_REGIONS (64)
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#define SPU_EXTDOMAIN_SECUREMAPPING_SHIFT (0)
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#define SPU_EXTDOMAIN_SECUREMAPPING_MASK (3 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
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# define SPU_EXTDOMAIN_SECUREMAPPING_NONSEC (0 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
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# define SPU_EXTDOMAIN_SECUREMAPPING_SEC (1 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
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# define SPU_EXTDOMAIN_SECUREMAPPING_USER (2 << SPU_EXTDOMAIN_SECUREMAPPING_SHIFT)
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#define SPU_EXTDOMAIN_SECUREMAPPING_SECATTR (1 << 4)
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#define SPU_EXTDOMAIN_SECUREMAPPING_LOCK (1 << 8)
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#define SPU_RAMREGION_PERM_EXEC (1 << 0)
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#define SPU_RAMREGION_PERM_WRITE (1 << 1)
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#define SPU_RAMREGION_PERM_READ (1 << 2)
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#define SPU_RAMREGION_PERM_SECATTR (1 << 4)
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#define SPU_RAMREGION_PERM_LOCK (1 << 5)
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#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_SPU_H */
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@@ -0,0 +1,183 @@
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/****************************************************************************
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* arch/arm/src/nrf53/nrf53_ipc.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
|
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*
|
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
|
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <nuttx/arch.h>
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#include "arm_internal.h"
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#include "nrf53_ipc.h"
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#include "hardware/nrf53_ipc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* IPC receive channel configuration */
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struct nrf53_ipc_recv_s
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{
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ipc_callback_t callback;
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void *args;
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};
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/* IPC device */
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struct nrf53_ipc_s
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{
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struct nrf53_ipc_recv_s recv[NRF53_IPC_CHANS];
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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struct nrf53_ipc_s g_nrf53_ipc;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nrf53_ipc_interrupt
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****************************************************************************/
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static int nrf53_ipc_interrupt(int irq, void *context, void *args)
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{
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struct nrf53_ipc_s *dev = args;
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uint32_t regval = 0;
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int i = 0;
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regval = getreg32(NRF53_IPC_INTPEND);
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_info("IPC interrupt 0x%" PRIx32 "\n", regval);
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for (i = 0; i < NRF53_IPC_CHANS; i += 1)
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{
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if (regval & IPC_CHAN_ID(i))
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{
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if (dev->recv[i].callback)
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{
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dev->recv[i].callback(i, dev->recv[i].args);
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}
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/* Clear EVENT */
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putreg32(0, NRF53_IPC_EVENTS_RECEIVE(i));
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}
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}
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: nrf53_ipc_subscribe
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****************************************************************************/
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void nrf53_ipc_subscribe(int id, ipc_callback_t callback, void *args)
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{
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struct nrf53_ipc_s *dev = &g_nrf53_ipc;
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DEBUGASSERT(id < NRF53_IPC_CHANS);
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_info("IPC subscribe %d\n", id);
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/* Register callaback */
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dev->recv[id].callback = callback;
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dev->recv[id].args = args;
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if (callback)
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{
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/* Register as receive channel and enable interrupts */
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|
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putreg32(IPC_CHAN_ID(id), NRF53_IPC_RECEIVE_CNF(id));
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putreg32(IPC_CHAN_ID(id), NRF53_IPC_INTENSET);
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}
|
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else
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{
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||||
/* Disable interrupts */
|
||||
|
||||
putreg32(IPC_CHAN_ID(id), NRF53_IPC_INTENCLR);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf53_ipc_signal
|
||||
****************************************************************************/
|
||||
|
||||
void nrf53_ipc_signal(int id)
|
||||
{
|
||||
DEBUGASSERT(id < NRF53_IPC_CHANS);
|
||||
|
||||
_info("IPC signal %d\n", id);
|
||||
|
||||
putreg32(1, NRF53_IPC_TASKS_SEND(id));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf53_ipc_send_cfg
|
||||
****************************************************************************/
|
||||
|
||||
void nrf53_ipc_send_cfg(int id)
|
||||
{
|
||||
DEBUGASSERT(id < NRF53_IPC_CHANS);
|
||||
|
||||
_info("IPC send cfg %d\n", id);
|
||||
|
||||
/* Enable send event on a single IPC channel */
|
||||
|
||||
putreg32(IPC_CHAN_ID(id), NRF53_IPC_SEND_CNF(id));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf53_ipc_init
|
||||
****************************************************************************/
|
||||
|
||||
void nrf53_ipc_init(void)
|
||||
{
|
||||
struct nrf53_ipc_s *dev = &g_nrf53_ipc;
|
||||
|
||||
/* Reset device */
|
||||
|
||||
memset(dev, 0, sizeof(struct nrf53_ipc_s));
|
||||
|
||||
/* Attach and enable the IRQ */
|
||||
|
||||
irq_attach(NRF53_IRQ_IPC, nrf53_ipc_interrupt, dev);
|
||||
|
||||
up_enable_irq(NRF53_IRQ_IPC);
|
||||
}
|
||||
@@ -0,0 +1,47 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/nrf53/nrf53_ipc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF53_NRF53_IPC_H
|
||||
#define __ARCH_ARM_SRC_NRF53_NRF53_IPC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "hardware/nrf53_ipc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef void (*ipc_callback_t)(int id, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
void nrf53_ipc_subscribe(int id, ipc_callback_t callback, void *args);
|
||||
void nrf53_ipc_send_cfg(int id);
|
||||
void nrf53_ipc_signal(int id);
|
||||
void nrf53_ipc_init(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF53_NRF53_IPC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,61 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/nrf53/nrf53_rptun.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF53_NRF53_RPTUN_H
|
||||
#define __ARCH_ARM_SRC_NRF53_NRF53_RPTUN_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf53_rptun_init
|
||||
****************************************************************************/
|
||||
|
||||
int nrf53_rptun_init(const char *shmemname, const char *cpuname);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_NRF53_NRF53_RPTUN_H */
|
||||
Reference in New Issue
Block a user