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https://github.com/apache/nuttx.git
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xtensa/esp32: Fix issue of system blocking when SPIRAM is used as stack
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
This commit is contained in:
chenwen@espressif.com
committed by
Xiang Xiao
Xiang Xiao
parent
c14888e759
commit
1665114fd1
@@ -31,6 +31,7 @@
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#include "esp32_spiram.h"
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#include "esp32_himem.h"
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#include "esp32_spiflash.h"
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#include "hardware/esp32_soc.h"
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/****************************************************************************
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@@ -79,8 +80,6 @@
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# define SPIRAM_BANKSWITCH_RESERVE 0
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#endif
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#define CACHE_BLOCKSIZE (32*1024)
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/* Start of the virtual address range reserved for himem use */
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#define VIRT_HIMEM_RANGE_START (SOC_EXTRAM_DATA_LOW + \
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@@ -164,20 +163,6 @@ static inline int rangeblock_idx_valid(int rangeblock_idx)
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return (rangeblock_idx >= 0 && rangeblock_idx < g_rangeblockcnt);
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}
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static void set_bank(int virt_bank, int phys_bank, int ct)
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{
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int r;
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r = cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE *
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virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct);
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DEBUGASSERT(r == 0);
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r = cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE *
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virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct);
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DEBUGASSERT(r == 0);
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UNUSED(r);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -567,9 +552,9 @@ int esp_himem_map(esp_himem_handle_t handle,
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for (i = 0; i < blockcount; i++)
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{
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set_bank(VIRT_HIMEM_RANGE_BLOCKSTART + range->block_start + i +
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range_block, handle->block[i + ram_block] +
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PHYS_HIMEM_BLOCKSTART, 1);
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esp32_set_bank(VIRT_HIMEM_RANGE_BLOCKSTART + range->block_start + i +
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range_block, handle->block[i + ram_block] +
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PHYS_HIMEM_BLOCKSTART, 1);
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}
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/* Set out pointer */
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@@ -113,6 +113,7 @@ enum spiflash_op_code_e
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SPIFLASH_OP_CODE_WRITE = 0,
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SPIFLASH_OP_CODE_READ,
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SPIFLASH_OP_CODE_ERASE,
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SPIFLASH_OP_CODE_SET_BANK,
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SPIFLASH_OP_CODE_ENCRYPT_READ,
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SPIFLASH_OP_CODE_ENCRYPT_WRITE
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};
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@@ -188,6 +189,7 @@ struct spiflash_work_arg
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uint32_t addr;
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uint8_t *buffer;
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uint32_t size;
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uint32_t paddr;
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} op_arg;
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volatile int ret;
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@@ -290,6 +292,9 @@ static int esp32_ioctl(struct mtd_dev_s *dev, int cmd,
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unsigned long arg);
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static int esp32_ioctl_encrypt(struct mtd_dev_s *dev, int cmd,
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unsigned long arg);
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#ifdef CONFIG_ESP32_SPIRAM
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static int esp32_set_mmu_map(int vaddr, int paddr, int num);
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#endif
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/****************************************************************************
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* Private Data
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@@ -1640,6 +1645,14 @@ static void esp32_spiflash_work(void *p)
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work_arg->op_arg.addr,
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work_arg->op_arg.size);
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}
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#ifdef CONFIG_ESP32_SPIRAM
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else if (work_arg->op_code == SPIFLASH_OP_CODE_SET_BANK)
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{
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work_arg->ret = esp32_set_mmu_map(work_arg->op_arg.addr,
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work_arg->op_arg.paddr,
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work_arg->op_arg.size);
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}
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#endif
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else if (work_arg->op_code == SPIFLASH_OP_CODE_ENCRYPT_READ)
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{
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esp32_set_read_opt(work_arg->op_arg.priv);
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@@ -1682,7 +1695,8 @@ static int esp32_async_op(enum spiflash_op_code_e opcode,
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struct esp32_spiflash_s *priv,
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uint32_t addr,
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const uint8_t *buffer,
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uint32_t size)
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uint32_t size,
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uint32_t paddr)
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{
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int ret;
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struct spiflash_work_arg work_arg =
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@@ -1694,6 +1708,7 @@ static int esp32_async_op(enum spiflash_op_code_e opcode,
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.addr = addr,
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.buffer = (uint8_t *)buffer,
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.size = size,
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.paddr = paddr,
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},
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.sem = NXSEM_INITIALIZER(0, 0)
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};
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@@ -1751,7 +1766,8 @@ static int esp32_erase(struct mtd_dev_s *dev, off_t startblock,
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#ifdef CONFIG_ESP32_SPI_FLASH_SUPPORT_PSRAM_STACK
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if (stack_is_psram())
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{
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ret = esp32_async_op(SPIFLASH_OP_CODE_ERASE, priv, addr, NULL, size);
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ret = esp32_async_op(SPIFLASH_OP_CODE_ERASE, priv, addr, NULL,
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size, 0);
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}
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else
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{
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@@ -1813,7 +1829,7 @@ static ssize_t esp32_read(struct mtd_dev_s *dev, off_t offset,
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if (stack_is_psram())
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{
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ret = esp32_async_op(SPIFLASH_OP_CODE_READ, priv,
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offset, buffer, nbytes);
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offset, buffer, nbytes, 0);
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}
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else
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{
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@@ -1925,7 +1941,7 @@ static ssize_t esp32_read_decrypt(struct mtd_dev_s *dev,
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if (stack_is_psram())
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{
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ret = esp32_async_op(SPIFLASH_OP_CODE_ENCRYPT_READ, priv,
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offset, buffer, nbytes);
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offset, buffer, nbytes, 0);
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}
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else
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{
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@@ -2040,7 +2056,7 @@ static ssize_t esp32_write(struct mtd_dev_s *dev, off_t offset,
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if (stack_is_psram())
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{
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ret = esp32_async_op(SPIFLASH_OP_CODE_WRITE, priv,
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offset, buffer, nbytes);
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offset, buffer, nbytes, 0);
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}
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else
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{
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@@ -2157,7 +2173,7 @@ static ssize_t esp32_bwrite_encrypt(struct mtd_dev_s *dev,
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if (stack_is_psram())
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{
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ret = esp32_async_op(SPIFLASH_OP_CODE_ENCRYPT_WRITE, priv,
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offset, buffer, nbytes);
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offset, buffer, nbytes, 0);
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}
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else
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{
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@@ -2463,10 +2479,78 @@ int spiflash_init_spi_flash_op_block_task(int cpu)
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_ESP32_SPIRAM
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/****************************************************************************
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* Name: esp32_set_mmu_map
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*
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* Description:
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* Set Ext-SRAM-Cache mmu mapping.
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*
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* Input Parameters:
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* vaddr - Virtual address in CPU address space
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* paddr - Physical address in Ext-SRAM
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* num - Pages to be set
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*
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* Returned Value:
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* 0 if success or a negative value if fail.
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*
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****************************************************************************/
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static int esp32_set_mmu_map(int vaddr, int paddr, int num)
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{
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int ret;
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ret = cache_sram_mmu_set(0, 0, vaddr, paddr, 32, num);
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DEBUGASSERT(ret == 0);
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ret = cache_sram_mmu_set(1, 0, vaddr, paddr, 32, num);
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return ret;
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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#ifdef CONFIG_ESP32_SPIRAM
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/****************************************************************************
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* Name: esp32_set_bank
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*
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* Description:
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* Set Ext-SRAM-Cache mmu mapping.
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*
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* Input Parameters:
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* virt_bank - Beginning of the virtual bank
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* phys_bank - Beginning of the physical bank
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* ct - Number of banks
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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void esp32_set_bank(int virt_bank, int phys_bank, int ct)
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{
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int ret;
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uint32_t vaddr = SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank;
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uint32_t paddr = phys_bank * CACHE_BLOCKSIZE;
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#ifdef CONFIG_ESP32_SPI_FLASH_SUPPORT_PSRAM_STACK
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if (stack_is_psram())
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{
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ret = esp32_async_op(SPIFLASH_OP_CODE_SET_BANK, NULL, vaddr, NULL,
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ct, paddr);
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}
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else
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#endif
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{
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ret = esp32_set_mmu_map(vaddr, paddr, ct);
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}
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DEBUGASSERT(ret == 0);
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UNUSED(ret);
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}
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#endif
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/****************************************************************************
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* Name: esp32_spiflash_init
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*
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@@ -44,10 +44,38 @@ extern "C"
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CACHE_BLOCKSIZE (32*1024)
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef CONFIG_ESP32_SPIRAM
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/****************************************************************************
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* Name: esp32_set_bank
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*
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* Description:
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* Set Ext-SRAM-Cache mmu mapping.
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*
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* Input Parameters:
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* virt_bank - Beginning of the virtual bank
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* phys_bank - Beginning of the physical bank
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* ct - Number of banks
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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void esp32_set_bank(int virt_bank, int phys_bank, int ct);
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#endif
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/****************************************************************************
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* Name: esp32_spiflash_init
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*
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