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SAMA5 NAND: Finish upper part of PMECC logic; add HSMC interrupt handling

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This commit is contained in:
Gregory Nutt
2013-11-24 11:51:30 -06:00
parent d1b4f1c466
commit 15f6e382cb
6 changed files with 527 additions and 136 deletions
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arch/arm/src/lpc31xx/lpc31_ehci.c
+2 -2
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@@ -3055,7 +3055,7 @@ static void lpc31_ehci_bottomhalf(FAR void *arg)
lpc31_givesem(&g_ehci.exclsem);
/* Re-enable relevant EHCI interrupts. Interrupts should still be enabled
* at the level of the AIC.
* at the level of the interrupt controller.
*/
lpc31_putreg(EHCI_HANDLED_INTS, &HCOR->usbintr);
@@ -4497,7 +4497,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
}
/* Enable EHCI interrupts. Interrupts are still disabled at the level of
* the AIC.
* the interrupt controller.
*/
lpc31_putreg(EHCI_HANDLED_INTS, &HCOR->usbintr);
arch/arm/src/sama5/chip/sam_hsmc.h
+3 -1
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@@ -352,7 +352,9 @@
#define HSMC_NFCINT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */
#define HSMC_NFCINT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */
#define HSMC_NFCINT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */
#define HSMC_NFCINT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
#define HSMC_NFCINT_RBEDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
#define HSMC_NFCINT_ALL (0x01f300030)
/* HSMC NFC Address Cycle Zero Register */
arch/arm/src/sama5/sam_nand.c
+399 -125
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File diff suppressed because it is too large Load Diff
arch/arm/src/sama5/sam_nand.h
+50 -7
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@@ -184,6 +184,46 @@
# endif
#endif /* CONFIG_SAMA5_EBICS3_NAND */
/* Count the number of banks that configured for NAND with PMECC support
* enabled.
*/
#undef HAVE_NAND
#ifdef CONFIG_SAMA5_EBICS0_NAND
# define HAVE_NAND 1
# define NAND_HAVE_EBICS0 1
#else
# define NAND_HAVE_EBICS0 0
#endif
#ifdef CONFIG_SAMA5_EBICS1_NAND
# define HAVE_NAND 1
# define NAND_HAVE_EBICS1 1
#else
# define NAND_HAVE_EBICS1 0
#endif
#ifdef CONFIG_SAMA5_EBICS2_NAND
# define HAVE_NAND 1
# define NAND_HAVE_EBICS2 1
#else
# define NAND_HAVE_EBICS2 0
#endif
#ifdef CONFIG_SAMA5_EBICS3_NAND
# define HAVE_NAND 1
# define NAND_HAVE_EBICS3 1
#else
# define NAND_HAVE_EBICS3 0
#endif
/* Count the number of banks configured for NAND */
#define NAND_NBANKS \
(NAND_HAVE_EBICS0 + NAND_HAVE_EBICS1 + NAND_HAVE_EBICS2 + NAND_HAVE_EBICS3)
#ifdef HAVE_NAND
/****************************************************************************
* Public Types
****************************************************************************/
@@ -200,14 +240,8 @@ struct sam_nandcs_s
/* Static configuration */
uint8_t cs; /* Chip select number (0..3) */
/* Dynamic state */
volatile bool cmddone; /* True: NFC commnad has completed */
volatile bool xfrdone; /* True: Transfer has completed */
volatile bool rbedge; /* True: Ready/busy edge detected */
volatile bool dmadone; /* True: DMA has completed */
sem_t waitsem; /* Used to wait for one of the above states */
sem_t waitsem; /* Used to wait for DMA done */
DMA_HANDLE dma; /* DMA channel assigned to this CS */
int result; /* The result of the DMA */
@@ -216,6 +250,14 @@ struct sam_nandcs_s
struct sam_nand_s
{
bool initialized; /* True: One time initialization is complete */
sem_t exclsem; /* Enforce exclusive access to the SMC hardware */
/* Dynamic state */
volatile bool cmddone; /* True: NFC commnad has completed */
volatile bool xfrdone; /* True: Transfer has completed */
volatile bool rbedge; /* True: Ready/busy edge detected */
sem_t waitsem; /* Used to wait for one of the above states */
#ifdef NAND_HAVE_PMECC
uint8_t ecctab[CONFIG_MTD_NAND_MAX_PMECCSIZE];
@@ -410,4 +452,5 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval)
#endif
#endif /* __ASSEMBLY__ */
#endif /* HAVE_NAND */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_NAND_H */
arch/arm/src/sama5/sam_pmecc.c
+52 -1
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@@ -134,11 +134,29 @@ struct sam_pmecc_s
struct pmecc_desc_s desc; /* Atmel PMECC descriptor */
};
/* This is the type of the ROM detection/correction function
*
* REVISIT: Whare are the types Pmecc and Pmerrloc?
*/
#ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO
typedef uint32_t (*pmecc_correctionalgo_t)(Pmecc *, Pmerrloc *,
struct pmecc_desc_s *desc,
uint32_t isr, uintptr_t data);
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
#ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO
# define pmecc_correctionalgo \
(pmecc_correctionalgo_t)CONFIG_SAMA5_PMECC_EMBEDDEDALGO_ADDR)
#else
static uint32_t pmecc_correctionalgo(uint32_t isr, uintptr_t data);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* PMECC state data */
@@ -418,6 +436,39 @@ void pmecc_unlock(void)
}
#endif
/****************************************************************************
* Name: pmecc_correction
*
* Description:
* Perform the PMECC correction algorithm
*
* Input Parameters:
* isr - Value of the PMECC ISR register
* data - Data to be corrected
*
* Returned Value:
* OK on success; a negated errno value on failure
*
* Assumptions:
* PMECC has been initialized for the CS and the caller holds the PMECC
* lock.
*
****************************************************************************/
int pmecc_correction(uint32_t isr, uintptr_t data)
{
#ifdef CONFIG_SAMA5_PMECC_EMBEDDEDALGO
/* REVISIT: Whare are the types Pmecc and Pmerrloc? */
/* REVISIT: Check returned value */
return pmecc_correctionalgo(??, ??, &g_pmecc, isr, data);
#else
/* REVISIT: Check returned value */
return pmecc_correctionalgo(isr, data);
#endif
}
/****************************************************************************
* Name: pmecc_get*
*
arch/arm/src/sama5/sam_pmecc.h
+21
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@@ -294,6 +294,27 @@ struct sam_nandcs_s;
int pmecc_configure(struct sam_nandcs_s *priv, uint16_t eccoffset,
bool protected);
/****************************************************************************
* Name: pmecc_correction
*
* Description:
* Perform the PMECC correction algorithm
*
* Input Parameters:
* isr - Value of the PMECC ISR register
* data - Data to be corrected
*
* Returned Value:
* OK on success; a negated errno value on failure
*
* Assumptions:
* PMECC has been initialized for the CS and the caller holds the PMECC
* lock.
*
****************************************************************************/
int pmecc_correction(uint32_t isr, uintptr_t data);
/****************************************************************************
* Name: pmecc_get*
*