Merged nuttx/nuttx into master

ChangeLog

@@ -11625,13 +11625,13 @@
 	* configs/nucleus2g:  Removed the Nucleus2G configuration.  There has
 	  not been any activity with the commercial board in a few years and it
 	  no longer appears to be available from the 2g-eng.com website.
-	  Since the board is commercial and no longer publically available, it
+	  Since the board is commercial and no longer publicly available, it
 	  no longer qualifies for inclusion in the open source repositories.
 	  The code as of this data is still available in the Obsoleted
 	  repository at configs/nucleus2g (2016-04-12).
 	* arch/arm/src/stm32l4: Fix the STM32L4 SPI driver.  That SPI driver is
 	  quite different. They now handle frames of arbitrary size between 4
-	  and 16 bits. It was broken before a new bit has to be set (rx fifo
+	  and 16 bits. It was broken before a new bit has to be set (RX fifo
 	  threshold) to handle <= 8-bit transactions. If not set, the default is
 	  16-bit packed >=8-bit frames and the RXNE bit is never set (it is set
 	  when 16-bits are received). weird things as always.
@@ -11671,7 +11671,50 @@
 	* arch/arm/src/stm32 and configs/stm32f429i-disco:  Correct some bad
 	  commits that broke the LTDC display example.  From Marco Krahl
 	  (2016-04-22).
-	* configs/samv71-xult/vnwwm:  Add a more complex NxWM configuration
+	* configs/samv71-xult/vncwwm:  Add a more complex NxWM configuration
 	  to support further VNC testing (particularly of VNC keyboard and
-          mouse intputs).  Initial configuration is not functional (2016-04-23).
+	  mouse inputs).  Initial configuration is not functional (2016-04-23).
-
+	* arch/arm/src/stm32l4: Add support for QSPI DMA. From Dave
+	  dev@ziggurat29.com (2016-04-24).
+	* configs/stm32l476vg-disco: Update stm32l4 disco board to reflect QSPI
+	  DMA support. From Dave dev@ziggurat29.com (2016-04-24).
+	* arch/arm/src/stm32l4: Add configuration options to allow SRAM2 to be
+	  used for heap, or not at all, and to zero-initialize it on OS start,
+	  or not at all. From Dave dev@ziggurat29.com (2016-04-24).
+	* drivers/mtd/smart.c:  Return code of smart_scan not checked, can
+	  cause success result in failure case, leading to 'dev' pointer being
+	  invalid. From Dave dev@ziggurat29.com (2016-04-27).
+	* arch/arm/src/stm32l4: Add support for QSPI memory mapped mode. From
+	  Dave dev@ziggurat29.com (2016-04-27).
+	* configs/stm32l476vg-disco: Add board ioctls for allowing user
+	  application to cause QSPI memory mapped mode to be engaged and
+	  disengaged.  Also partitioned QSPI flash for file system and other
+	 (eventually xip).  From Dave dev@ziggurat29.com (2016-04-27).
+	* fs/mount: Fix a backward debug assertion.  Noted by David Sidrane
+	  (2016-04-29).
+	* arch/arm/src/stm32l4: Add support for HSE and MSI clocks, and auto
+	  trim of MSI to LSE (needed for USB).  From Dave dev@ziggurat29.com
+	  (2016-04-29).
+	* arch/arm/src/stm32l4: Add support for unique id function to arch;
+	  modified board to support unique id boardctl.  From Dave
+	  dev@ziggurat29.com (2016-05-03).
+	* Makefile.unix and tools/mkexport.sh: Pass top-level make to the
+	  script to allow -j greater than 1.  From David Sidrane (2016-05-04).
+	* arch/arm/src/stm32, stm32f7, stm32l4: Fix typo in variable name in
+	  serial BREAK logic.  Review other serial implementations for similar
+	  naming problems. (2016-05-05).
+	* arch/arm/src/samv7:  Fix typo in MATRIX register definitions.  From
+	  Stefan Kolb (2016-05-06).
+	* arch/arm/src/stm32l4: Problem with resetting backup domain clears
+	  clocking options set up before in *rcc.c use INITS flag to avoid magic
+	  reg value to detect power up reset state of RTC correct a problem
+	  clearing interrupt flags (they weren't) which prevented an alarm from
+	  ever being used more than once per reset cycle.  From Dave
+	  dev@ziggurat29.com (2016-05-07).
+	* arch/arm/src/tiva: Fix a bug of GPIO falling-edge interrupt for tiva.
+	  From Young (2016-05-07).
+	* drivrs/mtd:  Add a driver for SST26F spi/qspi flash devices (SPI mode
+	  only).  From Sebastien Lorquet (2016-05-10).
+	* Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
+	  message weirdness when 'make clean' is done with no .config or Make.defs
+	  file (2016-05-10).

Kconfig

@@ -574,16 +574,6 @@ config DEBUG_INPUT
 		this debug option is board-specific and may not be available for
 		some boards.
 
-config DEBUG_DISCRETE
-	bool "Discrete I/O Debug Output"
-	default n
-	depends on DISCRETE_IO
-	---help---
-		Enable low level debug SYSLOG output from the discrete I/O device
-		drivers such as LEDs and I/O expanders (disabled by default).
-		Support for this debug option is board-specific and may not be
-		available for some boards.
-
 config DEBUG_ANALOG
 	bool "Analog Device Debug Output"
 	default n

Makefile.unix

@@ -507,7 +507,7 @@ gconfig: apps_preconfig
 # that the archiver is 'ar'
 
 export: pass2deps
-	$(Q) $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)"
+	$(Q) MAKE=${MAKE} $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)"
 
 # General housekeeping targets:  dependencies, cleaning, etc.
 #

arch/arm/src/dm320/dm320_serial.c

@@ -268,6 +268,7 @@ static inline void up_waittxready(struct up_dev_s *priv)
 static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
 {
   uint16_t lcr = up_serialin(priv, UART_LCR);
+
   if (enable)
     {
       lcr |= UART_LCR_BOC;
@@ -276,6 +277,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
     {
       lcr &= ~UART_LCR_BOC;
     }
+
   up_serialout(priv, UART_LCR, lcr);
 }
 

arch/arm/src/lpc214x/lpc214x_serial.c

@@ -272,6 +272,7 @@ static inline void up_waittxready(struct up_dev_s *priv)
 static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
 {
   uint8_t lcr = up_serialin(priv, LPC214X_UART_LCR_OFFSET);
+
   if (enable)
     {
       lcr |= LPC214X_LCR_BREAK_ENABLE;
@@ -280,6 +281,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
     {
       lcr &= ~LPC214X_LCR_BREAK_ENABLE;
     }
+
   up_serialout(priv, LPC214X_UART_LCR_OFFSET, lcr);
 }
 

arch/arm/src/lpc2378/lpc23xx_serial.c

@@ -290,6 +290,7 @@ static inline void up_waittxready(struct up_dev_s *priv)
 static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
 {
   uint8_t lcr = up_serialin(priv, UART_LCR_OFFSET);
+
   if (enable)
     {
       lcr |= LCR_BREAK_ENABLE;
@@ -298,6 +299,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
     {
       lcr &= ~LCR_BREAK_ENABLE;
     }
+
   up_serialout(priv, UART_LCR_OFFSET, lcr);
 }
 

arch/arm/src/lpc43xx/lpc43_serial.c

@@ -551,6 +551,7 @@ static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier)
 static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
 {
   uint32_t lcr = up_serialin(priv, LPC43_UART_LCR_OFFSET);
+
   if (enable)
     {
       lcr |= UART_LCR_BRK;
@@ -559,6 +560,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
     {
       lcr &= ~UART_LCR_BRK;
     }
+
   up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr);
 }
 

arch/arm/src/samv7/chip/sam_matrix.h

@@ -101,7 +101,7 @@
                                                 /* 0x006c8-0x00fc: Reserved */
 #define SAM_MATRIX_MRCR_OFFSET           0x0100 /* Master Remap Control Register */
                                                 /* 0x0104-0x010c: Reserved */
-#define SAM_MATRIX_CAN0_OFFSET           0x0100 /* Master Remap Control Register */
+#define SAM_MATRIX_CAN0_OFFSET           0x0110 /* CAN0 Configuration Register */
 #define SAM_MATRIX_CCFG_SYSIO_OFFSET     0x0114 /* System I/O Configuration Register */
                                                 /* 0x0118-0x0120: Reserved */
 #define SAM_MATRIX_CCFG_SMCNFCS_OFFSET   0x0124 /* SMC Chip Select NAND Flash Assignment Register */

arch/arm/src/stm32/stm32_serial.c

@@ -2060,8 +2060,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #ifdef CONFIG_USART_BREAKS
     case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
       {
-        irqstate_t flags = enter_critical_section();
+        uint32_t cr2;
-        uint32_t cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET);
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
         up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN);
         leave_critical_section(flags);
       }
@@ -2069,9 +2072,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 
     case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
       {
+        uint32_t cr2;
         irqstate_t flags;
+
         flags = enter_critical_section();
-        uint32_t cr1 = up_serialin(priv, STM32_USART_CR2_OFFSET);
+        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
         up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN);
         leave_critical_section(flags);
       }

arch/arm/src/stm32f7/stm32_serial.c

@@ -1967,8 +1967,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #ifdef CONFIG_USART_BREAKS
     case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
       {
-        irqstate_t flags = enter_critical_section();
+        uint32_t cr2;
-        uint32_t cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET);
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
         up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN);
         leave_critical_section(flags);
       }
@@ -1976,9 +1979,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 
     case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
       {
+        uint32_t cr2;
         irqstate_t flags;
+
         flags = enter_critical_section();
-        uint32_t cr1 = up_serialin(priv, STM32_USART_CR2_OFFSET);
+        cr2   = up_serialin(priv, STM32_USART_CR2_OFFSET);
         up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN);
         leave_critical_section(flags);
       }

arch/arm/src/stm32l4/Make.defs

@@ -114,7 +114,7 @@ endif
 CHIP_ASRCS  =
 CHIP_CSRCS  = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c
 CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c
-CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c
+CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c
 CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c
 
 ifneq ($(CONFIG_SCHED_TICKLESS),y)

arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h

@@ -120,8 +120,8 @@
 
 /* Clock control register */
 
-#define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Medium Speed clock enable */
+#define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Medium Speed clock ready flag */
+#define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Multi Speed clock ready flag */
 #define RCC_CR_MSIPLLEN             (1 << 2)  /* Bit 2: MSI clock PLL enable */
 #define RCC_CR_MSIRGSEL             (1 << 3)  /* Bit 2: MSI clock range selection */
 #define RCC_CR_MSIRANGE_SHIFT       (4)       /* Bits 7-4: MSI clock range */
@@ -161,9 +161,9 @@
 #define RCC_CR_HSITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
 #define RCC_CR_HSICAL_SHIFT         (16)      /* Bits 23-16: Internal High Speed clock Calibration */
 #define RCC_CR_HSICAL_MASK          (0xff << RCC_CR_HSICAL_SHIFT)
-#define RCC_CR_MSITRIM_SHIFT        (8)       /* Bits 15-8: Internal Medium Speed clock trimming */
+#define RCC_CR_MSITRIM_SHIFT        (8)       /* Bits 15-8: Internal Multi Speed clock trimming */
 #define RCC_CR_MSITRIM_MASK         (0xff << RCC_CR_MSITRIM_SHIFT)
-#define RCC_CR_MSICAL_SHIFT         (0)       /* Bits 7-0: Internal Menium Speed clock Calibration */
+#define RCC_CR_MSICAL_SHIFT         (0)       /* Bits 7-0: Internal Multi Speed clock Calibration */
 #define RCC_CR_MSICAL_MASK          (0xff << RCC_CR_MSICAL_SHIFT)
 
 /* Clock configuration register */

arch/arm/src/stm32l4/stm32l4_allocateheap.c

@@ -104,13 +104,13 @@
 #define SRAM2_START 0x10000000
 #define SRAM2_END   0x10008000
 
-#if defined(STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP)
+#if defined(CONFIG_STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP)
 #  if CONFIG_MM_REGIONS < 3
 #    error you need at least 3 memory manager regions to support SRAM2 and FSMC
 #  endif
 #endif
 
-#if defined(STM32L4_SRAM2_HEAP) || defined(CONFIG_STM32L4_FSMC_SRAM_HEAP)
+#if defined(CONFIG_STM32L4_SRAM2_HEAP) || defined(CONFIG_STM32L4_FSMC_SRAM_HEAP)
 #  if CONFIG_MM_REGIONS < 2
 #    error you need at least 2 memory manager regions to support SRAM2 or FSMC
 #  endif

arch/arm/src/stm32l4/stm32l4_exti_alarm.c

@@ -54,10 +54,6 @@
 #include "stm32l4_gpio.h"
 #include "stm32l4_exti.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -66,10 +62,6 @@
 
 static xcpt_t stm32l4_exti_callback;
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -86,17 +78,17 @@ static int stm32l4_exti_alarm_isr(int irq, void *context)
 {
   int ret = OK;
 
-  /* Clear the pending EXTI interrupt */
+  /* Dispatch the interrupt to the handler */
-
-  putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR);
-
-  /* And dispatch the interrupt to the handler */
 
   if (stm32l4_exti_callback)
     {
       ret = stm32l4_exti_callback(irq, context);
     }
 
+  /* Clear the pending EXTI interrupt */
+
+  putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR);
+
   return ret;
 }
 

arch/arm/src/stm32l4/stm32l4_rtc.h

@@ -43,6 +43,7 @@
 #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H
 #define __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H
 
+#include <time.h>
 #include <nuttx/config.h>
 
 #include "chip.h"
@@ -62,9 +63,30 @@
 
 #ifndef __ASSEMBLY__
 
+#ifdef CONFIG_RTC_ALARM
+
 /* The form of an alarm callback */
 
-typedef CODE void (*alarmcb_t)(void);
+typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid);
+
+enum alm_id_e
+{
+  RTC_ALARMA = 0,              /* RTC ALARM A */
+  RTC_ALARMB,                  /* RTC ALARM B */
+  RTC_ALARM_LAST
+};
+
+/* Structure used to pass parmaters to set an alarm */
+
+struct alm_setalarm_s
+{
+  int as_id;                   /* enum alm_id_e */
+  struct tm as_time;           /* Alarm expiration time */
+  alm_callback_t as_cb;        /* Callback (if non-NULL) */
+  FAR void *as_arg;            /* Argument for callback */
+};
+
+#endif /* CONFIG_RTC_ALARM */
 
 /****************************************************************************
  * Public Data
@@ -93,8 +115,7 @@ extern "C"
  *   during initialization to set up the system time when CONFIG_RTC and
  *   CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
  *
- *   NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
+ *   NOTE: The sub-second accuracy is returned through 'nsec'.
- *   That sub-second accuracy is returned through 'nsec'.
  *
  * Input Parameters:
  *   tp - The location to return the high resolution time value.
@@ -130,43 +151,39 @@ struct tm;
 int stm32l4_rtc_setdatetime(FAR const struct tm *tp);
 #endif
 
+#ifdef CONFIG_RTC_ALARM
 /****************************************************************************
  * Name: stm32l4_rtc_setalarm
  *
  * Description:
- *   Set up an alarm.
+ *   Set an alarm to an asbolute time using associated hardware.
  *
  * Input Parameters:
- *   tp - the time to set the alarm
+ *  alminfo - Information about the alarm configuration.
- *   callback - the function to call when the alarm expires.
  *
  * Returned Value:
  *   Zero (OK) on success; a negated errno on failure
  *
  ****************************************************************************/
 
-#ifdef CONFIG_RTC_ALARM
+int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo);
-struct timespec;
-int stm32l4_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
-#endif
 
 /****************************************************************************
  * Name: stm32l4_rtc_cancelalarm
  *
  * Description:
- *   Cancel a pending alarm alarm
+ *   Cancel an alaram.
  *
  * Input Parameters:
- *   none
+ *  alarmid - Identifies the alarm to be cancelled
  *
  * Returned Value:
  *   Zero (OK) on success; a negated errno on failure
  *
  ****************************************************************************/
 
-#ifdef CONFIG_RTC_ALARM
+int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid);
-int stm32l4_rtc_cancelalarm(void);
+#endif /* CONFIG_RTC_ALARM */
-#endif
 
 /****************************************************************************
  * Name: stm32l4_rtc_lowerhalf

arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c

@@ -34,8 +34,6 @@
  *
  ****************************************************************************/
 
-/* REVISIT:  This driver is *not* thread-safe! */
-
 /****************************************************************************
  * Included Files
  ****************************************************************************/
@@ -44,6 +42,7 @@
 
 #include <sys/types.h>
 #include <stdbool.h>
+#include <string.h>
 #include <errno.h>
 
 #include <nuttx/arch.h>
@@ -54,10 +53,25 @@
 
 #ifdef CONFIG_RTC_DRIVER
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STM32_NALARMS 2
+
 /****************************************************************************
  * Private Types
  ****************************************************************************/
 
+#ifdef CONFIG_RTC_ALARM
+struct stm32l4_cbinfo_s
+{
+  volatile rtc_alarm_callback_t cb;  /* Callback when the alarm expires */
+  volatile FAR void *priv;           /* Private argurment to accompany callback */
+  uint8_t id;                        /* Identifies the alarm */
+};
+#endif
+
 /* This is the private type for the RTC state.  It must be cast compatible
  * with struct rtc_lowerhalf_s.
  */
@@ -73,11 +87,20 @@ struct stm32l4_lowerhalf_s
   /* Data following is private to this driver and not visible outside of
    * this file.
    */
+
+  sem_t devsem;         /* Threads can only exclusively access the RTC */
+
+#ifdef CONFIG_RTC_ALARM
+  /* Alarm callback information */
+
+  struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS];
+#endif
 };
 
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
+
 /* Prototypes for static methods in struct rtc_ops_s */
 
 static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower,
@@ -85,6 +108,15 @@ static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower,
 static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower,
                            FAR const struct rtc_time *rtctime);
 
+#ifdef CONFIG_RTC_ALARM
+static int stm32l4_setalarm(FAR struct rtc_lowerhalf_s *lower,
+                          FAR const struct lower_setalarm_s *alarminfo);
+static int stm32l4_setrelative(FAR struct rtc_lowerhalf_s *lower,
+                             FAR const struct lower_setrelative_s *alarminfo);
+static int stm32l4_cancelalarm(FAR struct rtc_lowerhalf_s *lower,
+                             int alarmid);
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -96,9 +128,9 @@ static const struct rtc_ops_s g_rtc_ops =
   .rdtime      = stm32l4_rdtime,
   .settime     = stm32l4_settime,
 #ifdef CONFIG_RTC_ALARM
-  .setalarm    = NULL,
+  .setalarm    = stm32l4_setalarm,
-  .setrelative = NULL,
+  .setrelative = stm32l4_setrelative,
-  .cancelalarm = NULL,
+  .cancelalarm = stm32l4_cancelalarm,
 #endif
 #ifdef CONFIG_RTC_IOCTL
   .ioctl       = NULL,
@@ -120,7 +152,55 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf =
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32l4_rdtime
+ * Name: stm32l4_alarm_callback
+ *
+ * Description:
+ *   This is the function that is called from the RTC driver when the alarm
+ *   goes off.  It just invokes the upper half drivers callback.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static void stm32l4_alarm_callback(FAR void *arg, unsigned int alarmid)
+{
+  FAR struct stm32l4_lowerhalf_s *lower;
+  FAR struct stm32l4_cbinfo_s *cbinfo;
+  rtc_alarm_callback_t cb;
+  FAR void *priv;
+
+  DEBUGASSERT(priv != NULL);
+  DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
+
+  lower        = (struct stm32l4_lowerhalf_s *)arg;
+  cbinfo       = &lower->cbinfo[alarmid];
+
+  /* Sample and clear the callback information to minimize the window in
+   * time in which race conditions can occur.
+   */
+
+  cb           = (rtc_alarm_callback_t)cbinfo->cb;
+  priv         = (FAR void *)cbinfo->priv;
+
+  cbinfo->cb   = NULL;
+  cbinfo->priv = NULL;
+
+  /* Perform the callback */
+
+  if (cb != NULL)
+    {
+      cb(priv, alarmid);
+    }
+}
+#endif /* CONFIG_RTC_ALARM */
+
+/****************************************************************************
+ * Name: stm32_rdtime
  *
  * Description:
  *   Implements the rdtime() method of the RTC driver interface
@@ -138,11 +218,25 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf =
 static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower,
                           FAR struct rtc_time *rtctime)
 {
+  FAR struct stm32l4_lowerhalf_s *priv;
+  int ret;
+
+  priv = (FAR struct stm32l4_lowerhalf_s *)lower;
+
+  if (sem_wait(&priv->devsem) != OK)
+   {
+     return -errno;
+   }
+
   /* This operation depends on the fact that struct rtc_time is cast
    * compatible with struct tm.
    */
 
-  return up_rtc_getdatetime((FAR struct tm *)rtctime);
+  ret = up_rtc_getdatetime((FAR struct tm *)rtctime);
+
+  sem_post(&priv->devsem);
+  
+  return ret;
 }
 
 /****************************************************************************
@@ -164,13 +258,223 @@ static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower,
 static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower,
                            FAR const struct rtc_time *rtctime)
 {
+  FAR struct stm32l4_lowerhalf_s *priv;
+  int ret;
+
+  priv = (FAR struct stm32l4_lowerhalf_s *)lower;
+
+  if (sem_wait(&priv->devsem) != OK)
+   {
+     return -errno;
+   }
+
    /* This operation depends on the fact that struct rtc_time is cast
    * compatible with struct tm.
    */
 
-  return stm32l4_rtc_setdatetime((FAR const struct tm *)rtctime);
+  ret = stm32l4_rtc_setdatetime((FAR const struct tm *)rtctime);
+  
+  sem_post(&priv->devsem);
+
+  return ret;
 }
 
+/****************************************************************************
+ * Name: stm32l4_setalarm
+ *
+ * Description:
+ *   Set a new alarm.  This function implements the setalarm() method of the
+ *   RTC driver interface
+ *
+ * Input Parameters:
+ *   lower - A reference to RTC lower half driver state structure
+ *   alarminfo - Provided information needed to set the alarm
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static int stm32l4_setalarm(FAR struct rtc_lowerhalf_s *lower,
+                            FAR const struct lower_setalarm_s *alarminfo)
+{
+  FAR struct stm32l4_lowerhalf_s *priv;
+  FAR struct stm32l4_cbinfo_s *cbinfo;
+  struct alm_setalarm_s lowerinfo;
+  int ret = -EINVAL;
+
+  /* ID0-> Alarm A; ID1 -> Alarm B */
+
+  DEBUGASSERT(lower != NULL && alarminfo != NULL);
+  DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
+  priv = (FAR struct stm32l4_lowerhalf_s *)lower;
+
+  if (sem_wait(&priv->devsem) != OK)
+   {
+     return -errno;
+   }
+
+  if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB)
+    {
+      /* Remember the callback information */
+
+      cbinfo            = &priv->cbinfo[alarminfo->id];
+      cbinfo->cb        = alarminfo->cb;
+      cbinfo->priv      = alarminfo->priv;
+      cbinfo->id        = alarminfo->id;
+
+      /* Set the alarm */
+
+      lowerinfo.as_id   = alarminfo->id;
+      lowerinfo.as_cb   = stm32l4_alarm_callback;
+      lowerinfo.as_arg  = priv;
+      memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm));
+
+      /* And set the alarm */
+
+      ret = stm32l4_rtc_setalarm(&lowerinfo);
+      if (ret < 0)
+        {
+          cbinfo->cb   = NULL;
+          cbinfo->priv = NULL;
+        }
+    }
+
+  sem_post(&priv->devsem);
+
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32l4_setrelative
+ *
+ * Description:
+ *   Set a new alarm relative to the current time.  This function implements
+ *   the setrelative() method of the RTC driver interface
+ *
+ * Input Parameters:
+ *   lower - A reference to RTC lower half driver state structure
+ *   alarminfo - Provided information needed to set the alarm
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static int stm32l4_setrelative(FAR struct rtc_lowerhalf_s *lower,
+                               FAR const struct lower_setrelative_s *alarminfo)
+{
+  struct lower_setalarm_s setalarm;
+  struct tm time;
+  time_t seconds;
+  int ret = -EINVAL;
+
+  ASSERT(lower != NULL && alarminfo != NULL);
+  DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB);
+
+  if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) &&
+      alarminfo->reltime > 0)
+    {
+      /* Disable pre-emption while we do this so that we don't have to worry
+       * about being suspended and working on an old time.
+       */
+
+      sched_lock();
+
+      /* Get the current time in broken out format */
+
+      ret = up_rtc_getdatetime(&time);
+      if (ret >= 0)
+        {
+          /* Convert to seconds since the epoch */
+
+          seconds = mktime(&time);
+
+          /* Add the seconds offset.  Add one to the number of seconds
+           * because we are unsure of the phase of the timer.
+           */
+
+          seconds += (alarminfo->reltime + 1);
+
+          /* And convert the time back to broken out format */
+
+          (void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
+
+          /* The set the alarm using this absolute time */
+
+          setalarm.id   = alarminfo->id;
+          setalarm.cb   = alarminfo->cb;
+          setalarm.priv = alarminfo->priv;
+
+          ret = stm32l4_setalarm(lower, &setalarm);
+        }
+
+      sched_unlock();
+    }
+
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32l4_cancelalarm
+ *
+ * Description:
+ *   Cancel the current alarm.  This function implements the cancelalarm()
+ *   method of the RTC driver interface
+ *
+ * Input Parameters:
+ *   lower - A reference to RTC lower half driver state structure
+ *   alarminfo - Provided information needed to set the alarm
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned
+ *   on any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static int stm32l4_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid)
+{
+  FAR struct stm32l4_lowerhalf_s *priv;
+  FAR struct stm32l4_cbinfo_s *cbinfo;
+  int ret = -EINVAL;
+
+  DEBUGASSERT(lower != NULL);
+  DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB);
+  priv = (FAR struct stm32l4_lowerhalf_s *)lower;
+
+  if (sem_wait(&priv->devsem) != OK)
+   {
+     return -errno;
+   }
+
+  /* ID0-> Alarm A; ID1 -> Alarm B */
+
+  if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB)
+    {
+      /* Nullify callback information to reduce window for race conditions */
+
+      cbinfo       = &priv->cbinfo[alarmid];
+      cbinfo->cb   = NULL;
+      cbinfo->priv = NULL;
+
+      /* Then cancel the alarm */
+
+      ret = stm32l4_rtc_cancelalarm((enum alm_id_e)alarmid);
+    }
+
+  sem_post(&priv->devsem);
+
+  return ret;
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -199,6 +503,8 @@ static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower,
 
 FAR struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void)
 {
+  sem_init(&g_rtc_lowerhalf.devsem, 0, 1);
+
   return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
 }
 

arch/arm/src/stm32l4/stm32l4_serial.c

@@ -1723,8 +1723,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 #ifdef CONFIG_USART_BREAKS
     case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
       {
-        irqstate_t flags = enter_critical_section();
+        uint32_t cr2;
-        uint32_t cr2 = up_serialin(priv, STM32L4_USART_CR2_OFFSET);
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr2   = up_serialin(priv, STM32L4_USART_CR2_OFFSET);
         up_serialout(priv, STM32L4_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN);
         leave_critical_section(flags);
       }
@@ -1732,9 +1735,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
 
     case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
       {
+        uint32_t cr2;
         irqstate_t flags;
+
         flags = enter_critical_section();
-        uint32_t cr1 = up_serialin(priv, STM32L4_USART_CR2_OFFSET);
+        cr2   = up_serialin(priv, STM32L4_USART_CR2_OFFSET);
         up_serialout(priv, STM32L4_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN);
         leave_critical_section(flags);
       }

arch/arm/src/stm32l4/stm32l4_uid.c

@@ -0,0 +1,63 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_uid.c
+ *
+ *   Copyright (C) 2015 Marawan Ragab. All rights reserved.
+ *   Author: Marawan Ragab <marawan31@gmail.com>
+ *           dev@ziggurat9.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <chip/stm32l4_memorymap.h>
+
+#include "stm32l4_uid.h"
+
+#ifdef STM32L4_SYSMEM_UID
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+void stm32l4_get_uniqueid(uint8_t uniqueid[12])
+{
+  int i;
+
+  for (i = 0; i < 12; i++)
+    {
+      uniqueid[i] = *((uint8_t*)(STM32L4_SYSMEM_UID)+i);
+    }
+}
+
+#endif /* STM32L4_SYSMEM_UID */

arch/arm/src/stm32l4/stm32l4_uid.h

@@ -0,0 +1,52 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_uid.h
+ *
+ *   Copyright (C) 2015 Marawan Ragab. All rights reserved.
+ *   Author: Marawan Ragab <marawan31@gmail.com>
+ *           dev@ziggurat9.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H
+#define __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <stdint.h>
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+void stm32l4_get_uniqueid(uint8_t uniqueid[12]);
+
+#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H */

arch/arm/src/stm32l4/stm32l4x6xx_rcc.c

@@ -57,9 +57,10 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
-/* Same for HSI */
+/* Same for HSI and MSI */
 
 #define HSIRDY_TIMEOUT HSERDY_TIMEOUT
+#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
 
 /* HSE divisor to yield ~1MHz RTC clock */
 
@@ -578,14 +579,38 @@ static void stm32l4_stdclockconfig(void)
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
 
-#  error STM32L4_BOARD_USEMSI not yet implemented in arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+  /* Wait until the MSI is either off or ready (or until a timeout elapsed) */
+
+  for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
   /* setting MSIRANGE */
-  /* setting MSIPLLEN */
 
   regval  = getreg32(STM32L4_RCC_CR);
-  regval |= RCC_CR_MSION;           /* Enable MSI */
+  regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION);    /* Enable MSI and frequency */
   putreg32(regval, STM32L4_RCC_CR);
 
+  /* Wait until the MSI is ready (or until a timeout elapsed) */
+
+  for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      /* Check if the MSIRDY flag is the set in the CR */
+
+      if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
 #elif defined(STM32L4_BOARD_USEHSE)
   /* Enable External High-Speed Clock (HSE) */
 
@@ -696,6 +721,8 @@ static void stm32l4_stdclockconfig(void)
 
 #ifdef STM32L4_BOARD_USEHSI
       regval |= RCC_PLLCFG_PLLSRC_HSI;
+#elif defined(STM32L4_BOARD_USEMSI)
+      regval |= RCC_PLLCFG_PLLSRC_MSI;
 #else /* if STM32L4_BOARD_USEHSE */
       regval |= RCC_PLLCFG_PLLSRC_HSE;
 #endif
@@ -827,12 +854,20 @@ static void stm32l4_stdclockconfig(void)
        * and we need to ensure it is first off before doing so.
        */
 
-      /* turn on the LSE oscillator
+      /* Turn on the LSE oscillator
        * XXX this will almost surely get moved since we also want to use
        * this for automatically trimming MSI, etc.
        */
 
       stm32l4_rcc_enablelse();
+
+#  if defined(STM32L4_BOARD_USEMSI)
+      /* Now that LSE is up, auto trim the MSI */
+
+      regval  = getreg32(STM32L4_RCC_CR);
+      regval |= RCC_CR_MSIPLLEN;
+      putreg32(regval, STM32L4_RCC_CR);
+#  endif
 #endif
 
 #if defined(STM32L4_USE_CLK48)

arch/arm/src/tiva/tiva_gpio.c

@@ -661,9 +661,9 @@ static inline void tiva_interrupt(uint32_t pinset)
     {
       case GPIO_INT_FALLINGEDGE:
         {
-          isset  = pin;
+          isclr  = pin;
           ibeclr = pin;
-          ievset = pin;
+          ievclr = pin;
         }
         break;
 

audio/Makefile

@@ -62,6 +62,7 @@ OBJS = $(AOBJS) $(COBJS)
 BIN = libaudio$(LIBEXT)
 
 all: $(BIN)
+.PHONY: depend clean distclean
 
 $(AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)

binfmt/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # nxflat/Makefile
 #
-#   Copyright (C) 2007-2009, 2012-2015 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2009, 2012-2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -80,6 +80,7 @@ BINFMT_OBJS = $(BINFMT_AOBJS) $(BINFMT_COBJS)
 BIN = libbinfmt$(LIBEXT)
 
 all: $(BIN)
+.PHONY: depend clean distclean
 
 $(BINFMT_AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)

configs/Kconfig

@@ -1274,7 +1274,6 @@ config BOARD_CUSTOM_LEDS
 	bool "Custom board LEDs"
 	default n
 	select ARCH_HAVE_LEDS
-	select ARCH_LEDS
 
 config BOARD_CUSTOM_BUTTONS
 	bool "Custom board buttons"

configs/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # configs/Makefile
 #
-#   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -58,6 +58,7 @@ OBJS = $(AOBJS) $(COBJS)
 BIN = libconfigs$(LIBEXT)
 
 all: $(BIN)
+.PHONY: depend clean distclean
 
 $(AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)

configs/nucleo-f303re/uavcan/defconfig

@@ -814,7 +814,7 @@ CONFIG_HAVE_CXXINITIALIZE=y
 #
 CONFIG_CANUTILS_UAVCAN=y
 CONFIG_UAVCAN_LIBUAVCAN_URL="https://github.com/UAVCAN/libuavcan/archive"
-CONFIG_UAVCAN_LIBUAVCAN_VERSION="c152f28a620ceec9f63581a7c99fe77c89938048"
+CONFIG_UAVCAN_LIBUAVCAN_VERSION="b04396ace50155573e545ed9bf2fb09964ee2367"
 CONFIG_UAVCAN_DSDL_URL="https://github.com/UAVCAN/dsdl/archive"
 CONFIG_UAVCAN_DSDL_VERSION="9804a3e6972825586be252ce08dd899f44994b14"
 CONFIG_UAVCAN_PYUAVCAN_URL="https://github.com/UAVCAN/pyuavcan/archive"

configs/nucleo-l476rg/include/nucleo-l476rg.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * configs/nucleo-l476rg/include/nucleo-l476rg.h
  *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,8 +49,19 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
+#if 1
+#  define HSI_CLOCK_CONFIG          /* HSI-16 clock configuration */
+#elif 0
+/* Make sure you installed one! */
+
+#  define HSE_CLOCK_CONFIG          /* HSE with 8 MHz xtal */
+#else
+#  define MSI_CLOCK_CONFIG          /* MSI @ 4 MHz autotrimmed via LSE */
+#endif
+
 /* Clocking *************************************************************************/
 
+#if defined(HSI_CLOCK_CONFIG)
 /* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3).  However, as
  * shipped, the X3 crystal is not populated.  Therefore the Nucleo-L476RG
  * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
@@ -88,6 +99,10 @@
 
 #define STM32L4_BOARD_USEHSI      1
 
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = hsi */
+
 /* REVISIT: Trimming of the HSI and MSI is not yet supported. */
 
 /* Main PLL Configuration.
@@ -245,7 +260,7 @@
 
 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
-//#define STM32L4_USE_LSE           1
+#define STM32L4_USE_LSE           1
 
 /* AHB clock (HCLK) is SYSCLK (80MHz) */
 
@@ -287,6 +302,167 @@
 
 /* TODO SDMMC */
 
+#elif defined(HSE_CLOCK_CONFIG)
+
+/* Use the HSE */
+
+#define STM32L4_BOARD_USEHSE      1
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = hse */
+
+/* Prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(20)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(12)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* Enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* Enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* Configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* Configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#elif defined(MSI_CLOCK_CONFIG)
+
+/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
+
+#define STM32L4_BOARD_USEMSI      1
+#define STM32L4_BOARD_MSIRANGE    RCC_CR_MSIRANGE_4M
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = msi */
+
+/* prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(40)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(24)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* Enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* Enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* Configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* Configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#endif
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/

configs/nucleo-l476rg/nsh/defconfig

@@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y
 #
 # Build Configuration
 #
-CONFIG_APPS_DIR="../apps"
+# CONFIG_APPS_DIR="../apps"
 CONFIG_BUILD_FLAT=y
 # CONFIG_BUILD_2PASS is not set
 
@@ -49,7 +49,6 @@ CONFIG_DEBUG_VERBOSE=y
 #
 # Subsystem Debug Options
 #
-CONFIG_DEBUG_AUDIO=y
 CONFIG_DEBUG_BINFMT=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_GRAPHICS=y
@@ -60,6 +59,7 @@ CONFIG_DEBUG_LIB=y
 #
 # OS Function Debug Options
 #
+# CONFIG_DEBUG_DMA is not set
 # CONFIG_DEBUG_HEAP is not set
 # CONFIG_DEBUG_IRQ is not set
 
@@ -69,6 +69,7 @@ CONFIG_DEBUG_LIB=y
 CONFIG_DEBUG_LEDS=y
 CONFIG_DEBUG_ANALOG=y
 CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_RTC is not set
 CONFIG_DEBUG_SPI=y
 CONFIG_ARCH_HAVE_STACKCHECK=y
 # CONFIG_STACK_COLORATION is not set
@@ -101,7 +102,8 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_CALYPSO is not set
 # CONFIG_ARCH_CHIP_DM320 is not set
 # CONFIG_ARCH_CHIP_EFM32 is not set
-# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
 # CONFIG_ARCH_CHIP_KINETIS is not set
 # CONFIG_ARCH_CHIP_KL is not set
 # CONFIG_ARCH_CHIP_LM is not set
@@ -133,6 +135,7 @@ CONFIG_ARCH_CORTEXM4=y
 # CONFIG_ARCH_CORTEXM7 is not set
 # CONFIG_ARCH_CORTEXA5 is not set
 # CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
 # CONFIG_ARCH_CORTEXR4 is not set
 # CONFIG_ARCH_CORTEXR4F is not set
 # CONFIG_ARCH_CORTEXR5 is not set
@@ -141,6 +144,7 @@ CONFIG_ARCH_CORTEXM4=y
 # CONFIG_ARCH_CORTEXR7F is not set
 CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="stm32l4"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
 CONFIG_ARM_TOOLCHAIN_GNU=y
 # CONFIG_ARMV7M_USEBASEPRI is not set
 CONFIG_ARCH_HAVE_CMNVECTOR=y
@@ -149,6 +153,7 @@ CONFIG_ARMV7M_CMNVECTOR=y
 CONFIG_ARCH_HAVE_FPU=y
 CONFIG_ARCH_HAVE_DPFPU=y
 # CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
 CONFIG_ARM_HAVE_MPU_UNIFIED=y
 # CONFIG_ARM_MPU is not set
 # CONFIG_DEBUG_HARDFAULT is not set
@@ -162,6 +167,7 @@ CONFIG_ARMV7M_HAVE_ITCM=y
 CONFIG_ARMV7M_HAVE_DTCM=y
 # CONFIG_ARMV7M_ITCM is not set
 # CONFIG_ARMV7M_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
@@ -171,6 +177,7 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y
 # CONFIG_ARMV7M_ITMSYSLOG is not set
 # CONFIG_SERIAL_TERMIOS is not set
 # CONFIG_USART2_RS485 is not set
+# CONFIG_USART2_RXDMA is not set
 # CONFIG_SERIAL_DISABLE_REORDERING is not set
 
 #
@@ -185,6 +192,12 @@ CONFIG_STM32L4_STM32L476XX=y
 # CONFIG_STM32L4_FLASH_512KB is not set
 CONFIG_STM32L4_FLASH_1024KB=y
 
+#
+# SRAM2 Options
+#
+CONFIG_STM32L4_SRAM2_HEAP=y
+CONFIG_STM32L4_SRAM2_INIT=y
+
 #
 # STM32L4 Peripheral Support
 #
@@ -192,7 +205,7 @@ CONFIG_STM32L4_FLASH_1024KB=y
 # CONFIG_STM32L4_ADC is not set
 # CONFIG_STM32L4_CAN is not set
 # CONFIG_STM32L4_DAC is not set
-# CONFIG_STM32L4_DMA is not set
+CONFIG_STM32L4_DMA=y
 # CONFIG_STM32L4_I2C is not set
 # CONFIG_STM32L4_SAI is not set
 # CONFIG_STM32L4_SPI is not set
@@ -202,8 +215,8 @@ CONFIG_STM32L4_USART=y
 #
 # AHB1 Peripherals
 #
-# CONFIG_STM32L4_DMA1 is not set
+CONFIG_STM32L4_DMA1=y
-# CONFIG_STM32L4_DMA2 is not set
+CONFIG_STM32L4_DMA2=y
 # CONFIG_STM32L4_CRC is not set
 # CONFIG_STM32L4_TSC is not set
 
@@ -215,17 +228,18 @@ CONFIG_STM32L4_USART=y
 # CONFIG_STM32L4_ADC2 is not set
 # CONFIG_STM32L4_ADC3 is not set
 # CONFIG_STM32L4_AES is not set
-# CONFIG_STM32L4_RNG is not set
+CONFIG_STM32L4_RNG=y
 
 #
 # AHB3 Peripherals
 #
 # CONFIG_STM32L4_FMC is not set
-# CONFIG_STM32L4_QUADSPI is not set
+# CONFIG_STM32L4_QSPI is not set
 
 #
 # APB1 Peripherals
 #
+CONFIG_STM32L4_PWR=y
 # CONFIG_STM32L4_TIM2 is not set
 # CONFIG_STM32L4_TIM3 is not set
 # CONFIG_STM32L4_TIM4 is not set
@@ -276,8 +290,11 @@ CONFIG_STM32L4_FIREWALL=y
 # CONFIG_STM32L4_WWDG is not set
 CONFIG_STM32L4_FLASH_PREFETCH=y
 CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-# CONFIG_STM32L4_CUSTOM_CLOCKCONFIG is not set
+# CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is not set
-# CONFIG_STM32L4_SAI1PLL is not set
+CONFIG_STM32L4_RTC_LSECLOCK=y
+# CONFIG_STM32L4_RTC_LSICLOCK is not set
+# CONFIG_STM32L4_RTC_HSECLOCK is not set
+CONFIG_STM32L4_SAI1PLL=y
 # CONFIG_STM32L4_SAI2PLL is not set
 
 #
@@ -290,12 +307,13 @@ CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
 #
 # CONFIG_ARCH_NOINTC is not set
 # CONFIG_ARCH_VECNOTIRQ is not set
-# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_DMA=y
 CONFIG_ARCH_HAVE_IRQPRIO=y
 # CONFIG_ARCH_L2CACHE is not set
 # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
 # CONFIG_ARCH_HAVE_ADDRENV is not set
 # CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
 CONFIG_ARCH_HAVE_VFORK=y
 # CONFIG_ARCH_HAVE_MMU is not set
 CONFIG_ARCH_HAVE_MPU=y
@@ -346,6 +364,7 @@ CONFIG_RAM_SIZE=98304
 # Board Selection
 #
 CONFIG_ARCH_BOARD_NUCLEO_L476RG=y
+# CONFIG_ARCH_BOARD_STM32L476VG_DISCO is not set
 # CONFIG_ARCH_BOARD_CUSTOM is not set
 CONFIG_ARCH_BOARD="nucleo-l476rg"
 
@@ -362,7 +381,14 @@ CONFIG_NSH_MMCSDMINOR=0
 #
 # Board-Specific Options
 #
-# CONFIG_LIB_BOARDCTL is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_RESET is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_PWMTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
 
 #
 # RTOS Features
@@ -381,9 +407,6 @@ CONFIG_USEC_PER_TICK=10000
 # CONFIG_SYSTEM_TIME64 is not set
 # CONFIG_CLOCK_MONOTONIC is not set
 # CONFIG_JULIAN_TIME is not set
-CONFIG_START_YEAR=2014
-CONFIG_START_MONTH=5
-CONFIG_START_DAY=5
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_PREALLOC_WDOGS=8
 CONFIG_WDOG_INTRESERVE=1
@@ -472,6 +495,8 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048
 CONFIG_DISABLE_POLL=y
 CONFIG_DEV_NULL=y
 # CONFIG_DEV_ZERO is not set
+CONFIG_ARCH_HAVE_RNG=y
+CONFIG_DEV_RANDOM=y
 # CONFIG_DEV_LOOP is not set
 
 #
@@ -500,7 +525,13 @@ CONFIG_SPI_EXCHANGE=y
 # Timer Driver Support
 #
 # CONFIG_TIMER is not set
-# CONFIG_RTC is not set
+CONFIG_RTC=y
+CONFIG_RTC_DATETIME=y
+CONFIG_RTC_ALARM=y
+CONFIG_RTC_NALARMS=2
+CONFIG_RTC_DRIVER=y
+CONFIG_RTC_IOCTL=y
+# CONFIG_RTC_EXTERNAL is not set
 # CONFIG_WATCHDOG is not set
 # CONFIG_ANALOG is not set
 # CONFIG_AUDIO_DEVICES is not set
@@ -514,6 +545,7 @@ CONFIG_SPI_EXCHANGE=y
 # LED Support
 #
 # CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
 # CONFIG_PCA9635PW is not set
 # CONFIG_MMCSD is not set
 # CONFIG_MODEM is not set
@@ -579,7 +611,7 @@ CONFIG_USART2_2STOP=0
 # CONFIG_USART2_DMA is not set
 # CONFIG_USBDEV is not set
 # CONFIG_USBHOST is not set
-# CONFIG_WIRELESS is not set
+# CONFIG_DRIVERS_WIRELESS is not set
 
 #
 # System Logging Device Options
@@ -642,7 +674,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 # Memory Management
 #
 # CONFIG_MM_SMALL is not set
-CONFIG_MM_REGIONS=1
+CONFIG_MM_REGIONS=2
 # CONFIG_ARCH_HAVE_HEAP2 is not set
 # CONFIG_GRAN is not set
 
@@ -651,6 +683,10 @@ CONFIG_MM_REGIONS=1
 #
 # CONFIG_AUDIO is not set
 
+#
+# Wireless Support
+#
+
 #
 # Binary Loader
 #
@@ -694,6 +730,8 @@ CONFIG_ARCH_LOWPUTC=y
 CONFIG_LIB_SENDFILE_BUFSIZE=512
 # CONFIG_ARCH_ROMGETC is not set
 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
 # CONFIG_LIBC_NETDB is not set
 
 #
@@ -731,6 +769,12 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 #
 # Examples
 #
+CONFIG_EXAMPLES_ALARM=y
+CONFIG_EXAMPLES_ALARM_PRIORITY=100
+CONFIG_EXAMPLES_ALARM_STACKSIZE=2048
+CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0"
+CONFIG_EXAMPLES_ALARM_SIGNO=1
+# CONFIG_EXAMPLES_CHAT is not set
 # CONFIG_EXAMPLES_CONFIGDATA is not set
 # CONFIG_EXAMPLES_CPUHOG is not set
 # CONFIG_EXAMPLES_CXXTEST is not set
@@ -770,7 +814,10 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 # CONFIG_EXAMPLES_PIPE is not set
 # CONFIG_EXAMPLES_PPPD is not set
 # CONFIG_EXAMPLES_POSIXSPAWN is not set
-# CONFIG_EXAMPLES_QENCODER is not set
+CONFIG_EXAMPLES_RANDOM=y
+CONFIG_EXAMPLES_MAXSAMPLES=64
+CONFIG_EXAMPLES_NSAMPLES=8
+# CONFIG_EXAMPLES_RGBLED is not set
 # CONFIG_EXAMPLES_RGMP is not set
 # CONFIG_EXAMPLES_SENDMAIL is not set
 # CONFIG_EXAMPLES_SERIALBLASTER is not set
@@ -779,6 +826,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 # CONFIG_EXAMPLES_SLCD is not set
 # CONFIG_EXAMPLES_SMART_TEST is not set
 # CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
 # CONFIG_EXAMPLES_TCPECHO is not set
 # CONFIG_EXAMPLES_TELNETD is not set
 # CONFIG_EXAMPLES_TIFF is not set
@@ -791,6 +839,12 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 #
 # File System Utilities
 #
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
 
 #
 # Graphics Support
@@ -822,6 +876,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 # NSH Library
 #
 CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
 
 #
 # Command Line Configuration
@@ -846,7 +901,7 @@ CONFIG_NSH_BUILTIN_APPS=y
 # CONFIG_NSH_DISABLE_CD is not set
 # CONFIG_NSH_DISABLE_CP is not set
 # CONFIG_NSH_DISABLE_CMP is not set
-CONFIG_NSH_DISABLE_DATE=y
+# CONFIG_NSH_DISABLE_DATE is not set
 # CONFIG_NSH_DISABLE_DD is not set
 # CONFIG_NSH_DISABLE_DF is not set
 # CONFIG_NSH_DISABLE_DELROUTE is not set
@@ -909,7 +964,9 @@ CONFIG_NSH_FILEIOSIZE=512
 #
 CONFIG_NSH_CONSOLE=y
 # CONFIG_NSH_ALTCONDEV is not set
-# CONFIG_NSH_ARCHINIT is not set
+CONFIG_NSH_ARCHINIT=y
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
 
 #
 # NxWidgets/NxWM
@@ -928,7 +985,6 @@ CONFIG_NSH_CONSOLE=y
 # CONFIG_SYSTEM_CUTERM is not set
 # CONFIG_SYSTEM_INSTALL is not set
 # CONFIG_SYSTEM_HEX2BIN is not set
-# CONFIG_SYSTEM_INIFILE is not set
 # CONFIG_SYSTEM_HEXED is not set
 # CONFIG_SYSTEM_RAMTEST is not set
 CONFIG_READLINE_HAVE_EXTMATCH=y
@@ -936,7 +992,8 @@ CONFIG_SYSTEM_READLINE=y
 CONFIG_READLINE_ECHO=y
 # CONFIG_READLINE_TABCOMPLETION is not set
 # CONFIG_READLINE_CMD_HISTORY is not set
-# CONFIG_SYSTEM_RAMTRON is not set
 # CONFIG_SYSTEM_SUDOKU is not set
 # CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
 # CONFIG_SYSTEM_ZMODEM is not set
+# CONFIG_SYSTEM_DISCOTEST is not set

configs/nucleo-l476rg/src/nucleo-l476rg.h

@@ -52,7 +52,15 @@
  ************************************************************************************/
 /* Configuration ********************************************************************/
 
+#define HAVE_RTC_DRIVER       1
 #define HAVE_MMCSD 1
+
+/* Check if we can support the RTC driver */
+
+#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER)
+#  undef HAVE_RTC_DRIVER
+#endif
+
 #if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \
     !defined(CONFIG_MMCSD_SDIO)
 #  undef HAVE_MMCSD

configs/nucleo-l476rg/src/stm32_appinit.c

@@ -55,6 +55,11 @@
 
 #include "nucleo-l476rg.h"
 
+#ifdef HAVE_RTC_DRIVER
+#  include <nuttx/timers/rtc.h>
+#  include "stm32l4_rtc.h"
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -83,9 +88,12 @@ void up_netinitialize(void)
 
 int board_app_initialize(void)
 {
-#if defined(HAVE_MMCSD) || defined(CONFIG_AJOYSTICK)
+#ifdef HAVE_RTC_DRIVER
-  int ret;
+  FAR struct rtc_lowerhalf_s *rtclower;
 #endif
+  int ret;
+
+  (void)ret;
 
   /* Configure CPU load estimation */
 
@@ -93,6 +101,30 @@ int board_app_initialize(void)
   cpuload_initialize_once();
 #endif
 
+#ifdef HAVE_RTC_DRIVER
+  /* Instantiate the STM32L4 lower-half RTC driver */
+
+  rtclower = stm32l4_rtc_lowerhalf();
+  if (!rtclower)
+    {
+      sdbg("ERROR: Failed to instantiate the RTC lower-half driver\n");
+      return -ENOMEM;
+    }
+  else
+    {
+      /* Bind the lower half driver and register the combined RTC driver
+       * as /dev/rtc0
+       */
+
+      ret = rtc_initialize(0, rtclower);
+      if (ret < 0)
+        {
+          sdbg("ERROR: Failed to bind/register the RTC driver: %d\n", ret);
+          return ret;
+        }
+    }
+#endif
+
 #ifdef HAVE_MMCSD
   /* First, get an instance of the SDIO interface */
 

configs/stm32f4discovery/uavcan/defconfig

@@ -843,11 +843,11 @@ CONFIG_HAVE_CXXINITIALIZE=y
 #
 CONFIG_CANUTILS_UAVCAN=y
 CONFIG_UAVCAN_LIBUAVCAN_URL="https://github.com/UAVCAN/libuavcan/archive"
-CONFIG_UAVCAN_LIBUAVCAN_VERSION="531433a3261ff1568e824c240d0f1c6ecef73be1"
+CONFIG_UAVCAN_LIBUAVCAN_VERSION="b04396ace50155573e545ed9bf2fb09964ee2367"
 CONFIG_UAVCAN_DSDL_URL="https://github.com/UAVCAN/dsdl/archive"
 CONFIG_UAVCAN_DSDL_VERSION="9804a3e6972825586be252ce08dd899f44994b14"
 CONFIG_UAVCAN_PYUAVCAN_URL="https://github.com/UAVCAN/pyuavcan/archive"
-CONFIG_UAVCAN_PYUAVCAN_VERSION="4e2798ec3da8e8493b769da514f3b96eea5773e2"
+CONFIG_UAVCAN_PYUAVCAN_VERSION="c58477a644d20ccf95a20c151f3a0402f271c3b8"
 CONFIG_UAVCAN_STM32_NUM_IFACES=1
 # CONFIG_UAVCAN_STM32_TIM2 is not set
 # CONFIG_UAVCAN_STM32_TIM3 is not set

configs/stm32l476vg-disco/include/nsh_romfsimg.h

@@ -0,0 +1,89 @@
+unsigned char romfs_img[] = {
+  0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80,
+  0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56,
+  0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49,
+  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97,
+  0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20,
+  0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00,
+  0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0,
+  0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x00,
+  0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x6a, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x9a, 0x8d, 0x9c, 0xaa, 0xfc, 0x72, 0x63, 0x53, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x23, 0x20, 0x73, 0x61, 0x6d, 0x70, 0x6c, 0x65, 0x20, 0x72, 0x63, 0x53,
+  0x20, 0x66, 0x69, 0x6c, 0x65, 0x3b, 0x20, 0x79, 0x6f, 0x75, 0x20, 0x6d,
+  0x75, 0x73, 0x74, 0x20, 0x72, 0x75, 0x6e, 0x20, 0x74, 0x6f, 0x6f, 0x6c,
+  0x73, 0x2f, 0x67, 0x65, 0x6e, 0x72, 0x6f, 0x6d, 0x66, 0x73, 0x20, 0x3c,
+  0x6e, 0x75, 0x74, 0x74, 0x78, 0x20, 0x64, 0x69, 0x72, 0x3e, 0x20, 0x66,
+  0x72, 0x6f, 0x6d, 0x20, 0x77, 0x69, 0x74, 0x68, 0x69, 0x6e, 0x20, 0x74,
+  0x68, 0x69, 0x73, 0x0a, 0x23, 0x20, 0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69,
+  0x6f, 0x6e, 0x20, 0x74, 0x6f, 0x20, 0x63, 0x6f, 0x6e, 0x76, 0x65, 0x72,
+  0x74, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x20,
+  0x74, 0x6f, 0x20, 0x6e, 0x73, 0x68, 0x5f, 0x72, 0x6f, 0x6d, 0x66, 0x73,
+  0x69, 0x6d, 0x67, 0x2e, 0x68, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x69, 0x6e,
+  0x63, 0x6c, 0x75, 0x73, 0x69, 0x6f, 0x6e, 0x20, 0x69, 0x6e, 0x20, 0x74,
+  0x68, 0x65, 0x20, 0x62, 0x75, 0x69, 0x6c, 0x64, 0x0a, 0x0a, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+  0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0xe0, 0x2e, 0x2e, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00
+};
+unsigned int romfs_img_len = 1024;

configs/stm32l476vg-disco/include/rcS.template

@@ -0,0 +1,3 @@
+# sample rcS file; you must run tools/genromfs <nuttx dir> from within this
+# location to convert this file to nsh_romfsimg.h for inclusion in the build
+

configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h

@@ -51,9 +51,9 @@
 
 /* Clocking *************************************************************************/
 
-/* The stm32l476vg-disco supports both HSE and LSE crystals (X2 and X3).  However, as
+/* The stm32l476vg-disco supports both HSE and LSE crystals.  As shipped, the HSE
- * shipped, the HSE X2 crystal is not populated.  Therefore the stm32l476vg-disco
+ * crystal is not populated.  Therefore the stm32l476vg-disco will need to run off the
- * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
+ * 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
  */
 
 /* HSI - 16 MHz RC factory-trimmed
@@ -69,18 +69,27 @@
 
 #define BOARD_AHB_FREQUENCY       80000000ul
 
-/* XXX review the STM32L4_BOARD_USEHSI usage, it has too much influence in
+/* XXX there needs to be independent selections for the System Clock Mux and
- * stm32l4x6xx_rcc.c.  I suspect it is fine for it to turn on and off that
+ * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
- * ocillator, but really that's all it should do (e.g. it also controls
+ * Source Mux is chosen by the following define.  This is probably OK in many
- * input of teh PLLs.  Also, it should be fine/desireable to support things
+ * cases, but should be separated to support other power configurations.
- * like turning on both HSI and MSI, because they plausibly can both be
- * used at the same time; currently those choices HSE/HSI16/MSI are
- * mutually exclusive.
  */
 
+#if 0
+#  define HSI_CLOCK_CONFIG          /* HSI-16 clock configuration */
+#elif 0
+/* Make sure you actually installed one! */
+
+#  define HSE_CLOCK_CONFIG          /* HSE with 8 MHz xtal */
+#else
+#  define MSI_CLOCK_CONFIG          /* MSI @ 4 MHz autotrimmed via LSE */
+#endif
+
+#if defined(HSI_CLOCK_CONFIG)
+
 #define STM32L4_BOARD_USEHSI           1
 
-/* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
+/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
  as per comment above HSI) */
 
 #define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
@@ -136,7 +145,7 @@
 #define STM32L4_USE_CLK48         1
 #define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
 
-/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
+/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
 #define STM32L4_USE_LSE           1
 
@@ -178,6 +187,167 @@
  */
 /* REVISIT : this can be configured */
 
+#elif defined(HSE_CLOCK_CONFIG)
+
+/* Use the HSE */
+
+#define STM32L4_BOARD_USEHSE      1
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = hse */
+
+/* Prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(20)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(12)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* Enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* Enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* Configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* Configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#elif defined(MSI_CLOCK_CONFIG)
+
+/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
+
+#define STM32L4_BOARD_USEMSI      1
+#define STM32L4_BOARD_MSIRANGE    RCC_CR_MSIRANGE_4M
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = msi */
+
+/* Prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(40)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(24)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* Enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* Enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* Configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* Configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#endif
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/

configs/stm32l476vg-disco/nsh/defconfig

@@ -50,7 +50,7 @@ CONFIG_ARCH_HAVE_HEAPCHECK=y
 # Subsystem Debug Options
 #
 # CONFIG_DEBUG_BINFMT is not set
-CONFIG_DEBUG_FS=y
+# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_GRAPHICS is not set
 # CONFIG_DEBUG_LIB is not set
 # CONFIG_DEBUG_MM is not set
@@ -398,7 +398,8 @@ CONFIG_NSH_MMCSDMINOR=0
 #
 CONFIG_LIB_BOARDCTL=y
 # CONFIG_BOARDCTL_RESET is not set
-# CONFIG_BOARDCTL_UNIQUEID is not set
+CONFIG_BOARDCTL_UNIQUEID=y
+CONFIG_BOARDCTL_UNIQUEID_SIZE=12
 # CONFIG_BOARDCTL_TSCTEST is not set
 # CONFIG_BOARDCTL_ADCTEST is not set
 # CONFIG_BOARDCTL_PWMTEST is not set
@@ -542,7 +543,8 @@ CONFIG_SPI_EXCHANGE=y
 # CONFIG_TIMER is not set
 CONFIG_RTC=y
 CONFIG_RTC_DATETIME=y
-# CONFIG_RTC_ALARM is not set
+CONFIG_RTC_ALARM=y
+CONFIG_RTC_NALARMS=2
 CONFIG_RTC_DRIVER=y
 CONFIG_RTC_IOCTL=y
 # CONFIG_RTC_EXTERNAL is not set
@@ -696,16 +698,15 @@ CONFIG_FS_WRITABLE=y
 # CONFIG_FS_NAMED_SEMAPHORES is not set
 CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 # CONFIG_FS_RAMMAP is not set
-CONFIG_FS_FAT=y
+# CONFIG_FS_FAT is not set
-# CONFIG_FAT_LCNAMES is not set
-# CONFIG_FAT_LFN is not set
-# CONFIG_FS_FATTIME is not set
-# CONFIG_FAT_FORCE_INDIRECT is not set
-# CONFIG_FAT_DMAMEMORY is not set
-# CONFIG_FAT_DIRECT_RETRY is not set
 # CONFIG_FS_NXFFS is not set
-# CONFIG_FS_ROMFS is not set
+CONFIG_FS_ROMFS=y
-# CONFIG_FS_TMPFS is not set
+CONFIG_FS_TMPFS=y
+CONFIG_FS_TMPFS_BLOCKSIZE=512
+CONFIG_FS_TMPFS_DIRECTORY_ALLOCGUARD=64
+CONFIG_FS_TMPFS_DIRECTORY_FREEGUARD=128
+CONFIG_FS_TMPFS_FILE_ALLOCGUARD=512
+CONFIG_FS_TMPFS_FILE_FREEGUARD=1024
 # CONFIG_FS_SMARTFS is not set
 # CONFIG_FS_BINFS is not set
 CONFIG_FS_PROCFS=y
@@ -834,6 +835,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 #
 # Examples
 #
+CONFIG_EXAMPLES_ALARM=y
+CONFIG_EXAMPLES_ALARM_PRIORITY=100
+CONFIG_EXAMPLES_ALARM_STACKSIZE=2048
+CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0"
+CONFIG_EXAMPLES_ALARM_SIGNO=1
 CONFIG_EXAMPLES_BUTTONS=y
 CONFIG_EXAMPLES_BUTTONS_MIN=0
 CONFIG_EXAMPLES_BUTTONS_MAX=4
@@ -853,14 +859,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7"
 # CONFIG_EXAMPLES_CXXTEST is not set
 # CONFIG_EXAMPLES_DHCPD is not set
 # CONFIG_EXAMPLES_ELF is not set
-CONFIG_EXAMPLES_FSTEST=y
+# CONFIG_EXAMPLES_FSTEST is not set
-CONFIG_EXAMPLES_FSTEST_MAXNAME=32
-CONFIG_EXAMPLES_FSTEST_MAXFILE=8192
-CONFIG_EXAMPLES_FSTEST_MAXIO=347
-CONFIG_EXAMPLES_FSTEST_MAXOPEN=2
-CONFIG_EXAMPLES_FSTEST_MOUNTPT="/mnt/n25qxxx"
-CONFIG_EXAMPLES_FSTEST_NLOOPS=1
-# CONFIG_EXAMPLES_FSTEST_VERBOSE is not set
 # CONFIG_EXAMPLES_FTPC is not set
 # CONFIG_EXAMPLES_FTPD is not set
 # CONFIG_EXAMPLES_HELLO is not set
@@ -895,6 +894,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
 # CONFIG_EXAMPLES_RANDOM is not set
 # CONFIG_EXAMPLES_RGBLED is not set
 # CONFIG_EXAMPLES_RGMP is not set
+# CONFIG_EXAMPLES_ROMFS is not set
 # CONFIG_EXAMPLES_SENDMAIL is not set
 # CONFIG_EXAMPLES_SERIALBLASTER is not set
 # CONFIG_EXAMPLES_SERIALRX is not set
@@ -905,9 +905,11 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
 # CONFIG_EXAMPLES_SMP is not set
 # CONFIG_EXAMPLES_TCPECHO is not set
 # CONFIG_EXAMPLES_TELNETD is not set
+# CONFIG_EXAMPLES_THTTPD is not set
 # CONFIG_EXAMPLES_TIFF is not set
 # CONFIG_EXAMPLES_TOUCHSCREEN is not set
 # CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_UNIONFS is not set
 # CONFIG_EXAMPLES_USBSERIAL is not set
 # CONFIG_EXAMPLES_USBTERM is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
@@ -999,7 +1001,6 @@ CONFIG_NSH_DISABLE_LOSMART=y
 # CONFIG_NSH_DISABLE_LS is not set
 # CONFIG_NSH_DISABLE_MB is not set
 # CONFIG_NSH_DISABLE_MKDIR is not set
-# CONFIG_NSH_DISABLE_MKFATFS is not set
 # CONFIG_NSH_DISABLE_MKFIFO is not set
 # CONFIG_NSH_DISABLE_MKRD is not set
 # CONFIG_NSH_DISABLE_MH is not set
@@ -1038,6 +1039,15 @@ CONFIG_NSH_FILEIOSIZE=512
 # CONFIG_NSH_DISABLESCRIPT is not set
 # CONFIG_NSH_DISABLE_ITEF is not set
 # CONFIG_NSH_DISABLE_LOOPS is not set
+CONFIG_NSH_ROMFSETC=y
+# CONFIG_NSH_ROMFSRC is not set
+CONFIG_NSH_ROMFSMOUNTPT="/etc"
+CONFIG_NSH_INITSCRIPT="init.d/rcS"
+CONFIG_NSH_ROMFSDEVNO=0
+CONFIG_NSH_ROMFSSECTSIZE=64
+# CONFIG_NSH_DEFAULTROMFS is not set
+CONFIG_NSH_ARCHROMFS=y
+# CONFIG_NSH_CUSTOMROMFS is not set
 
 #
 # Console Configuration

configs/stm32l476vg-disco/src/stm32_appinit.c

@@ -53,6 +53,7 @@
 
 #include <stm32l4.h>
 #include <stm32l4_uart.h>
+#include <stm32l4_uid.h>
 
 #include <arch/board/board.h>
 #include <arch/board/boardctl.h>
@@ -308,3 +309,16 @@ int board_ioctl(unsigned int cmd, uintptr_t arg)
     return OK;
 }
 #endif
+
+#if defined(CONFIG_BOARDCTL_UNIQUEID)
+int board_uniqueid(uint8_t *uniqueid)
+{
+  if (uniqueid == 0)
+    {
+      return -EINVAL;
+    }
+
+  stm32l4_get_uniqueid(uniqueid);
+  return OK;
+}
+#endif

crypto/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # crypto/Makefile
 #
-#   Copyright (C) 2007, 2008, 2011-2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007, 2008, 2011-2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -70,6 +70,7 @@ OBJS = $(AOBJS) $(COBJS)
 BIN = libcrypto$(LIBEXT)
 
 all: $(BIN)
+.PHONY: depend clean distclean
 
 $(AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)

drivers/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # drivers/Makefile
 #
-#   Copyright (C) 2007-2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007-2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -108,6 +108,7 @@ OBJS = $(AOBJS) $(COBJS)
 BIN = libdrivers$(LIBEXT)
 
 all: $(BIN)
+.PHONY: depend clean distclean
 
 $(AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)

drivers/can.c

@@ -522,6 +522,44 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
       /* Interrupts must be disabled while accessing the cd_recv FIFO */
 
       flags = enter_critical_section();
+
+#ifdef CONFIG_CAN_ERRORS
+      /* Check for internal errors */
+
+      if (dev->cd_error != 0)
+        {
+          FAR struct can_msg_s *msg;
+
+          /* Detected an internal driver error.  Generate a
+           * CAN_ERROR_MESSAGE
+           */
+
+          if (buflen < CAN_MSGLEN(CAN_ERROR_DLC))
+            {
+              goto return_with_irqdisabled;
+            }
+
+          msg                   = (FAR struct can_msg_s *)buffer;
+          msg->cm_hdr.ch_id     = CAN_ERROR_INTERNAL;
+          msg->cm_hdr.ch_dlc    = CAN_ERROR_DLC;
+          msg->cm_hdr.ch_rtr    = 0;
+          msg->cm_hdr.ch_error  = 1;
+#ifdef CONFIG_CAN_EXTID
+          msg->cm_hdr.ch_extid  = 0;
+#endif
+          msg->cm_hdr.ch_unused = 0;
+          memset(&(msg->cm_data), 0, CAN_ERROR_DLC);
+          msg->cm_data[5]       = dev->cd_error;
+
+          /* Reset the error flag */
+
+          dev->cd_error         = 0;
+
+          ret = CAN_MSGLEN(CAN_ERROR_DLC);
+          goto return_with_irqdisabled;
+        }
+#endif /* CONFIG_CAN_ERRORS */
+
       while (dev->cd_recv.rx_head == dev->cd_recv.rx_tail)
         {
           /* The receive FIFO is empty -- was non-blocking mode selected? */
@@ -540,6 +578,7 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
               ret = sem_wait(&dev->cd_recv.rx_sem);
             }
           while (ret >= 0 && dev->cd_recv.rx_head == dev->cd_recv.rx_tail);
+
           dev->cd_nrxwaiters--;
 
           if (ret < 0)
@@ -927,6 +966,9 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev)
   dev->cd_ntxwaiters = 0;
   dev->cd_nrxwaiters = 0;
   dev->cd_npendrtr   = 0;
+#ifdef CONFIG_CAN_ERRORS
+  dev->cd_error      = 0;
+#endif
 
   sem_init(&dev->cd_xmit.tx_sem, 0, 0);
   sem_init(&dev->cd_recv.rx_sem, 0, 0);
@@ -1073,6 +1115,14 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
 
       err = OK;
     }
+#ifdef CONFIG_CAN_ERRORS
+  else
+    {
+      /* Report rx overflow error */
+
+      dev->cd_error |= CAN_ERROR5_RXOVERFLOW;
+    }
+#endif
 
   return err;
 }

drivers/leds/userled_upper.c

@@ -63,10 +63,10 @@
 
 #ifndef CONFIG_DEBUG
 #  undef CONFIG_DEBUG_VERBOSE
-#  undef CONFIG_DEBUG_DISCRETE
+#  undef CONFIG_DEBUG_LEDS
 #endif
 
-#ifdef CONFIG_DEBUG_DISCRETE
+#ifdef CONFIG_DEBUG_LEDS
 #  define ddbg lldbg
 #  ifdef CONFIG_DEBUG_VERBOSE
 #    define dvdbg lldbg

drivers/mtd/Kconfig

@@ -783,6 +783,39 @@ config SST25XX_MEMORY_TYPE
 
 endif # MTD_SST25XX
 
+config MTD_SST26
+	bool "SPI/QSPI-based SST26XX FLASHes (16,32,64-MBit)"
+	default n
+	select SPI
+	---help---
+		These part are also different from SST25 and SST25XX, they support both SPI and QSPI.
+
+if MTD_SST26
+
+config SST26_SPIMODE
+	int "SST26 (Q)SPI Mode"
+	default 0
+
+config SST26_SPIFREQUENCY
+	int "SST26 (Q)SPI Frequency"
+	default 64000000
+
+config SST26_MANUFACTURER
+	hex "Manufacturers ID"
+	default 0xBF
+	---help---
+		Various manufacturers may have produced the parts.  0xBF is the manufacturer ID
+		for the parts manufactured by SST.
+
+config SST26_MEMORY_TYPE
+	hex "Memory type ID"
+	default 0x26
+	---help---
+		The memory type for SST26VF0xx series is 0x26, but this can be modified if needed
+		to support compatible devices from different manufacturers.
+
+endif # MTD_SST26
+
 config MTD_SST39FV
 	bool "SST39FV NOR FLASH"
 	default n

drivers/mtd/Make.defs

@@ -88,6 +88,10 @@ ifeq ($(CONFIG_MTD_SST25XX),y)
 CSRCS += sst25xx.c
 endif
 
+ifeq ($(CONFIG_MTD_SST26),y)
+CSRCS += sst26.c
+endif
+
 ifeq ($(CONFIG_MTD_SST39FV),y)
 CSRCS += sst39vf.c
 endif

drivers/serial/uart_16550.c

@@ -520,6 +520,7 @@ static inline void u16550_restoreuartint(FAR struct u16550_s *priv, uint32_t ier
 static inline void u16550_enablebreaks(FAR struct u16550_s *priv, bool enable)
 {
   uint32_t lcr = u16550_serialin(priv, UART_LCR_OFFSET);
+
   if (enable)
     {
       lcr |= UART_LCR_BRK;
@@ -528,6 +529,7 @@ static inline void u16550_enablebreaks(FAR struct u16550_s *priv, bool enable)
     {
       lcr &= ~UART_LCR_BRK;
     }
+
   u16550_serialout(priv, UART_LCR_OFFSET, lcr);
 }
 

fs/Kconfig

@@ -43,10 +43,21 @@ config DISABLE_PSEUDOFS_OPERATIONS
 config FS_READABLE
 	bool
 	default n
+	---help---
+		Automatically selected if any readable file system is selected
 
 config FS_WRITABLE
-	bool
+	bool "Writable file system"
 	default n
+	---help---
+		Automatically selected if any writable file system is selected.  If
+		not selected, support for writing will be disabled in all block
+		drivers and also the block-to-character (BCH) layer and the MTD FTL
+		layer.
+
+		This selection can also be manually selected.  You might want to do
+		this if there are no writable file systems enabled, but you still
+		want support for write access in block drivers and/or FTL.
 
 source fs/aio/Kconfig
 source fs/semaphore/Kconfig

fs/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # fs/Makefile
 #
-#   Copyright (C) 2007, 2008, 2011-2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2007, 2008, 2011-2014, 2016 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -84,6 +84,7 @@ OBJS = $(AOBJS) $(COBJS)
 BIN = libfs$(LIBEXT)
 
 all: $(BIN)
+.PHONY: depend clean distclean
 
 $(AOBJS): %$(OBJEXT): %.S
 	$(call ASSEMBLE, $<, $@)

fs/mount/fs_mount.c

@@ -103,9 +103,6 @@ extern const struct mountpt_operations fat_operations;
 #ifdef CONFIG_FS_ROMFS
 extern const struct mountpt_operations romfs_operations;
 #endif
-#ifdef CONFIG_FS_TMPFS
-extern const struct mountpt_operations tmpfs_operations;
-#endif
 #ifdef CONFIG_FS_SMARTFS
 extern const struct mountpt_operations smartfs_operations;
 #endif
@@ -129,6 +126,9 @@ static const struct fsmap_t g_bdfsmap[] =
 #ifdef CONFIG_FS_NXFFS
 extern const struct mountpt_operations nxffs_operations;
 #endif
+#ifdef CONFIG_FS_TMPFS
+extern const struct mountpt_operations tmpfs_operations;
+#endif
 #ifdef CONFIG_NFS
 extern const struct mountpt_operations nfs_operations;
 #endif
@@ -298,7 +298,7 @@ int mount(FAR const char *source, FAR const char *target,
        * incremented.
        */
 
-      DEBUGASSERT(mountpt_inode->u.i_mops == NULL);
+      DEBUGASSERT(mountpt_inode->u.i_mops != NULL);
     }
   else
 #endif

include/nuttx/can.h

@@ -219,7 +219,8 @@
 #  define CAN_ERROR_BUSOFF        (1 << 6) /* Bit 6: Bus off */
 #  define CAN_ERROR_BUSERROR      (1 << 7) /* Bit 7: Bus error */
 #  define CAN_ERROR_RESTARTED     (1 << 8) /* Bit 8: Controller restarted */
-                                           /* Bits 9-10: Available */
+#  define CAN_ERROR_INTERNAL      (1 << 9) /* Bit 9: Stack internal error (See CAN_ERROR5_* definitions) */
+                                           /* Bit 10: Available */
 
 /* The remaining definitions described the error report payload that follows the
  * CAN header.
@@ -295,6 +296,11 @@
 #  define CANL_ERROR4_SHORT2GND   0x40
 #  define CANL_ERROR4_SHORT2CANH  0x50
 
+/* Data[5]: Error status of stack internals */
+
+#  define CAN_ERROR5_UNSPEC       0x00     /* Unspecified error */
+#  define CAN_ERROR5_RXOVERFLOW   (1 << 0) /* Bit 0: RX buffer overflow */
+
 #endif /* CONFIG_CAN_ERRORS */
 
 /* CAN filter support ***************************************************************/
@@ -494,6 +500,9 @@ struct can_dev_s
   uint8_t              cd_npendrtr;      /* Number of pending RTR messages */
   volatile uint8_t     cd_ntxwaiters;    /* Number of threads waiting to enqueue a message */
   volatile uint8_t     cd_nrxwaiters;    /* Number of threads waiting to receive a message */
+#ifdef CONFIG_CAN_ERRORS
+  uint8_t              cd_error;         /* Flags to indicate internal device errors */
+#endif
   sem_t                cd_closesem;      /* Locks out new opens while close is in progress */
   struct can_txfifo_s  cd_xmit;          /* Describes transmit FIFO */
   struct can_rxfifo_s  cd_recv;          /* Describes receive FIFO */

include/nuttx/mtd/mtd.h

@@ -476,6 +476,18 @@ FAR struct mtd_dev_s *sst25_initialize(FAR struct spi_dev_s *dev);
 
 FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev);
 
+/****************************************************************************
+ * Name: sst26_initialize_spi
+ *
+ * Description:
+ *   Initializes the driver for SPI-based SST26 FLASH
+ *
+ *   Supports SST26VF016 SST26VF032 SST26VF064
+ *
+ ****************************************************************************/
+
+FAR struct mtd_dev_s *sst26_initialize_spi(FAR struct spi_dev_s *dev);
+
 /****************************************************************************
  * Name: sst39vf_initialize
  *