diff --git a/ChangeLog b/ChangeLog index faa17d5bbf1..455ccb8c46c 100755 --- a/ChangeLog +++ b/ChangeLog @@ -10401,7 +10401,7 @@ * arch/arm/src/efm32/efm32_rtc_burtc.c: Updated EFM32 RTC driver from Pierre-noel Bouteville (2015-05-19). * arch/arm/src/tiva/chip/tm4c_memorymap.h, tm4c_pinmap.h, and vectors.h. - configs/tm4c1294-launchpad/include/board.h and src/tm4c_autoleds.c: + configs/tm4c1294-launchpad/include/board.h and src/tm4c_autoleds.c: Fixes for Tiva TM4C1294NCPDT. From Frank Sautter. (2015-05-20). * configs/tm4c1294-launchpad/include/board.h: Added TM4C1294NCPDT EN0_LED2 (10/100-Base-Tx); removed all booster pack pin definitions. @@ -11625,13 +11625,13 @@ * configs/nucleus2g: Removed the Nucleus2G configuration. There has not been any activity with the commercial board in a few years and it no longer appears to be available from the 2g-eng.com website. - Since the board is commercial and no longer publically available, it + Since the board is commercial and no longer publicly available, it no longer qualifies for inclusion in the open source repositories. The code as of this data is still available in the Obsoleted repository at configs/nucleus2g (2016-04-12). * arch/arm/src/stm32l4: Fix the STM32L4 SPI driver. That SPI driver is quite different. They now handle frames of arbitrary size between 4 - and 16 bits. It was broken before a new bit has to be set (rx fifo + and 16 bits. It was broken before a new bit has to be set (RX fifo threshold) to handle <= 8-bit transactions. If not set, the default is 16-bit packed >=8-bit frames and the RXNE bit is never set (it is set when 16-bits are received). weird things as always. @@ -11662,7 +11662,7 @@ * configs/stm32l476vb-disco: Add support for QSPI based N25Qxxx flash. From Dave dev@ziggurat29.com (2016-04-18). * graphics/vnc: Add support for a VNC server. This logic is code - complete, but untested and so not ready for primetime (2016-04-18). + complete, but untested and so not ready for prime time (2016-04-18). * configs/samv71-xult/vnc: Add a configuration that will be used to verify VNC (also untested) (2016-04-18). * drivers/ioexpander: Fix an error in the PCA9555 driver: Under certain @@ -11670,8 +11670,51 @@ Lorquet (2016-04-20). * arch/arm/src/stm32 and configs/stm32f429i-disco: Correct some bad commits that broke the LTDC display example. From Marco Krahl - (2016-04-22). - * configs/samv71-xult/vnwwm: Add a more complex NxWM configuration + (2016-04-22). + * configs/samv71-xult/vncwwm: Add a more complex NxWM configuration to support further VNC testing (particularly of VNC keyboard and - mouse intputs). Initial configuration is not functional (2016-04-23). - + mouse inputs). Initial configuration is not functional (2016-04-23). + * arch/arm/src/stm32l4: Add support for QSPI DMA. From Dave + dev@ziggurat29.com (2016-04-24). + * configs/stm32l476vg-disco: Update stm32l4 disco board to reflect QSPI + DMA support. From Dave dev@ziggurat29.com (2016-04-24). + * arch/arm/src/stm32l4: Add configuration options to allow SRAM2 to be + used for heap, or not at all, and to zero-initialize it on OS start, + or not at all. From Dave dev@ziggurat29.com (2016-04-24). + * drivers/mtd/smart.c: Return code of smart_scan not checked, can + cause success result in failure case, leading to 'dev' pointer being + invalid. From Dave dev@ziggurat29.com (2016-04-27). + * arch/arm/src/stm32l4: Add support for QSPI memory mapped mode. From + Dave dev@ziggurat29.com (2016-04-27). + * configs/stm32l476vg-disco: Add board ioctls for allowing user + application to cause QSPI memory mapped mode to be engaged and + disengaged. Also partitioned QSPI flash for file system and other + (eventually xip). From Dave dev@ziggurat29.com (2016-04-27). + * fs/mount: Fix a backward debug assertion. Noted by David Sidrane + (2016-04-29). + * arch/arm/src/stm32l4: Add support for HSE and MSI clocks, and auto + trim of MSI to LSE (needed for USB). From Dave dev@ziggurat29.com + (2016-04-29). + * arch/arm/src/stm32l4: Add support for unique id function to arch; + modified board to support unique id boardctl. From Dave + dev@ziggurat29.com (2016-05-03). + * Makefile.unix and tools/mkexport.sh: Pass top-level make to the + script to allow -j greater than 1. From David Sidrane (2016-05-04). + * arch/arm/src/stm32, stm32f7, stm32l4: Fix typo in variable name in + serial BREAK logic. Review other serial implementations for similar + naming problems. (2016-05-05). + * arch/arm/src/samv7: Fix typo in MATRIX register definitions. From + Stefan Kolb (2016-05-06). + * arch/arm/src/stm32l4: Problem with resetting backup domain clears + clocking options set up before in *rcc.c use INITS flag to avoid magic + reg value to detect power up reset state of RTC correct a problem + clearing interrupt flags (they weren't) which prevented an alarm from + ever being used more than once per reset cycle. From Dave + dev@ziggurat29.com (2016-05-07). + * arch/arm/src/tiva: Fix a bug of GPIO falling-edge interrupt for tiva. + From Young (2016-05-07). + * drivrs/mtd: Add a driver for SST26F spi/qspi flash devices (SPI mode + only). From Sebastien Lorquet (2016-05-10). + * Several Makefiles: Add .PHONY definitions to prevent 'clean up to date' + message weirdness when 'make clean' is done with no .config or Make.defs + file (2016-05-10). diff --git a/Kconfig b/Kconfig index 11e734ab2ac..17d6e351f9e 100644 --- a/Kconfig +++ b/Kconfig @@ -574,16 +574,6 @@ config DEBUG_INPUT this debug option is board-specific and may not be available for some boards. -config DEBUG_DISCRETE - bool "Discrete I/O Debug Output" - default n - depends on DISCRETE_IO - ---help--- - Enable low level debug SYSLOG output from the discrete I/O device - drivers such as LEDs and I/O expanders (disabled by default). - Support for this debug option is board-specific and may not be - available for some boards. - config DEBUG_ANALOG bool "Analog Device Debug Output" default n diff --git a/Makefile.unix b/Makefile.unix index 96179c419bc..022c7962169 100644 --- a/Makefile.unix +++ b/Makefile.unix @@ -507,7 +507,7 @@ gconfig: apps_preconfig # that the archiver is 'ar' export: pass2deps - $(Q) $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)" + $(Q) MAKE=${MAKE} $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)" # General housekeeping targets: dependencies, cleaning, etc. # diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index dcceafb28a2..19e5c9d7bdf 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -268,6 +268,7 @@ static inline void up_waittxready(struct up_dev_s *priv) static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { uint16_t lcr = up_serialin(priv, UART_LCR); + if (enable) { lcr |= UART_LCR_BOC; @@ -276,6 +277,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { lcr &= ~UART_LCR_BOC; } + up_serialout(priv, UART_LCR, lcr); } diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index 041f9b8c059..62b18ecfe35 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -272,6 +272,7 @@ static inline void up_waittxready(struct up_dev_s *priv) static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { uint8_t lcr = up_serialin(priv, LPC214X_UART_LCR_OFFSET); + if (enable) { lcr |= LPC214X_LCR_BREAK_ENABLE; @@ -280,6 +281,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { lcr &= ~LPC214X_LCR_BREAK_ENABLE; } + up_serialout(priv, LPC214X_UART_LCR_OFFSET, lcr); } diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 389d713284b..9650a0827a3 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -290,6 +290,7 @@ static inline void up_waittxready(struct up_dev_s *priv) static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { uint8_t lcr = up_serialin(priv, UART_LCR_OFFSET); + if (enable) { lcr |= LCR_BREAK_ENABLE; @@ -298,6 +299,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { lcr &= ~LCR_BREAK_ENABLE; } + up_serialout(priv, UART_LCR_OFFSET, lcr); } diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 0dda586af1b..c12d65597b1 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -551,6 +551,7 @@ static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier) static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { uint32_t lcr = up_serialin(priv, LPC43_UART_LCR_OFFSET); + if (enable) { lcr |= UART_LCR_BRK; @@ -559,6 +560,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) { lcr &= ~UART_LCR_BRK; } + up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr); } diff --git a/arch/arm/src/samv7/chip/sam_matrix.h b/arch/arm/src/samv7/chip/sam_matrix.h index e399ef3cc12..2de2cd538c6 100644 --- a/arch/arm/src/samv7/chip/sam_matrix.h +++ b/arch/arm/src/samv7/chip/sam_matrix.h @@ -101,7 +101,7 @@ /* 0x006c8-0x00fc: Reserved */ #define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ /* 0x0104-0x010c: Reserved */ -#define SAM_MATRIX_CAN0_OFFSET 0x0100 /* Master Remap Control Register */ +#define SAM_MATRIX_CAN0_OFFSET 0x0110 /* CAN0 Configuration Register */ #define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */ /* 0x0118-0x0120: Reserved */ #define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x0124 /* SMC Chip Select NAND Flash Assignment Register */ diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 2e11d526094..73039dcf6db 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -2060,8 +2060,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_USART_BREAKS case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { - irqstate_t flags = enter_critical_section(); - uint32_t cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); + uint32_t cr2; + irqstate_t flags; + + flags = enter_critical_section(); + cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN); leave_critical_section(flags); } @@ -2069,9 +2072,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ { + uint32_t cr2; irqstate_t flags; + flags = enter_critical_section(); - uint32_t cr1 = up_serialin(priv, STM32_USART_CR2_OFFSET); + cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN); leave_critical_section(flags); } diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index d62b78fd6ed..78810f52f36 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -1967,8 +1967,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_USART_BREAKS case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { - irqstate_t flags = enter_critical_section(); - uint32_t cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); + uint32_t cr2; + irqstate_t flags; + + flags = enter_critical_section(); + cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN); leave_critical_section(flags); } @@ -1976,9 +1979,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ { + uint32_t cr2; irqstate_t flags; + flags = enter_critical_section(); - uint32_t cr1 = up_serialin(priv, STM32_USART_CR2_OFFSET); + cr2 = up_serialin(priv, STM32_USART_CR2_OFFSET); up_serialout(priv, STM32_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN); leave_critical_section(flags); } diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index d9f3fb8341a..561cfedf283 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -114,7 +114,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c -CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c +CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c ifneq ($(CONFIG_SCHED_TICKLESS),y) diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h index 134ee2844cd..0b184230b4b 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h @@ -120,8 +120,8 @@ /* Clock control register */ -#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Medium Speed clock enable */ -#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Medium Speed clock ready flag */ +#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Multi Speed clock enable */ +#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Multi Speed clock ready flag */ #define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */ #define RCC_CR_MSIRGSEL (1 << 3) /* Bit 2: MSI clock range selection */ #define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */ @@ -161,9 +161,9 @@ #define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) #define RCC_CR_HSICAL_SHIFT (16) /* Bits 23-16: Internal High Speed clock Calibration */ #define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT) -#define RCC_CR_MSITRIM_SHIFT (8) /* Bits 15-8: Internal Medium Speed clock trimming */ +#define RCC_CR_MSITRIM_SHIFT (8) /* Bits 15-8: Internal Multi Speed clock trimming */ #define RCC_CR_MSITRIM_MASK (0xff << RCC_CR_MSITRIM_SHIFT) -#define RCC_CR_MSICAL_SHIFT (0) /* Bits 7-0: Internal Menium Speed clock Calibration */ +#define RCC_CR_MSICAL_SHIFT (0) /* Bits 7-0: Internal Multi Speed clock Calibration */ #define RCC_CR_MSICAL_MASK (0xff << RCC_CR_MSICAL_SHIFT) /* Clock configuration register */ diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 9e37373adfe..d5ac105436c 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -104,13 +104,13 @@ #define SRAM2_START 0x10000000 #define SRAM2_END 0x10008000 -#if defined(STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) +#if defined(CONFIG_STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) # if CONFIG_MM_REGIONS < 3 # error you need at least 3 memory manager regions to support SRAM2 and FSMC # endif #endif -#if defined(STM32L4_SRAM2_HEAP) || defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) +#if defined(CONFIG_STM32L4_SRAM2_HEAP) || defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) # if CONFIG_MM_REGIONS < 2 # error you need at least 2 memory manager regions to support SRAM2 or FSMC # endif diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index 8f145ccd4fd..c71d9752837 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -54,10 +54,6 @@ #include "stm32l4_gpio.h" #include "stm32l4_exti.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ @@ -66,10 +62,6 @@ static xcpt_t stm32l4_exti_callback; -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -86,17 +78,17 @@ static int stm32l4_exti_alarm_isr(int irq, void *context) { int ret = OK; - /* Clear the pending EXTI interrupt */ - - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); - - /* And dispatch the interrupt to the handler */ + /* Dispatch the interrupt to the handler */ if (stm32l4_exti_callback) { ret = stm32l4_exti_callback(irq, context); } + /* Clear the pending EXTI interrupt */ + + putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + return ret; } diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 5292f6f4eb9..b155bef8b0b 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -43,6 +43,7 @@ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H +#include #include #include "chip.h" @@ -62,9 +63,30 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_RTC_ALARM + /* The form of an alarm callback */ -typedef CODE void (*alarmcb_t)(void); +typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid); + +enum alm_id_e +{ + RTC_ALARMA = 0, /* RTC ALARM A */ + RTC_ALARMB, /* RTC ALARM B */ + RTC_ALARM_LAST +}; + +/* Structure used to pass parmaters to set an alarm */ + +struct alm_setalarm_s +{ + int as_id; /* enum alm_id_e */ + struct tm as_time; /* Alarm expiration time */ + alm_callback_t as_cb; /* Callback (if non-NULL) */ + FAR void *as_arg; /* Argument for callback */ +}; + +#endif /* CONFIG_RTC_ALARM */ /**************************************************************************** * Public Data @@ -93,8 +115,7 @@ extern "C" * during initialization to set up the system time when CONFIG_RTC and * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. - * That sub-second accuracy is returned through 'nsec'. + * NOTE: The sub-second accuracy is returned through 'nsec'. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -130,43 +151,39 @@ struct tm; int stm32l4_rtc_setdatetime(FAR const struct tm *tp); #endif +#ifdef CONFIG_RTC_ALARM /**************************************************************************** * Name: stm32l4_rtc_setalarm * * Description: - * Set up an alarm. + * Set an alarm to an asbolute time using associated hardware. * * Input Parameters: - * tp - the time to set the alarm - * callback - the function to call when the alarm expires. + * alminfo - Information about the alarm configuration. * * Returned Value: * Zero (OK) on success; a negated errno on failure * ****************************************************************************/ -#ifdef CONFIG_RTC_ALARM -struct timespec; -int stm32l4_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); -#endif +int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo); /**************************************************************************** * Name: stm32l4_rtc_cancelalarm * * Description: - * Cancel a pending alarm alarm + * Cancel an alaram. * * Input Parameters: - * none + * alarmid - Identifies the alarm to be cancelled * * Returned Value: * Zero (OK) on success; a negated errno on failure * ****************************************************************************/ -#ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_cancelalarm(void); -#endif +int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); +#endif /* CONFIG_RTC_ALARM */ /**************************************************************************** * Name: stm32l4_rtc_lowerhalf diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index 033a191e411..558aa2533be 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -34,8 +34,6 @@ * ****************************************************************************/ -/* REVISIT: This driver is *not* thread-safe! */ - /**************************************************************************** * Included Files ****************************************************************************/ @@ -44,6 +42,7 @@ #include #include +#include #include #include @@ -54,10 +53,25 @@ #ifdef CONFIG_RTC_DRIVER +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_NALARMS 2 + /**************************************************************************** * Private Types ****************************************************************************/ +#ifdef CONFIG_RTC_ALARM +struct stm32l4_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile FAR void *priv; /* Private argurment to accompany callback */ + uint8_t id; /* Identifies the alarm */ +}; +#endif + /* This is the private type for the RTC state. It must be cast compatible * with struct rtc_lowerhalf_s. */ @@ -73,11 +87,20 @@ struct stm32l4_lowerhalf_s /* Data following is private to this driver and not visible outside of * this file. */ + + sem_t devsem; /* Threads can only exclusively access the RTC */ + +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS]; +#endif }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Prototypes for static methods in struct rtc_ops_s */ static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower, @@ -85,6 +108,15 @@ static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower, static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower, FAR const struct rtc_time *rtctime); +#ifdef CONFIG_RTC_ALARM +static int stm32l4_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo); +static int stm32l4_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); +static int stm32l4_cancelalarm(FAR struct rtc_lowerhalf_s *lower, + int alarmid); +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -96,9 +128,9 @@ static const struct rtc_ops_s g_rtc_ops = .rdtime = stm32l4_rdtime, .settime = stm32l4_settime, #ifdef CONFIG_RTC_ALARM - .setalarm = NULL, - .setrelative = NULL, - .cancelalarm = NULL, + .setalarm = stm32l4_setalarm, + .setrelative = stm32l4_setrelative, + .cancelalarm = stm32l4_cancelalarm, #endif #ifdef CONFIG_RTC_IOCTL .ioctl = NULL, @@ -120,7 +152,55 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rdtime + * Name: stm32l4_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static void stm32l4_alarm_callback(FAR void *arg, unsigned int alarmid) +{ + FAR struct stm32l4_lowerhalf_s *lower; + FAR struct stm32l4_cbinfo_s *cbinfo; + rtc_alarm_callback_t cb; + FAR void *priv; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); + + lower = (struct stm32l4_lowerhalf_s *)arg; + cbinfo = &lower->cbinfo[alarmid]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + cb = (rtc_alarm_callback_t)cbinfo->cb; + priv = (FAR void *)cbinfo->priv; + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, alarmid); + } +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -138,11 +218,25 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower, FAR struct rtc_time *rtctime) { + FAR struct stm32l4_lowerhalf_s *priv; + int ret; + + priv = (FAR struct stm32l4_lowerhalf_s *)lower; + + if (sem_wait(&priv->devsem) != OK) + { + return -errno; + } + /* This operation depends on the fact that struct rtc_time is cast * compatible with struct tm. */ - return up_rtc_getdatetime((FAR struct tm *)rtctime); + ret = up_rtc_getdatetime((FAR struct tm *)rtctime); + + sem_post(&priv->devsem); + + return ret; } /**************************************************************************** @@ -164,13 +258,223 @@ static int stm32l4_rdtime(FAR struct rtc_lowerhalf_s *lower, static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower, FAR const struct rtc_time *rtctime) { - /* This operation depends on the fact that struct rtc_time is cast + FAR struct stm32l4_lowerhalf_s *priv; + int ret; + + priv = (FAR struct stm32l4_lowerhalf_s *)lower; + + if (sem_wait(&priv->devsem) != OK) + { + return -errno; + } + + /* This operation depends on the fact that struct rtc_time is cast * compatible with struct tm. */ - return stm32l4_rtc_setdatetime((FAR const struct tm *)rtctime); + ret = stm32l4_rtc_setdatetime((FAR const struct tm *)rtctime); + + sem_post(&priv->devsem); + + return ret; } +/**************************************************************************** + * Name: stm32l4_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32l4_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo) +{ + FAR struct stm32l4_lowerhalf_s *priv; + FAR struct stm32l4_cbinfo_s *cbinfo; + struct alm_setalarm_s lowerinfo; + int ret = -EINVAL; + + /* ID0-> Alarm A; ID1 -> Alarm B */ + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + priv = (FAR struct stm32l4_lowerhalf_s *)lower; + + if (sem_wait(&priv->devsem) != OK) + { + return -errno; + } + + if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) + { + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[alarminfo->id]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + cbinfo->id = alarminfo->id; + + /* Set the alarm */ + + lowerinfo.as_id = alarminfo->id; + lowerinfo.as_cb = stm32l4_alarm_callback; + lowerinfo.as_arg = priv; + memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); + + /* And set the alarm */ + + ret = stm32l4_rtc_setalarm(&lowerinfo); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + } + + sem_post(&priv->devsem); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32l4_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32l4_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo) +{ + struct lower_setalarm_s setalarm; + struct tm time; + time_t seconds; + int ret = -EINVAL; + + ASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + + if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) && + alarminfo->reltime > 0) + { + /* Disable pre-emption while we do this so that we don't have to worry + * about being suspended and working on an old time. + */ + + sched_lock(); + + /* Get the current time in broken out format */ + + ret = up_rtc_getdatetime(&time); + if (ret >= 0) + { + /* Convert to seconds since the epoch */ + + seconds = mktime(&time); + + /* Add the seconds offset. Add one to the number of seconds + * because we are unsure of the phase of the timer. + */ + + seconds += (alarminfo->reltime + 1); + + /* And convert the time back to broken out format */ + + (void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + + ret = stm32l4_setalarm(lower, &setalarm); + } + + sched_unlock(); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32l4_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32l4_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid) +{ + FAR struct stm32l4_lowerhalf_s *priv; + FAR struct stm32l4_cbinfo_s *cbinfo; + int ret = -EINVAL; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); + priv = (FAR struct stm32l4_lowerhalf_s *)lower; + + if (sem_wait(&priv->devsem) != OK) + { + return -errno; + } + + /* ID0-> Alarm A; ID1 -> Alarm B */ + + if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB) + { + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[alarmid]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + ret = stm32l4_rtc_cancelalarm((enum alm_id_e)alarmid); + } + + sem_post(&priv->devsem); + + return ret; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -199,6 +503,8 @@ static int stm32l4_settime(FAR struct rtc_lowerhalf_s *lower, FAR struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void) { + sem_init(&g_rtc_lowerhalf.devsem, 0, 1); + return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32l4/stm32l4_rtcc.c b/arch/arm/src/stm32l4/stm32l4_rtcc.c index 1b7bb5f12ad..eab4fa45e81 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtcc.c @@ -42,6 +42,7 @@ #include "chip.h" #include +#include #include #include #include @@ -65,7 +66,10 @@ ************************************************************************************/ /* Configuration ********************************************************************/ -/* This RTC implementation supports only date/time RTC hardware */ +/* This RTC implementation supports + * - date/time RTC hardware + * - extended functions Alarm A and B + * */ #ifndef CONFIG_RTC_DATETIME # error "CONFIG_RTC_DATETIME must be set to use this driver" @@ -95,8 +99,22 @@ #define SYNCHRO_TIMEOUT (0x00020000) #define INITMODE_TIMEOUT (0x00010000) -#define RTC_MAGIC CONFIG_RTC_MAGIC -#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_RTC_MAGIC_REG) + +/* BCD conversions */ + +#define rtc_reg_tr_bin2bcd(tp) \ + ((rtc_bin2bcd((tp)->tm_sec) << RTC_TR_SU_SHIFT) | \ + (rtc_bin2bcd((tp)->tm_min) << RTC_TR_MNU_SHIFT) | \ + (rtc_bin2bcd((tp)->tm_hour) << RTC_TR_HU_SHIFT)) + +#define rtc_reg_alrmr_bin2bcd(tm) \ + ((rtc_bin2bcd((tm)->tm_sec) << RTC_ALRMR_SU_SHIFT) | \ + (rtc_bin2bcd((tm)->tm_min) << RTC_ALRMR_MNU_SHIFT) | \ + (rtc_bin2bcd((tm)->tm_hour) << RTC_ALRMR_HU_SHIFT)) + +/* Need to ignore DATE/DOW part of alarm; rtc_reg_alrmr_bin2bcd only encodes hms */ + +#define RTC_ALRMR_ENABLE (0x80000000) /* Debug ****************************************************************************/ @@ -112,14 +130,28 @@ # define rtcllvdbg(x...) #endif +/************************************************************************************ + * Private Types + ************************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +typedef unsigned int rtc_alarmreg_t; + +struct alm_cbinfo_s +{ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile FAR void *ac_arg; /* Argument to pass with the callback function */ +}; +#endif + /************************************************************************************ * Private Data ************************************************************************************/ -/* Callback to use when the alarm expires */ - #ifdef CONFIG_RTC_ALARM -static alarmcb_t g_alarmcb; +/* Callback to use when an EXTI is activated */ + +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; #endif /************************************************************************************ @@ -130,6 +162,17 @@ static alarmcb_t g_alarmcb; volatile bool g_rtc_enabled = false; +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void); +static int rtchw_check_alrbwf(void); +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg); +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); +#endif + /************************************************************************************ * Private Functions ************************************************************************************/ @@ -166,10 +209,9 @@ static void rtc_dumpregs(FAR const char *msg) rtclldbg(" TSDR: %08x\n", getreg32(STM32L4_RTC_TSDR)); rtclldbg(" TSSSR: %08x\n", getreg32(STM32L4_RTC_TSSSR)); rtclldbg(" CALR: %08x\n", getreg32(STM32L4_RTC_CALR)); - rtclldbg(" TAFCR: %08x\n", getreg32(STM32L4_RTC_TAMPCR_OFFSET)); + rtclldbg(" TAMPCR: %08x\n", getreg32(STM32L4_RTC_TAMPCR)); rtclldbg("ALRMASSR: %08x\n", getreg32(STM32L4_RTC_ALRMASSR)); rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32L4_RTC_ALRMBSSR)); - rtclldbg("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG)); } #else # define rtc_dumpregs(msg) @@ -193,17 +235,48 @@ static void rtc_dumpregs(FAR const char *msg) static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) { rtclldbg("%s:\n", msg); +#if 0 rtclldbg(" tm_sec: %08x\n", tp->tm_sec); rtclldbg(" tm_min: %08x\n", tp->tm_min); rtclldbg(" tm_hour: %08x\n", tp->tm_hour); rtclldbg(" tm_mday: %08x\n", tp->tm_mday); rtclldbg(" tm_mon: %08x\n", tp->tm_mon); rtclldbg(" tm_year: %08x\n", tp->tm_year); +#else + rtclldbg(" tm: %04d-%02d-%02d %02d:%02d:%02d\n", + tp->tm_year+1900, tp->tm_mon+1, tp->tm_mday, + tp->tm_hour, tp->tm_min, tp->tm_sec); +#endif } #else # define rtc_dumptime(tp, msg) #endif +/************************************************************************************ + * Name: rtc_is_inits + * + * Description: + * Returns 'true' if the RTC has been initialized (according to the RTC itself). + * It will be 'false' if the RTC has never been initialized since first time power + * up, and the counters are stopped until it is first initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * bool -- true if the INITS flag is set in the ISR. + * + ************************************************************************************/ + +static bool rtc_is_inits(void) +{ + uint32_t regval; + + regval = getreg32(STM32L4_RTC_ISR); + + return (regval & RTC_ISR_INITS) ? true : false; +} + /************************************************************************************ * Name: rtc_wprunlock * @@ -432,74 +505,6 @@ static int rtc_bcd2bin(uint32_t value) return (int)(tens + (value & 0x0f)); } -/************************************************************************************ - * Name: rtc_setup - * - * Description: - * Performs first time configuration of the RTC. A special value written into - * back-up register 0 will prevent this function from being called on sub-sequent - * resets or power up. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -static int rtc_setup(void) -{ - uint32_t regval; - int ret; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the 24 hour format by clearing the FMT bit in the RTC - * control register - */ - - regval = getreg32(STM32L4_RTC_CR); - regval &= ~RTC_CR_FMT; - putreg32(regval, STM32L4_RTC_CR); - - /* Configure RTC pre-scaler with the required values */ - -#ifdef CONFIG_STM32L4_RTC_HSECLOCK - /* For a 1 MHz clock this yields 0.9999360041 Hz on the second - * timer - which is pretty close. - */ - - putreg32(((uint32_t)7182 << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); -#else - /* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */ - - putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); -#endif - - /* Exit RTC initialization mode */ - - rtc_exitinit(); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - - return ret; -} - /************************************************************************************ * Name: rtc_resume * @@ -528,15 +533,15 @@ static void rtc_resume(void) /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ - putreg32((1 << 18), STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); #endif } /************************************************************************************ - * Name: rtc_interrupt + * Name: stm32l4_rtc_alarm_handler * * Description: - * RTC interrupt service routine + * RTC ALARM interrupt service routine through the EXTI line * * Input Parameters: * irq - The IRQ number that generated the interrupt @@ -548,10 +553,259 @@ static void rtc_resume(void) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int rtc_interrupt(int irq, void *context) +static int stm32l4_rtc_alarm_handler(int irq, void *context) { -#warning "Missing logic" - return OK; + FAR struct alm_cbinfo_s *cbinfo; + alm_callback_t cb; + FAR void *arg; + uint32_t isr; + uint32_t cr; + int ret = OK; + + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + (void)stm32l4_pwr_enablebkp(true); + + /* Check for EXTI from Alarm A or B and handle according */ + + cr = getreg32(STM32L4_RTC_CR); + if ((cr & RTC_CR_ALRAIE) != 0) + { + isr = getreg32(STM32L4_RTC_ISR); + if ((isr & RTC_ISR_ALRAF) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm A callback */ + + cb = cbinfo->ac_cb; + arg = (FAR void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(arg, RTC_ALARMA); + } + + /* note, bits 8-13 do /not/ require the write enable procedure */ + + isr = getreg32(STM32L4_RTC_ISR); + isr &= ~RTC_ISR_ALRAF; + putreg32(isr, STM32L4_RTC_ISR); + } + } + + cr = getreg32(STM32L4_RTC_CR); + if ((cr & RTC_CR_ALRBIE) != 0) + { + isr = getreg32(STM32L4_RTC_ISR); + if ((isr & RTC_ISR_ALRBF) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm B callback */ + + cb = cbinfo->ac_cb; + arg = (FAR void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(arg, RTC_ALARMB); + } + + /* note, bits 8-13 do /not/ require the write enable procedure */ + + isr = getreg32(STM32L4_RTC_ISR); + isr &= ~RTC_ISR_ALRBF; + putreg32(isr, STM32L4_RTC_ISR); + } + } + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + (void)stm32l4_pwr_enablebkp(false); + + return ret; +} +#endif + +/************************************************************************************ + * Name: rtchw_check_alrXwf X= a or B + * + * Description: + * Check registers + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRAWF for access to alarm register, + * Can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32L4_RTC_ISR); + if ((regval & RTC_ISR_ALRAWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrbwf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRAWF for access to alarm register, + * can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32L4_RTC_ISR); + if ((regval & RTC_ISR_ALRBWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +/************************************************************************************ + * Name: stm32_rtchw_set_alrmXr X is a or b + * + * Description: + * Set the alarm (A or B) hardware registers, using the required hardware access + * protocol + * + * Input Parameters: + * alarmreg - the register + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) +{ + int isr; + int ret = -EBUSY; + + /* Need to allow RTC register write + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm A & Interrupt A */ + + modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + /* Ensure Alarm A flag reset; this is edge triggered */ + + isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32L4_RTC_ISR); + + /* Wait for Alarm A to be writable */ + + ret = rtchw_check_alrawf(); + if (ret != OK) + { + goto errout_with_wprunlock; + } + + /* Set the RTC Alarm A register */ + + putreg32(alarmreg, STM32L4_RTC_ALRMAR); + putreg32(0, STM32L4_RTC_ALRMASSR); + rtcvdbg(" TR: %08x ALRMAR: %08x\n", + getreg32(STM32L4_RTC_TR), getreg32(STM32L4_RTC_ALRMAR)); + + /* Enable RTC alarm A */ + + modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +#ifdef CONFIG_RTC_ALARM +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) +{ + int isr; + int ret = -EBUSY; + + /* Need to allow RTC register write + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm B & Interrupt B */ + + modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + /* Ensure Alarm B flag reset; this is edge triggered */ + + isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32L4_RTC_ISR); + + /* Wait for Alarm B to be writable */ + + ret = rtchw_check_alrbwf(); + if (ret != OK) + { + goto rtchw_set_alrmbr_exit; + } + + /* Set the RTC Alarm B register */ + + putreg32(alarmreg, STM32L4_RTC_ALRMBR); + putreg32(0, STM32L4_RTC_ALRMBSSR); + rtcvdbg(" TR: %08x ALRMBR: %08x\n", + getreg32(STM32L4_RTC_TR), getreg32(STM32L4_RTC_ALRMBR)); + + /* Enable RTC alarm B */ + + modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + +rtchw_set_alrmbr_exit: + rtc_wprlock(); + return ret; } #endif @@ -576,206 +830,169 @@ static int rtc_interrupt(int irq, void *context) int up_rtc_initialize(void) { + bool init_stat; uint32_t regval; - uint32_t tr_bkp; - uint32_t dr_bkp; int ret; - int maxretry = 10; - int nretry = 0; - /* Clocking for the PWR block must be provided. + rtc_dumpregs("Before Initialization"); + + /* See if the clock has already been initialized; since it is battery + * backed, we don't need or want to re-initialize on each reset. */ - rtc_dumpregs("On reset"); + init_stat = rtc_is_inits(); - /* Select the clock source */ - /* Save the token before losing it when resetting */ - - regval = getreg32(RTC_MAGIC_REG); - - (void)stm32l4_pwr_enablebkp(true); - - if (regval != RTC_MAGIC) + if(!init_stat) { - /* We might be changing RTCSEL - to ensure such changes work, we must reset the - * backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); - - /* Some boards do not have the external 32khz oscillator installed, for those - * boards we must fallback to the crummy internal RC clock or the external high - * rate clock - */ - -#ifdef CONFIG_STM32L4_RTC_HSECLOCK - /* Use the HSE clock as the input to the RTC block */ - - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); - -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - /* Use the LSI clock as the input to the RTC block */ - - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); - -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - /* Use the LSE clock as the input to the RTC block */ - - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); - -#endif - /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); - } - else /* The RTC is already in use: check if the clock source is changed */ - { -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) || defined(CONFIG_STM32L4_RTC_LSICLOCK) || \ - defined(CONFIG_STM32L4_RTC_LSECLOCK) - - uint32_t clksrc = getreg32(STM32L4_RCC_BDCR); - -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) - if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_HSE) -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSI) -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSE) -#endif -#endif - { - tr_bkp = getreg32(STM32L4_RTC_TR); - dr_bkp = getreg32(STM32L4_RTC_DR); - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); - -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) - /* Change to the new clock as the input to the RTC block */ - - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); - -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); - -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); -#endif - - putreg32(tr_bkp, STM32L4_RTC_TR); - putreg32(dr_bkp, STM32L4_RTC_DR); - - /* Remember that the RTC is initialized */ - - putreg32(RTC_MAGIC, RTC_MAGIC_REG); - - /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); - } - } - - (void)stm32l4_pwr_enablebkp(false); - - /* Loop, attempting to initialize/resume the RTC. This loop is necessary - * because it seems that occasionally it takes longer to initialize the RTC - * (the actual failure is in rtc_synchwait()). - */ - - do - { - /* Wait for the RTC Time and Date registers to be synchronized with RTC APB - * clock. - */ - - ret = rtc_synchwait(); - - /* Check that rtc_syncwait() returned successfully */ - - switch (ret) - { - case OK: - { - rtclldbg("rtc_syncwait() okay\n"); - break; - } - - default: - { - rtclldbg("rtc_syncwait() failed (%d)\n", ret); - break; - } - } - } - while (ret != OK && ++nretry < maxretry); - - /* Check if the one-time initialization of the RTC has already been - * performed. We can determine this by checking if the magic number - * has been writing to to back-up date register DR0. - */ - - if (regval != RTC_MAGIC) - { - rtclldbg("Do setup\n"); - - /* Perform the one-time setup of the LSE clocking to the RTC */ - - ret = rtc_setup(); - /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ (void)stm32l4_pwr_enablebkp(true); - /* Remember that the RTC is initialized */ +#if 0 + /* Do not reset the backup domain; you will lose your clock setup done in *rcc.c */ - putreg32(RTC_MAGIC, RTC_MAGIC_REG); + modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); +#endif + +#if defined(CONFIG_STM32L4_RTC_HSECLOCK) + modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); +#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) + modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); +#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) + modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); +#endif + + /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ + + modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + if (OK != rtc_enterinit()) + { + /* Enable the write protection for RTC registers */ + + rtc_wprlock(); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + (void)stm32l4_pwr_enablebkp(false); + + rtc_dumpregs("After Failed Initialization"); + + return -1; + } + else + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + + regval = getreg32(STM32L4_RTC_CR); + regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); + + /* Configure RTC pre-scaler with the required values */ + +#ifdef CONFIG_STM32L4_RTC_HSECLOCK + /* The HSE is divided by 32 prior to the prescaler we set here. + * 1953 + * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC + */ + + /* For a 1 MHz clock this yields 0.9999360041 Hz on the second + * timer - which is pretty close. + */ + + putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32L4_RTC_PRER); +#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) + /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, though) */ + + putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32L4_RTC_PRER); +#else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */ + /* Correct values for 32.768 KHz LSE clock */ + + putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32L4_RTC_PRER); +#endif + + /* Wait for the RTC Time and Date registers to be synchronized with RTC APB + * clock. + */ + + ret = rtc_synchwait(); + (void)ret; + + /* Exit Initialization mode */ + + rtc_exitinit(); + + /* Enable the write protection for RTC registers */ + + rtc_wprlock(); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + (void)stm32l4_pwr_enablebkp(false); + } } else { - rtclldbg("Do resume\n"); + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ - /* RTC already set-up, just resume normal operation */ + (void)stm32l4_pwr_enablebkp(true); + + /* Disable the write protection for RTC registers */ + + //rtc_wprunlock(); rtc_resume(); - rtc_dumpregs("Did resume"); - } - - /* Disable write access to the backup domain (RTC registers, RTC backup - * data registers and backup SRAM). - */ - - (void)stm32l4_pwr_enablebkp(false); - - if (ret != OK && nretry > 0) - { - rtclldbg("setup/resume ran %d times and failed with %d\n", - nretry, ret); - return -ETIMEDOUT; + + /* Enable the write protection for RTC registers */ + + //rtc_wprlock(); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + (void)stm32l4_pwr_enablebkp(false); } +#ifdef CONFIG_RTC_ALARM /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are * connected to the EXTI controller. To enable the RTC Alarm interrupt, the * following sequence is required: * * 1. Configure and enable the EXTI Line 18 in interrupt mode and select the * rising edge sensitivity. + * EXTI line 19 RTC Tamper or Timestamp or CSS_LSE + * EXTI line 20 RTC Wakeup * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ -#ifdef CONFIG_RTC_ALARM -# warning "Missing EXTI setup logic" - - /* Then attach the ALARM interrupt handler */ - - irq_attach(STM32L4_IRQ_RTC_WKUP, rtc_interrupt); - up_enable_irq(STM32L4_IRQ_RTC_WKUP); + stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler); #endif g_rtc_enabled = true; rtc_dumpregs("After Initialization"); + return OK; } @@ -1029,11 +1246,10 @@ int up_rtc_settime(FAR const struct timespec *tp) * Name: stm32l4_rtc_setalarm * * Description: - * Set up an alarm. Up to two alarms can be supported (ALARM A and ALARM B). + * Set an alarm to an absolute time using associated hardware. * * Input Parameters: - * tp - the time to set the alarm - * callback - the function to call when the alarm expires. + * alminfo - Information about the alarm configuration. * * Returned Value: * Zero (OK) on success; a negated errno on failure @@ -1041,27 +1257,166 @@ int up_rtc_settime(FAR const struct timespec *tp) ************************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) +int stm32l4_rtc_setalarm(FAR struct alm_setalarm_s *alminfo) { - int ret = -EBUSY; + FAR struct alm_cbinfo_s *cbinfo; + rtc_alarmreg_t alarmreg; + int ret = -EINVAL; - /* Is there already something waiting on the ALARM? */ + ASSERT(alminfo != NULL); + DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); - if (g_alarmcb == NULL) + /* REVISIT: Should test that the time is in the future */ + + rtc_dumptime(&alminfo->as_time, "New alarm time"); + + /* Break out the values to the HW alarm register format */ + + alarmreg = rtc_reg_alrmr_bin2bcd(&alminfo->as_time); + + /* Set the alarm in hardware and enable interrupts */ + + switch (alminfo->as_id) { - /* No.. Save the callback function pointer */ + case RTC_ALARMA: + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; - g_alarmcb = callback; + ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + } + break; - /* Break out the time values */ -#warning "Missing logic" + case RTC_ALARMB: + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; - /* The set the alarm */ -#warning "Missing logic" + ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + } + break; - ret = OK; + default: + rtcvdbg("ERROR: Invalid ALARM%d\n", alminfo->as_id); + break; } + rtc_dumpregs("After alarm setting"); + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32l4_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) +{ + int ret = -EINVAL; + + DEBUGASSERT(RTC_ALARM_LAST > alarmid); + + /* Cancel the alarm in hardware and disable interrupts */ + + switch (alarmid) + { + case RTC_ALARMA: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Need to follow RTC register wrote protection. + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + ret = rtchw_check_alrawf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32L4_RTC_ALRMAR); + modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0); + rtc_wprlock(); + ret = OK; + } + break; + + case RTC_ALARMB: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Need to follow RTC register wrote protection. + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + ret = rtchw_check_alrbwf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32L4_RTC_ALRMBR); + modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0); + rtc_wprlock(); + ret = OK; + } + break; + + default: + rtcvdbg("ERROR: Invalid ALARM%d\n", alarmid); + break; + } + + return ret; + +errout_with_wprunlock: + rtc_wprlock(); return ret; } #endif diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 68e9e752457..8f68409dba5 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -1723,8 +1723,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_USART_BREAKS case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { - irqstate_t flags = enter_critical_section(); - uint32_t cr2 = up_serialin(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr2; + irqstate_t flags; + + flags = enter_critical_section(); + cr2 = up_serialin(priv, STM32L4_USART_CR2_OFFSET); up_serialout(priv, STM32L4_USART_CR2_OFFSET, cr2 | USART_CR2_LINEN); leave_critical_section(flags); } @@ -1732,9 +1735,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ { + uint32_t cr2; irqstate_t flags; + flags = enter_critical_section(); - uint32_t cr1 = up_serialin(priv, STM32L4_USART_CR2_OFFSET); + cr2 = up_serialin(priv, STM32L4_USART_CR2_OFFSET); up_serialout(priv, STM32L4_USART_CR2_OFFSET, cr2 & ~USART_CR2_LINEN); leave_critical_section(flags); } diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c new file mode 100644 index 00000000000..4547dcc4560 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_uid.c @@ -0,0 +1,63 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_uid.c + * + * Copyright (C) 2015 Marawan Ragab. All rights reserved. + * Author: Marawan Ragab + * dev@ziggurat9.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "stm32l4_uid.h" + +#ifdef STM32L4_SYSMEM_UID + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +void stm32l4_get_uniqueid(uint8_t uniqueid[12]) +{ + int i; + + for (i = 0; i < 12; i++) + { + uniqueid[i] = *((uint8_t*)(STM32L4_SYSMEM_UID)+i); + } +} + +#endif /* STM32L4_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l4/stm32l4_uid.h b/arch/arm/src/stm32l4/stm32l4_uid.h new file mode 100644 index 00000000000..50805c1509f --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_uid.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_uid.h + * + * Copyright (C) 2015 Marawan Ragab. All rights reserved. + * Author: Marawan Ragab + * dev@ziggurat9.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +void stm32l4_get_uniqueid(uint8_t uniqueid[12]); + +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H */ diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 64c8021f954..b97fd002dcd 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -57,9 +57,10 @@ #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) -/* Same for HSI */ +/* Same for HSI and MSI */ #define HSIRDY_TIMEOUT HSERDY_TIMEOUT +#define MSIRDY_TIMEOUT HSERDY_TIMEOUT /* HSE divisor to yield ~1MHz RTC clock */ @@ -578,14 +579,38 @@ static void stm32l4_stdclockconfig(void) #elif defined(STM32L4_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ -# error STM32L4_BOARD_USEMSI not yet implemented in arch/arm/src/stm32l4/stm32l4x6xx_rcc.c + /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ + + for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) + { + if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + /* setting MSIRANGE */ - /* setting MSIPLLEN */ regval = getreg32(STM32L4_RCC_CR); - regval |= RCC_CR_MSION; /* Enable MSI */ + regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ putreg32(regval, STM32L4_RCC_CR); + /* Wait until the MSI is ready (or until a timeout elapsed) */ + + for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the MSIRDY flag is the set in the CR */ + + if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + #elif defined(STM32L4_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ @@ -696,6 +721,8 @@ static void stm32l4_stdclockconfig(void) #ifdef STM32L4_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; +#elif defined(STM32L4_BOARD_USEMSI) + regval |= RCC_PLLCFG_PLLSRC_MSI; #else /* if STM32L4_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif @@ -827,12 +854,20 @@ static void stm32l4_stdclockconfig(void) * and we need to ensure it is first off before doing so. */ - /* turn on the LSE oscillator + /* Turn on the LSE oscillator * XXX this will almost surely get moved since we also want to use * this for automatically trimming MSI, etc. */ stm32l4_rcc_enablelse(); + +# if defined(STM32L4_BOARD_USEMSI) + /* Now that LSE is up, auto trim the MSI */ + + regval = getreg32(STM32L4_RCC_CR); + regval |= RCC_CR_MSIPLLEN; + putreg32(regval, STM32L4_RCC_CR); +# endif #endif #if defined(STM32L4_USE_CLK48) diff --git a/arch/arm/src/tiva/tiva_gpio.c b/arch/arm/src/tiva/tiva_gpio.c index 1ca011909a6..6ce03bdae55 100644 --- a/arch/arm/src/tiva/tiva_gpio.c +++ b/arch/arm/src/tiva/tiva_gpio.c @@ -661,9 +661,9 @@ static inline void tiva_interrupt(uint32_t pinset) { case GPIO_INT_FALLINGEDGE: { - isset = pin; + isclr = pin; ibeclr = pin; - ievset = pin; + ievclr = pin; } break; diff --git a/audio/Makefile b/audio/Makefile index 33b3a26a798..42ee4ea319b 100644 --- a/audio/Makefile +++ b/audio/Makefile @@ -62,6 +62,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libaudio$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/binfmt/Makefile b/binfmt/Makefile index 5c5244d89bf..7240ca9b15c 100644 --- a/binfmt/Makefile +++ b/binfmt/Makefile @@ -1,7 +1,7 @@ ############################################################################ # nxflat/Makefile # -# Copyright (C) 2007-2009, 2012-2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2009, 2012-2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -80,6 +80,7 @@ BINFMT_OBJS = $(BINFMT_AOBJS) $(BINFMT_COBJS) BIN = libbinfmt$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(BINFMT_AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/configs/Kconfig b/configs/Kconfig index 7b9618bfda6..17d7a9ba85c 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -1274,7 +1274,6 @@ config BOARD_CUSTOM_LEDS bool "Custom board LEDs" default n select ARCH_HAVE_LEDS - select ARCH_LEDS config BOARD_CUSTOM_BUTTONS bool "Custom board buttons" diff --git a/configs/Makefile b/configs/Makefile index 4e96cc8dfdb..496601da0b0 100644 --- a/configs/Makefile +++ b/configs/Makefile @@ -1,7 +1,7 @@ ############################################################################ # configs/Makefile # -# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -58,6 +58,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libconfigs$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -84,4 +85,4 @@ distclean: clean $(call DELFILE, Make.dep) $(call DELFILE, .depend) --include Make.dep \ No newline at end of file +-include Make.dep diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index 11737a5671c..6fe165d4615 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -814,7 +814,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_CANUTILS_UAVCAN=y CONFIG_UAVCAN_LIBUAVCAN_URL="https://github.com/UAVCAN/libuavcan/archive" -CONFIG_UAVCAN_LIBUAVCAN_VERSION="c152f28a620ceec9f63581a7c99fe77c89938048" +CONFIG_UAVCAN_LIBUAVCAN_VERSION="b04396ace50155573e545ed9bf2fb09964ee2367" CONFIG_UAVCAN_DSDL_URL="https://github.com/UAVCAN/dsdl/archive" CONFIG_UAVCAN_DSDL_VERSION="9804a3e6972825586be252ce08dd899f44994b14" CONFIG_UAVCAN_PYUAVCAN_URL="https://github.com/UAVCAN/pyuavcan/archive" diff --git a/configs/nucleo-l476rg/include/nucleo-l476rg.h b/configs/nucleo-l476rg/include/nucleo-l476rg.h index 4e4ec25d1f8..e661f5965fb 100644 --- a/configs/nucleo-l476rg/include/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/include/nucleo-l476rg.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-l476rg/include/nucleo-l476rg.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,8 +49,19 @@ * Pre-processor Definitions ************************************************************************************/ +#if 1 +# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */ +#elif 0 +/* Make sure you installed one! */ + +# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */ +#else +# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */ +#endif + /* Clocking *************************************************************************/ +#if defined(HSI_CLOCK_CONFIG) /* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However, as * shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI. @@ -88,6 +99,10 @@ #define STM32L4_BOARD_USEHSI 1 +/* XXX sysclk mux = pllclk */ + +/* XXX pll source mux = hsi */ + /* REVISIT: Trimming of the HSI and MSI is not yet supported. */ /* Main PLL Configuration. @@ -245,7 +260,7 @@ /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -//#define STM32L4_USE_LSE 1 +#define STM32L4_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ @@ -287,6 +302,167 @@ /* TODO SDMMC */ +#elif defined(HSE_CLOCK_CONFIG) + +/* Use the HSE */ + +#define STM32L4_BOARD_USEHSE 1 + +/* XXX sysclk mux = pllclk */ + +/* XXX pll source mux = hse */ + +/* Prescaler common to all PLL inputs */ + +#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) + +/* 'main' PLL config; we use this to generate our system clock */ + +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32L4_PLLCFG_PLLP 0 +#undef STM32L4_PLLCFG_PLLP_ENABLED +#define STM32L4_PLLCFG_PLLQ 0 +#undef STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32L4_PLLCFG_PLLR_ENABLED + +/* 'SAIPLL1' is used to generate the 48 MHz clock */ + +#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32L4_PLLSAI1CFG_PLLP 0 +#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#define STM32L4_PLLSAI1CFG_PLLR 0 +#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED + +/* 'SAIPLL2' is not used in this application */ + +#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32L4_PLLSAI2CFG_PLLP 0 +#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#define STM32L4_PLLSAI2CFG_PLLR 0 +#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED + +#define STM32L4_SYSCLK_FREQUENCY 80000000ul + +/* Enable CLK48; get it from PLLSAI1 */ + +#define STM32L4_USE_CLK48 +#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 + +/* Enable LSE (for the RTC) */ + +#define STM32L4_USE_LSE 1 + +/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ + +#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* Configure the APB1 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) + +/* Configure the APB2 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) + +#elif defined(MSI_CLOCK_CONFIG) + +/* Use the MSI; frequ = 4 MHz; autotrim from LSE */ + +#define STM32L4_BOARD_USEMSI 1 +#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M + +/* XXX sysclk mux = pllclk */ + +/* XXX pll source mux = msi */ + +/* prescaler common to all PLL inputs */ + +#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) + +/* 'main' PLL config; we use this to generate our system clock */ + +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32L4_PLLCFG_PLLP 0 +#undef STM32L4_PLLCFG_PLLP_ENABLED +#define STM32L4_PLLCFG_PLLQ 0 +#undef STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32L4_PLLCFG_PLLR_ENABLED + +/* 'SAIPLL1' is used to generate the 48 MHz clock */ + +#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32L4_PLLSAI1CFG_PLLP 0 +#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#define STM32L4_PLLSAI1CFG_PLLR 0 +#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED + +/* 'SAIPLL2' is not used in this application */ + +#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32L4_PLLSAI2CFG_PLLP 0 +#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#define STM32L4_PLLSAI2CFG_PLLR 0 +#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED + +#define STM32L4_SYSCLK_FREQUENCY 80000000ul + +/* Enable CLK48; get it from PLLSAI1 */ + +#define STM32L4_USE_CLK48 +#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 + +/* Enable LSE (for the RTC) */ + +#define STM32L4_USE_LSE 1 + +/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ + +#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* Configure the APB1 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) + +/* Configure the APB2 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) + +#endif + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 10abc318495..a4c68715642 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -49,7 +49,6 @@ CONFIG_DEBUG_VERBOSE=y # # Subsystem Debug Options # -CONFIG_DEBUG_AUDIO=y CONFIG_DEBUG_BINFMT=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_GRAPHICS=y @@ -60,6 +59,7 @@ CONFIG_DEBUG_LIB=y # # OS Function Debug Options # +# CONFIG_DEBUG_DMA is not set # CONFIG_DEBUG_HEAP is not set # CONFIG_DEBUG_IRQ is not set @@ -69,6 +69,7 @@ CONFIG_DEBUG_LIB=y CONFIG_DEBUG_LEDS=y CONFIG_DEBUG_ANALOG=y CONFIG_DEBUG_GPIO=y +# CONFIG_DEBUG_RTC is not set CONFIG_DEBUG_SPI=y CONFIG_ARCH_HAVE_STACKCHECK=y # CONFIG_STACK_COLORATION is not set @@ -101,7 +102,8 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set # CONFIG_ARCH_CHIP_KINETIS is not set # CONFIG_ARCH_CHIP_KL is not set # CONFIG_ARCH_CHIP_LM is not set @@ -133,6 +135,7 @@ CONFIG_ARCH_CORTEXM4=y # CONFIG_ARCH_CORTEXM7 is not set # CONFIG_ARCH_CORTEXA5 is not set # CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set # CONFIG_ARCH_CORTEXR4 is not set # CONFIG_ARCH_CORTEXR4F is not set # CONFIG_ARCH_CORTEXR5 is not set @@ -141,6 +144,7 @@ CONFIG_ARCH_CORTEXM4=y # CONFIG_ARCH_CORTEXR7F is not set CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="stm32l4" +# CONFIG_ARM_TOOLCHAIN_IAR is not set CONFIG_ARM_TOOLCHAIN_GNU=y # CONFIG_ARMV7M_USEBASEPRI is not set CONFIG_ARCH_HAVE_CMNVECTOR=y @@ -149,6 +153,7 @@ CONFIG_ARMV7M_CMNVECTOR=y CONFIG_ARCH_HAVE_FPU=y CONFIG_ARCH_HAVE_DPFPU=y # CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y # CONFIG_ARM_MPU is not set # CONFIG_DEBUG_HARDFAULT is not set @@ -162,6 +167,7 @@ CONFIG_ARMV7M_HAVE_ITCM=y CONFIG_ARMV7M_HAVE_DTCM=y # CONFIG_ARMV7M_ITCM is not set # CONFIG_ARMV7M_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y @@ -171,6 +177,7 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set # CONFIG_USART2_RS485 is not set +# CONFIG_USART2_RXDMA is not set # CONFIG_SERIAL_DISABLE_REORDERING is not set # @@ -185,6 +192,12 @@ CONFIG_STM32L4_STM32L476XX=y # CONFIG_STM32L4_FLASH_512KB is not set CONFIG_STM32L4_FLASH_1024KB=y +# +# SRAM2 Options +# +CONFIG_STM32L4_SRAM2_HEAP=y +CONFIG_STM32L4_SRAM2_INIT=y + # # STM32L4 Peripheral Support # @@ -192,7 +205,7 @@ CONFIG_STM32L4_FLASH_1024KB=y # CONFIG_STM32L4_ADC is not set # CONFIG_STM32L4_CAN is not set # CONFIG_STM32L4_DAC is not set -# CONFIG_STM32L4_DMA is not set +CONFIG_STM32L4_DMA=y # CONFIG_STM32L4_I2C is not set # CONFIG_STM32L4_SAI is not set # CONFIG_STM32L4_SPI is not set @@ -202,8 +215,8 @@ CONFIG_STM32L4_USART=y # # AHB1 Peripherals # -# CONFIG_STM32L4_DMA1 is not set -# CONFIG_STM32L4_DMA2 is not set +CONFIG_STM32L4_DMA1=y +CONFIG_STM32L4_DMA2=y # CONFIG_STM32L4_CRC is not set # CONFIG_STM32L4_TSC is not set @@ -215,17 +228,18 @@ CONFIG_STM32L4_USART=y # CONFIG_STM32L4_ADC2 is not set # CONFIG_STM32L4_ADC3 is not set # CONFIG_STM32L4_AES is not set -# CONFIG_STM32L4_RNG is not set +CONFIG_STM32L4_RNG=y # # AHB3 Peripherals # # CONFIG_STM32L4_FMC is not set -# CONFIG_STM32L4_QUADSPI is not set +# CONFIG_STM32L4_QSPI is not set # # APB1 Peripherals # +CONFIG_STM32L4_PWR=y # CONFIG_STM32L4_TIM2 is not set # CONFIG_STM32L4_TIM3 is not set # CONFIG_STM32L4_TIM4 is not set @@ -276,8 +290,11 @@ CONFIG_STM32L4_FIREWALL=y # CONFIG_STM32L4_WWDG is not set CONFIG_STM32L4_FLASH_PREFETCH=y CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -# CONFIG_STM32L4_CUSTOM_CLOCKCONFIG is not set -# CONFIG_STM32L4_SAI1PLL is not set +# CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is not set +CONFIG_STM32L4_RTC_LSECLOCK=y +# CONFIG_STM32L4_RTC_LSICLOCK is not set +# CONFIG_STM32L4_RTC_HSECLOCK is not set +CONFIG_STM32L4_SAI1PLL=y # CONFIG_STM32L4_SAI2PLL is not set # @@ -290,12 +307,13 @@ CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y # # CONFIG_ARCH_NOINTC is not set # CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_DMA=y CONFIG_ARCH_HAVE_IRQPRIO=y # CONFIG_ARCH_L2CACHE is not set # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set # CONFIG_ARCH_HAVE_ADDRENV is not set # CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set CONFIG_ARCH_HAVE_VFORK=y # CONFIG_ARCH_HAVE_MMU is not set CONFIG_ARCH_HAVE_MPU=y @@ -346,6 +364,7 @@ CONFIG_RAM_SIZE=98304 # Board Selection # CONFIG_ARCH_BOARD_NUCLEO_L476RG=y +# CONFIG_ARCH_BOARD_STM32L476VG_DISCO is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="nucleo-l476rg" @@ -362,7 +381,14 @@ CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # -# CONFIG_LIB_BOARDCTL is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -381,9 +407,6 @@ CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set # CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2014 -CONFIG_START_MONTH=5 -CONFIG_START_DAY=5 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=8 CONFIG_WDOG_INTRESERVE=1 @@ -472,6 +495,8 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +CONFIG_ARCH_HAVE_RNG=y +CONFIG_DEV_RANDOM=y # CONFIG_DEV_LOOP is not set # @@ -500,7 +525,13 @@ CONFIG_SPI_EXCHANGE=y # Timer Driver Support # # CONFIG_TIMER is not set -# CONFIG_RTC is not set +CONFIG_RTC=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_NALARMS=2 +CONFIG_RTC_DRIVER=y +CONFIG_RTC_IOCTL=y +# CONFIG_RTC_EXTERNAL is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set # CONFIG_AUDIO_DEVICES is not set @@ -514,6 +545,7 @@ CONFIG_SPI_EXCHANGE=y # LED Support # # CONFIG_USERLED is not set +# CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set # CONFIG_MMCSD is not set # CONFIG_MODEM is not set @@ -579,7 +611,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USART2_DMA is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set -# CONFIG_WIRELESS is not set +# CONFIG_DRIVERS_WIRELESS is not set # # System Logging Device Options @@ -642,7 +674,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # Memory Management # # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 +CONFIG_MM_REGIONS=2 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set @@ -651,6 +683,10 @@ CONFIG_MM_REGIONS=1 # # CONFIG_AUDIO is not set +# +# Wireless Support +# + # # Binary Loader # @@ -694,6 +730,8 @@ CONFIG_ARCH_LOWPUTC=y CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set # CONFIG_LIBC_NETDB is not set # @@ -731,6 +769,12 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_ALARM_PRIORITY=100 +CONFIG_EXAMPLES_ALARM_STACKSIZE=2048 +CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0" +CONFIG_EXAMPLES_ALARM_SIGNO=1 +# CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -770,7 +814,10 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set +CONFIG_EXAMPLES_RANDOM=y +CONFIG_EXAMPLES_MAXSAMPLES=64 +CONFIG_EXAMPLES_NSAMPLES=8 +# CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set @@ -779,6 +826,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_SLCD is not set # CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set @@ -791,6 +839,12 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # # File System Utilities # +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set # # Graphics Support @@ -822,6 +876,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # NSH Library # CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set # # Command Line Configuration @@ -846,7 +901,7 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_CD is not set # CONFIG_NSH_DISABLE_CP is not set # CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DATE is not set # CONFIG_NSH_DISABLE_DD is not set # CONFIG_NSH_DISABLE_DF is not set # CONFIG_NSH_DISABLE_DELROUTE is not set @@ -909,7 +964,9 @@ CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set # # NxWidgets/NxWM @@ -928,7 +985,6 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_HEX2BIN is not set -# CONFIG_SYSTEM_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set CONFIG_READLINE_HAVE_EXTMATCH=y @@ -936,7 +992,8 @@ CONFIG_SYSTEM_READLINE=y CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_RAMTRON is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_ZMODEM is not set +# CONFIG_SYSTEM_DISCOTEST is not set diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h index b5b56eb5a0c..7f1ef0feef7 100644 --- a/configs/nucleo-l476rg/src/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h @@ -52,7 +52,15 @@ ************************************************************************************/ /* Configuration ********************************************************************/ +#define HAVE_RTC_DRIVER 1 #define HAVE_MMCSD 1 + +/* Check if we can support the RTC driver */ + +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + #if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index b7f5f1e6b4d..5a8b78513ab 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -55,6 +55,11 @@ #include "nucleo-l476rg.h" +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32l4_rtc.h" +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -83,9 +88,12 @@ void up_netinitialize(void) int board_app_initialize(void) { -#if defined(HAVE_MMCSD) || defined(CONFIG_AJOYSTICK) - int ret; +#ifdef HAVE_RTC_DRIVER + FAR struct rtc_lowerhalf_s *rtclower; #endif + int ret; + + (void)ret; /* Configure CPU load estimation */ @@ -93,6 +101,30 @@ int board_app_initialize(void) cpuload_initialize_once(); #endif +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32L4 lower-half RTC driver */ + + rtclower = stm32l4_rtc_lowerhalf(); + if (!rtclower) + { + sdbg("ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, rtclower); + if (ret < 0) + { + sdbg("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + return ret; + } + } +#endif + #ifdef HAVE_MMCSD /* First, get an instance of the SDIO interface */ diff --git a/configs/stm32f4discovery/uavcan/defconfig b/configs/stm32f4discovery/uavcan/defconfig index abdde2ee949..1bc92535c77 100644 --- a/configs/stm32f4discovery/uavcan/defconfig +++ b/configs/stm32f4discovery/uavcan/defconfig @@ -843,11 +843,11 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_CANUTILS_UAVCAN=y CONFIG_UAVCAN_LIBUAVCAN_URL="https://github.com/UAVCAN/libuavcan/archive" -CONFIG_UAVCAN_LIBUAVCAN_VERSION="531433a3261ff1568e824c240d0f1c6ecef73be1" +CONFIG_UAVCAN_LIBUAVCAN_VERSION="b04396ace50155573e545ed9bf2fb09964ee2367" CONFIG_UAVCAN_DSDL_URL="https://github.com/UAVCAN/dsdl/archive" CONFIG_UAVCAN_DSDL_VERSION="9804a3e6972825586be252ce08dd899f44994b14" CONFIG_UAVCAN_PYUAVCAN_URL="https://github.com/UAVCAN/pyuavcan/archive" -CONFIG_UAVCAN_PYUAVCAN_VERSION="4e2798ec3da8e8493b769da514f3b96eea5773e2" +CONFIG_UAVCAN_PYUAVCAN_VERSION="c58477a644d20ccf95a20c151f3a0402f271c3b8" CONFIG_UAVCAN_STM32_NUM_IFACES=1 # CONFIG_UAVCAN_STM32_TIM2 is not set # CONFIG_UAVCAN_STM32_TIM3 is not set diff --git a/configs/stm32l476vg-disco/include/nsh_romfsimg.h b/configs/stm32l476vg-disco/include/nsh_romfsimg.h new file mode 100644 index 00000000000..6bf0d908f08 --- /dev/null +++ b/configs/stm32l476vg-disco/include/nsh_romfsimg.h @@ -0,0 +1,89 @@ +unsigned char romfs_img[] = { + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, + 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 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0x00 +}; +unsigned int romfs_img_len = 1024; diff --git a/configs/stm32l476vg-disco/include/rcS.template b/configs/stm32l476vg-disco/include/rcS.template new file mode 100644 index 00000000000..ba8d905ae46 --- /dev/null +++ b/configs/stm32l476vg-disco/include/rcS.template @@ -0,0 +1,3 @@ +# sample rcS file; you must run tools/genromfs from within this +# location to convert this file to nsh_romfsimg.h for inclusion in the build + diff --git a/configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index d90e38428f8..7db8d8603eb 100644 --- a/configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -51,9 +51,9 @@ /* Clocking *************************************************************************/ -/* The stm32l476vg-disco supports both HSE and LSE crystals (X2 and X3). However, as - * shipped, the HSE X2 crystal is not populated. Therefore the stm32l476vg-disco - * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI. +/* The stm32l476vg-disco supports both HSE and LSE crystals. As shipped, the HSE + * crystal is not populated. Therefore the stm32l476vg-disco will need to run off the + * 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal. */ /* HSI - 16 MHz RC factory-trimmed @@ -69,18 +69,27 @@ #define BOARD_AHB_FREQUENCY 80000000ul -/* XXX review the STM32L4_BOARD_USEHSI usage, it has too much influence in - * stm32l4x6xx_rcc.c. I suspect it is fine for it to turn on and off that - * ocillator, but really that's all it should do (e.g. it also controls - * input of teh PLLs. Also, it should be fine/desireable to support things - * like turning on both HSI and MSI, because they plausibly can both be - * used at the same time; currently those choices HSE/HSI16/MSI are - * mutually exclusive. +/* XXX there needs to be independent selections for the System Clock Mux and + * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL + * Source Mux is chosen by the following define. This is probably OK in many + * cases, but should be separated to support other power configurations. */ -#define STM32L4_BOARD_USEHSI 1 +#if 0 +# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */ +#elif 0 +/* Make sure you actually installed one! */ -/* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly +# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */ +#else +# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */ +#endif + +#if defined(HSI_CLOCK_CONFIG) + +#define STM32L4_BOARD_USEHSI 1 + +/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly as per comment above HSI) */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) @@ -136,7 +145,7 @@ #define STM32L4_USE_CLK48 1 #define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ +/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ #define STM32L4_USE_LSE 1 @@ -178,6 +187,167 @@ */ /* REVISIT : this can be configured */ +#elif defined(HSE_CLOCK_CONFIG) + +/* Use the HSE */ + +#define STM32L4_BOARD_USEHSE 1 + +/* XXX sysclk mux = pllclk */ + +/* XXX pll source mux = hse */ + +/* Prescaler common to all PLL inputs */ + +#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) + +/* 'main' PLL config; we use this to generate our system clock */ + +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32L4_PLLCFG_PLLP 0 +#undef STM32L4_PLLCFG_PLLP_ENABLED +#define STM32L4_PLLCFG_PLLQ 0 +#undef STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32L4_PLLCFG_PLLR_ENABLED + +/* 'SAIPLL1' is used to generate the 48 MHz clock */ + +#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32L4_PLLSAI1CFG_PLLP 0 +#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#define STM32L4_PLLSAI1CFG_PLLR 0 +#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED + +/* 'SAIPLL2' is not used in this application */ + +#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32L4_PLLSAI2CFG_PLLP 0 +#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#define STM32L4_PLLSAI2CFG_PLLR 0 +#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED + +#define STM32L4_SYSCLK_FREQUENCY 80000000ul + +/* Enable CLK48; get it from PLLSAI1 */ + +#define STM32L4_USE_CLK48 +#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 + +/* Enable LSE (for the RTC) */ + +#define STM32L4_USE_LSE 1 + +/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ + +#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* Configure the APB1 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) + +/* Configure the APB2 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) + +#elif defined(MSI_CLOCK_CONFIG) + +/* Use the MSI; frequ = 4 MHz; autotrim from LSE */ + +#define STM32L4_BOARD_USEMSI 1 +#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M + +/* XXX sysclk mux = pllclk */ + +/* XXX pll source mux = msi */ + +/* Prescaler common to all PLL inputs */ + +#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) + +/* 'main' PLL config; we use this to generate our system clock */ + +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32L4_PLLCFG_PLLP 0 +#undef STM32L4_PLLCFG_PLLP_ENABLED +#define STM32L4_PLLCFG_PLLQ 0 +#undef STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32L4_PLLCFG_PLLR_ENABLED + +/* 'SAIPLL1' is used to generate the 48 MHz clock */ + +#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32L4_PLLSAI1CFG_PLLP 0 +#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#define STM32L4_PLLSAI1CFG_PLLR 0 +#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED + +/* 'SAIPLL2' is not used in this application */ + +#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32L4_PLLSAI2CFG_PLLP 0 +#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#define STM32L4_PLLSAI2CFG_PLLR 0 +#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED + +#define STM32L4_SYSCLK_FREQUENCY 80000000ul + +/* Enable CLK48; get it from PLLSAI1 */ + +#define STM32L4_USE_CLK48 +#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 + +/* Enable LSE (for the RTC) */ + +#define STM32L4_USE_LSE 1 + +/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ + +#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* Configure the APB1 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) + +/* Configure the APB2 prescaler */ + +#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) + +#endif + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index 4f889363a79..78242a4deb8 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -50,7 +50,7 @@ CONFIG_ARCH_HAVE_HEAPCHECK=y # Subsystem Debug Options # # CONFIG_DEBUG_BINFMT is not set -CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_FS is not set # CONFIG_DEBUG_GRAPHICS is not set # CONFIG_DEBUG_LIB is not set # CONFIG_DEBUG_MM is not set @@ -398,7 +398,8 @@ CONFIG_NSH_MMCSDMINOR=0 # CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set -# CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_UNIQUEID=y +CONFIG_BOARDCTL_UNIQUEID_SIZE=12 # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_PWMTEST is not set @@ -542,7 +543,8 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_TIMER is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y -# CONFIG_RTC_ALARM is not set +CONFIG_RTC_ALARM=y +CONFIG_RTC_NALARMS=2 CONFIG_RTC_DRIVER=y CONFIG_RTC_IOCTL=y # CONFIG_RTC_EXTERNAL is not set @@ -696,16 +698,15 @@ CONFIG_FS_WRITABLE=y # CONFIG_FS_NAMED_SEMAPHORES is not set CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set -CONFIG_FS_FAT=y -# CONFIG_FAT_LCNAMES is not set -# CONFIG_FAT_LFN is not set -# CONFIG_FS_FATTIME is not set -# CONFIG_FAT_FORCE_INDIRECT is not set -# CONFIG_FAT_DMAMEMORY is not set -# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_FAT is not set # CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set +CONFIG_FS_ROMFS=y +CONFIG_FS_TMPFS=y +CONFIG_FS_TMPFS_BLOCKSIZE=512 +CONFIG_FS_TMPFS_DIRECTORY_ALLOCGUARD=64 +CONFIG_FS_TMPFS_DIRECTORY_FREEGUARD=128 +CONFIG_FS_TMPFS_FILE_ALLOCGUARD=512 +CONFIG_FS_TMPFS_FILE_FREEGUARD=1024 # CONFIG_FS_SMARTFS is not set # CONFIG_FS_BINFS is not set CONFIG_FS_PROCFS=y @@ -834,6 +835,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_ALARM_PRIORITY=100 +CONFIG_EXAMPLES_ALARM_STACKSIZE=2048 +CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0" +CONFIG_EXAMPLES_ALARM_SIGNO=1 CONFIG_EXAMPLES_BUTTONS=y CONFIG_EXAMPLES_BUTTONS_MIN=0 CONFIG_EXAMPLES_BUTTONS_MAX=4 @@ -853,14 +859,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set -CONFIG_EXAMPLES_FSTEST=y -CONFIG_EXAMPLES_FSTEST_MAXNAME=32 -CONFIG_EXAMPLES_FSTEST_MAXFILE=8192 -CONFIG_EXAMPLES_FSTEST_MAXIO=347 -CONFIG_EXAMPLES_FSTEST_MAXOPEN=2 -CONFIG_EXAMPLES_FSTEST_MOUNTPT="/mnt/n25qxxx" -CONFIG_EXAMPLES_FSTEST_NLOOPS=1 -# CONFIG_EXAMPLES_FSTEST_VERBOSE is not set +# CONFIG_EXAMPLES_FSTEST is not set # CONFIG_EXAMPLES_FTPC is not set # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set @@ -895,6 +894,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set @@ -905,9 +905,11 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set # CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_UNIONFS is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set @@ -999,7 +1001,6 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFATFS is not set # CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set @@ -1038,6 +1039,15 @@ CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_DISABLESCRIPT is not set # CONFIG_NSH_DISABLE_ITEF is not set # CONFIG_NSH_DISABLE_LOOPS is not set +CONFIG_NSH_ROMFSETC=y +# CONFIG_NSH_ROMFSRC is not set +CONFIG_NSH_ROMFSMOUNTPT="/etc" +CONFIG_NSH_INITSCRIPT="init.d/rcS" +CONFIG_NSH_ROMFSDEVNO=0 +CONFIG_NSH_ROMFSSECTSIZE=64 +# CONFIG_NSH_DEFAULTROMFS is not set +CONFIG_NSH_ARCHROMFS=y +# CONFIG_NSH_CUSTOMROMFS is not set # # Console Configuration diff --git a/configs/stm32l476vg-disco/src/stm32_appinit.c b/configs/stm32l476vg-disco/src/stm32_appinit.c index 79cdbb9f3c2..ec485fa1f13 100644 --- a/configs/stm32l476vg-disco/src/stm32_appinit.c +++ b/configs/stm32l476vg-disco/src/stm32_appinit.c @@ -53,6 +53,7 @@ #include #include +#include #include #include @@ -308,3 +309,16 @@ int board_ioctl(unsigned int cmd, uintptr_t arg) return OK; } #endif + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == 0) + { + return -EINVAL; + } + + stm32l4_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/crypto/Makefile b/crypto/Makefile index c56640534ef..23b4cf137e9 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -1,7 +1,7 @@ ############################################################################ # crypto/Makefile # -# Copyright (C) 2007, 2008, 2011-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2008, 2011-2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -70,6 +70,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libcrypto$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/drivers/Makefile b/drivers/Makefile index 025444990f9..224cd78f6e5 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,7 +1,7 @@ ############################################################################ # drivers/Makefile # -# Copyright (C) 2007-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -108,6 +108,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libdrivers$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/drivers/can.c b/drivers/can.c index 4cca6c0dbb8..2454f06c2d3 100644 --- a/drivers/can.c +++ b/drivers/can.c @@ -522,6 +522,44 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer, /* Interrupts must be disabled while accessing the cd_recv FIFO */ flags = enter_critical_section(); + +#ifdef CONFIG_CAN_ERRORS + /* Check for internal errors */ + + if (dev->cd_error != 0) + { + FAR struct can_msg_s *msg; + + /* Detected an internal driver error. Generate a + * CAN_ERROR_MESSAGE + */ + + if (buflen < CAN_MSGLEN(CAN_ERROR_DLC)) + { + goto return_with_irqdisabled; + } + + msg = (FAR struct can_msg_s *)buffer; + msg->cm_hdr.ch_id = CAN_ERROR_INTERNAL; + msg->cm_hdr.ch_dlc = CAN_ERROR_DLC; + msg->cm_hdr.ch_rtr = 0; + msg->cm_hdr.ch_error = 1; +#ifdef CONFIG_CAN_EXTID + msg->cm_hdr.ch_extid = 0; +#endif + msg->cm_hdr.ch_unused = 0; + memset(&(msg->cm_data), 0, CAN_ERROR_DLC); + msg->cm_data[5] = dev->cd_error; + + /* Reset the error flag */ + + dev->cd_error = 0; + + ret = CAN_MSGLEN(CAN_ERROR_DLC); + goto return_with_irqdisabled; + } +#endif /* CONFIG_CAN_ERRORS */ + while (dev->cd_recv.rx_head == dev->cd_recv.rx_tail) { /* The receive FIFO is empty -- was non-blocking mode selected? */ @@ -540,6 +578,7 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer, ret = sem_wait(&dev->cd_recv.rx_sem); } while (ret >= 0 && dev->cd_recv.rx_head == dev->cd_recv.rx_tail); + dev->cd_nrxwaiters--; if (ret < 0) @@ -927,6 +966,9 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev) dev->cd_ntxwaiters = 0; dev->cd_nrxwaiters = 0; dev->cd_npendrtr = 0; +#ifdef CONFIG_CAN_ERRORS + dev->cd_error = 0; +#endif sem_init(&dev->cd_xmit.tx_sem, 0, 0); sem_init(&dev->cd_recv.rx_sem, 0, 0); @@ -1073,6 +1115,14 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr, err = OK; } +#ifdef CONFIG_CAN_ERRORS + else + { + /* Report rx overflow error */ + + dev->cd_error |= CAN_ERROR5_RXOVERFLOW; + } +#endif return err; } diff --git a/drivers/leds/userled_upper.c b/drivers/leds/userled_upper.c index 0d2377b624f..5c8f0a0997b 100644 --- a/drivers/leds/userled_upper.c +++ b/drivers/leds/userled_upper.c @@ -63,10 +63,10 @@ #ifndef CONFIG_DEBUG # undef CONFIG_DEBUG_VERBOSE -# undef CONFIG_DEBUG_DISCRETE +# undef CONFIG_DEBUG_LEDS #endif -#ifdef CONFIG_DEBUG_DISCRETE +#ifdef CONFIG_DEBUG_LEDS # define ddbg lldbg # ifdef CONFIG_DEBUG_VERBOSE # define dvdbg lldbg diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 3a3b8b77094..89f130ccb16 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -783,6 +783,39 @@ config SST25XX_MEMORY_TYPE endif # MTD_SST25XX +config MTD_SST26 + bool "SPI/QSPI-based SST26XX FLASHes (16,32,64-MBit)" + default n + select SPI + ---help--- + These part are also different from SST25 and SST25XX, they support both SPI and QSPI. + +if MTD_SST26 + +config SST26_SPIMODE + int "SST26 (Q)SPI Mode" + default 0 + +config SST26_SPIFREQUENCY + int "SST26 (Q)SPI Frequency" + default 64000000 + +config SST26_MANUFACTURER + hex "Manufacturers ID" + default 0xBF + ---help--- + Various manufacturers may have produced the parts. 0xBF is the manufacturer ID + for the parts manufactured by SST. + +config SST26_MEMORY_TYPE + hex "Memory type ID" + default 0x26 + ---help--- + The memory type for SST26VF0xx series is 0x26, but this can be modified if needed + to support compatible devices from different manufacturers. + +endif # MTD_SST26 + config MTD_SST39FV bool "SST39FV NOR FLASH" default n diff --git a/drivers/mtd/Make.defs b/drivers/mtd/Make.defs index a3a6eb7f20f..1d1ba6d26b7 100644 --- a/drivers/mtd/Make.defs +++ b/drivers/mtd/Make.defs @@ -88,6 +88,10 @@ ifeq ($(CONFIG_MTD_SST25XX),y) CSRCS += sst25xx.c endif +ifeq ($(CONFIG_MTD_SST26),y) +CSRCS += sst26.c +endif + ifeq ($(CONFIG_MTD_SST39FV),y) CSRCS += sst39vf.c endif diff --git a/drivers/mtd/sst26.c b/drivers/mtd/sst26.c new file mode 100644 index 00000000000..6790af73763 --- /dev/null +++ b/drivers/mtd/sst26.c @@ -0,0 +1,946 @@ +/************************************************************************************ + * drivers/mtd/sst26.c + * Driver for SPI-based or QSPI-based SST26VF parts of 32 or 64MBit. + * + * For smaller SST25 parts, use the sst25.c driver instead as support + * a different program mechanism (byte or word writing vs page writing + * supported in this driver). + * + * For SST25VF064, see sst25cxx.c driver instead. + * + * Copyright (C) 2009-2011, 2013, 2016 Gregory Nutt. All rights reserved. + * Author: Ken Pettit + * Author: Sebastien Lorquet + * + * Copied from / based on sst25.c driver written by + * Gregory Nutt + * Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* Per the data sheet, SST26 parts can be driven with either SPI mode 0 (CPOL=0 and + * CPHA=0) or mode 3 (CPOL=1 and CPHA=1). So you may need to specify + * CONFIG_SST26_SPIMODE to select the best mode for your device. If + * CONFIG_SST26_SPIMODE is not defined, mode 0 will be used. + */ + +#ifndef CONFIG_SST26_SPIMODE +# define CONFIG_SST26_SPIMODE SPIDEV_MODE0 +#endif + +/* SPI Frequency. May be up to 104 MHz. */ + +#ifndef CONFIG_SST26_SPIFREQUENCY +# define CONFIG_SST26_SPIFREQUENCY 20000000 +#endif + +/* Various manufacturers may have produced the parts. 0xBF is the manufacturer ID + * for the SST serial FLASH. + */ + +#ifndef CONFIG_SST26_MANUFACTURER +# define CONFIG_SST26_MANUFACTURER 0xBF +#endif + +#ifndef CONFIG_SST26_MEMORY_TYPE +# define CONFIG_SST26_MEMORY_TYPE 0x25 +#endif + +/* SST26 Registers *******************************************************************/ +/* Indentification register values */ + +#define SST26_MANUFACTURER CONFIG_SST26_MANUFACTURER +#define SST26_MEMORY_TYPE CONFIG_SST26_MEMORY_TYPE + +#define SST26_SST26VF016_CAPACITY 0x41 /* 16 M-bit */ +#define SST26_SST26VF032_CAPACITY 0x42 /* 32 M-bit */ +#define SST26_SST26VF064_CAPACITY 0x43 /* 64 M-bit */ + +/* SST26VF016 capacity is 2,097,152 bytes: + * (512 sectors) * (4,096 bytes per sector) + * (8192 pages) * (256 bytes per page) + */ + +#define SST26_SST26VF016_SECTOR_SHIFT 12 /* Sector size 1 << 15 = 65,536 */ +#define SST26_SST26VF016_NSECTORS 512 +#define SST26_SST26VF016_PAGE_SHIFT 8 /* Page size 1 << 8 = 256 */ +#define SST26_SST26VF016_NPAGES 8192 + +/* SST26VF032 capacity is 4,194,304 bytes: + * (1,024 sectors) * (4,096 bytes per sector) + * (16,384 pages) * (256 bytes per page) + */ + +#define SST26_SST26VF032_SECTOR_SHIFT 12 /* Sector size 1 << 15 = 65,536 */ +#define SST26_SST26VF032_NSECTORS 1024 +#define SST26_SST26VF032_PAGE_SHIFT 8 /* Page size 1 << 8 = 256 */ +#define SST26_SST26VF032_NPAGES 16384 + +/* SST26VF064 capacity is 8,388,608 bytes: + * (2,048 sectors) * (4,096 bytes per sector) + * (32,768 pages) * (256 bytes per page) + */ + +#define SST26_SST26VF064_SECTOR_SHIFT 12 /* Sector size 1 << 15 = 65,536 */ +#define SST26_SST26VF064_NSECTORS 2048 +#define SST26_SST26VF064_PAGE_SHIFT 8 /* Page size 1 << 8 = 256 */ +#define SST26_SST26VF064_NPAGES 32768 + +/* Instructions */ +/* Command Value NN Description Addr Dummy Data */ +#define SST26_NOP 0x00 /* 14 No Operation 0 0 0 */ +#define SST26_RSTEN 0x66 /* 14 Reset Enable 0 0 0 */ +#define SST26_RST 0x99 /* 14 Reset Memory 0 0 0 */ +#define SST26_EQIO 0x38 /* 1 Enable Quad I/O 0 0 0 */ +#define SST26_RSTQIO 0xFF /* 4 Reset Quad I/O 0 0 0 */ +#define SST26_RDSR 0x05 /* 1 Read Status Register 0 0 >=1 */ + /* 4 Read Status Register 0 1 >=1 */ +#define SST26_WRSR 0x01 /* 14 Write Status Register 0 0 2 */ +#define SST26_RDCR 0x35 /* 1 Read Config Register 0 0 >=1 */ + /* 4 Read Config Register 0 1 >=1 */ + +#define SST26_READ 0x03 /* 1 Read Data Bytes 3 0 >=1 */ +#define SST26_FAST_READ 0x0b /* 1 Higher speed read 3 1 >=1 */ + /* 4 Higher speed read 3 3 >=1 */ +#define SST26_SQOR 0x6b /* 1 SQI Output Read 3 1 >=1 */ +#define SST26_SQIOR 0xeb /* 1 SQI I/O Read 3 3 >=1 */ +#define SST26_SDOR 0x3b /* 1 SDI Output Read 3 1 >=1 */ +#define SST26_SDIOR 0xbb /* 1 SDI I/O Read 3 1 >=1 */ +#define SST26_SB 0xc0 /* 14 Set Burst Length 0 0 1 */ +#define SST26_RBSQI 0x0c /* 4 SQI Read Burst w/ Wrap 3 3 >=1 */ +#define SST26_RBSPI 0xec /* 1 SPI Read Burst w/ Wrap 3 3 >=1 */ + +#define SST26_RDID 0x9f /* 1 Read Identification 0 0 >=3 */ +#define SST26_QRDID 0xaf /* 4 Quad Read Identification 0 1 >=3 */ +#define SST26_SFDP 0x5a /* 1 Serial Flash Discov. Par. 3 1 >=1 */ + +#define SST26_WREN 0x06 /* 14 Write Enable 0 0 0 */ +#define SST26_WRDI 0x04 /* 14 Write Disable 0 0 0 */ +#define SST26_SE 0x20 /* 14 Sector Erase 3 0 0 */ +#define SST26_BE 0xd8 /* 14 8/32/64K Block Erase 3 0 0 */ +#define SST26_CE 0xc7 /* 14 Chip Erase 0 0 0 */ +#define SST26_PP 0x02 /* 1 Page Program 3 0 1-256 */ +#define SST26_QPP 0x32 /* 1 Quad Page Program 3 0 1-256 */ +#define SST26_WRSU 0xb0 /* 14 Suspend Program/Erase 0 0 0 */ +#define SST26_WRRE 0x30 /* 14 Resume Program/Erase 0 0 0 */ + +#define SST26_RBPR 0x72 /* 1 Read Block-Protection reg 0 0 1-18 */ + /* 4 Read Block-Protection reg 0 1 1-18 */ +#define SST26_WBPR 0x42 /* 14 Write Block-Protection reg 0 0 1-18 */ +#define SST26_LBPR 0x8d /* 14 Lock down Block-Prot. reg 0 0 0 */ +#define SST26_NVWLDR 0xe8 /* 14 non-Volatile Write L-D reg 0 0 1-18 */ +#define SST26_ULBPR 0x98 /* 14 Global Block Protection unlock 0 0 0 */ +#define SST26_RSID 0x88 /* 14 Read Security ID 2 1 1-2048*/ + /* 4 Read Security ID 2 3 1-2048*/ +#define SST26_PSID 0xa5 /* 14 Program User Security ID area 2 0 1-256 */ +#define SST26_LSID 0x85 /* 14 Lockout Security ID programming 0 0 0 */ + +/* NOTE 1: All parts. + * NOTE 2: In SST26VF064 terminology, 0xd8 is block erase and 0x20 + * is a sector erase. Block erase provides a faster way to erase + * multiple 4K sectors at once. + */ + +/* Status register bit definitions */ + +#define SST26_SR_WIP (1 << 0) /* Bit 0: Write in progress */ +#define SST26_SR_WEL (1 << 1) /* Bit 1: Write enable latch */ +#define SST26_SR_WSE (1 << 2) /* Bit 2: Write Suspend-Erase Status */ +#define SST26_SR_WSP (1 << 3) /* Bit 3: Write Suspend-Program Status */ +#define SST26_SR_WPLD (1 << 4) /* Bit 4: Write Protection Lock-Down Status */ +#define SST26_SR_SEC (1 << 5) /* Bit 5: Security ID status */ +#define SST26_SR_RES (1 << 6) /* Bit 6: RFU */ +#define SST26_SR_WIP2 (1 << 7) /* Bit 7: Write in progress */ + +#define SST26_DUMMY 0xa5 + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* This type represents the state of the MTD device. The struct mtd_dev_s + * must appear at the beginning of the definition so that you can freely + * cast between pointers to struct mtd_dev_s and struct sst26_dev_s. + */ + +struct sst26_dev_s +{ + struct mtd_dev_s mtd; /* MTD interface */ + FAR struct spi_dev_s *dev; /* Saved SPI interface instance */ + uint8_t sectorshift; + uint8_t pageshift; + uint16_t nsectors; + uint32_t npages; +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +/* Helpers */ + +static void sst26_lock(FAR struct spi_dev_s *dev); +static inline void sst26_unlock(FAR struct spi_dev_s *dev); +static inline int sst26_readid(struct sst26_dev_s *priv); +static void sst26_waitwritecomplete(struct sst26_dev_s *priv); +static void sst26_writeenable(struct sst26_dev_s *priv); +static void sst26_globalunlock(struct sst26_dev_s *priv); +static inline void sst26_sectorerase(struct sst26_dev_s *priv, off_t offset, uint8_t type); +static inline int sst26_chiperase(struct sst26_dev_s *priv); +static inline void sst26_pagewrite(struct sst26_dev_s *priv, FAR const uint8_t *buffer, + off_t offset); + +/* MTD driver methods */ + +static int sst26_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks); +static ssize_t sst26_bread(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR uint8_t *buf); +static ssize_t sst26_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR const uint8_t *buf); +static ssize_t sst26_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR uint8_t *buffer); +#ifdef CONFIG_MTD_BYTE_WRITE +static ssize_t sst26_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR const uint8_t *buffer); +#endif +static int sst26_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg); + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sst26_lock + ************************************************************************************/ + +static void sst26_lock(FAR struct spi_dev_s *dev) +{ + /* On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. + * + * This is a blocking call and will not return until we have exclusiv access to + * the SPI buss. We will retain that exclusive access until the bus is unlocked. + */ + + (void)SPI_LOCK(dev, true); + + /* After locking the SPI bus, the we also need call the setfrequency, setbits, and + * setmode methods to make sure that the SPI is properly configured for the device. + * If the SPI buss is being shared, then it may have been left in an incompatible + * state. + */ + + SPI_SETMODE(dev, CONFIG_SST26_SPIMODE); + SPI_SETBITS(dev, 8); + (void)SPI_HWFEATURES(dev, 0); + (void)SPI_SETFREQUENCY(dev, CONFIG_SST26_SPIFREQUENCY); +} + +/************************************************************************************ + * Name: sst26_unlock + ************************************************************************************/ + +static inline void sst26_unlock(FAR struct spi_dev_s *dev) +{ + (void)SPI_LOCK(dev, false); +} + +/************************************************************************************ + * Name: sst26_readid + ************************************************************************************/ + +static inline int sst26_readid(struct sst26_dev_s *priv) +{ + uint16_t manufacturer; + uint16_t memory; + uint16_t capacity; + + fvdbg("priv: %p\n", priv); + + /* Lock the SPI bus, configure the bus, and select this FLASH part. */ + + sst26_lock(priv->dev); + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send the "Read ID (RDID)" command and read the first three ID bytes */ + + (void)SPI_SEND(priv->dev, SST26_RDID); + manufacturer = SPI_SEND(priv->dev, SST26_DUMMY); + memory = SPI_SEND(priv->dev, SST26_DUMMY); + capacity = SPI_SEND(priv->dev, SST26_DUMMY); + + /* Deselect the FLASH and unlock the bus */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + sst26_unlock(priv->dev); + + lldbg("manufacturer: %02x memory: %02x capacity: %02x\n", + manufacturer, memory, capacity); + + /* Check for a valid manufacturer and memory type */ + + if (manufacturer == SST26_MANUFACTURER && memory == SST26_MEMORY_TYPE) + { + /* Okay.. is it a FLASH capacity that we understand? */ + + if (capacity == SST26_SST26VF064_CAPACITY) + { + /* Save the FLASH geometry */ + + priv->sectorshift = SST26_SST26VF064_SECTOR_SHIFT; + priv->nsectors = SST26_SST26VF064_NSECTORS; + priv->pageshift = SST26_SST26VF064_PAGE_SHIFT; + priv->npages = SST26_SST26VF064_NPAGES; + return OK; + } + else if (capacity == SST26_SST26VF032_CAPACITY) + { + /* Save the FLASH geometry */ + + priv->sectorshift = SST26_SST26VF032_SECTOR_SHIFT; + priv->nsectors = SST26_SST26VF032_NSECTORS; + priv->pageshift = SST26_SST26VF032_PAGE_SHIFT; + priv->npages = SST26_SST26VF032_NPAGES; + return OK; + } + } + + return -ENODEV; +} + +/************************************************************************************ + * Name: sst26_waitwritecomplete + ************************************************************************************/ + +static void sst26_waitwritecomplete(struct sst26_dev_s *priv) +{ + uint8_t status; + + /* Loop as long as the memory is busy with a write cycle */ + + do + { + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Read Status Register (RDSR)" command */ + + (void)SPI_SEND(priv->dev, SST26_RDSR); + + /* Send a dummy byte to generate the clock needed to shift out the status */ + + status = SPI_SEND(priv->dev, SST26_DUMMY); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + /* Given that writing could take up to few tens of milliseconds, and erasing + * could take more. The following short delay in the "busy" case will allow + * other peripherals to access the SPI bus. + */ + + if ((status & SST26_SR_WIP) != 0) + { + sst26_unlock(priv->dev); + usleep(1000); + sst26_lock(priv->dev); + } + } + while ((status & SST26_SR_WIP) != 0); + + fvdbg("Complete\n"); +} + +/************************************************************************************ + * Name: sst26_globalunlock + * Description: SST26 flashes are globally locked after startup. To allow writing, + * this command must be sent once. + ************************************************************************************/ + +static void sst26_globalunlock(struct sst26_dev_s *priv) +{ + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Write Enable (WREN)" command */ + + (void)SPI_SEND(priv->dev, SST26_ULBPR); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + fvdbg("Device unlocked.\n"); +} + +/************************************************************************************ + * Name: sst26_writeenable + ************************************************************************************/ + +static void sst26_writeenable(struct sst26_dev_s *priv) +{ + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Write Enable (WREN)" command */ + + (void)SPI_SEND(priv->dev, SST26_WREN); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + fvdbg("Enabled\n"); +} + +/************************************************************************************ + * Name: sst26_sectorerase (4k) + ************************************************************************************/ + +static void sst26_sectorerase(struct sst26_dev_s *priv, off_t sector, uint8_t type) +{ + off_t offset; + + offset = sector << priv->sectorshift; + + fvdbg("sector: %08lx\n", (long)sector); + + /* Send write enable instruction */ + + sst26_writeenable(priv); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send the "Sector Erase (SE)" or "Block Erase (BE)" instruction + * that was passed in as the erase type. + */ + + (void)SPI_SEND(priv->dev, type); + + /* Send the sector offset high byte first. For all of the supported + * parts, the sector number is completely contained in the first byte + * and the values used in the following two bytes don't really matter. + */ + + (void)SPI_SEND(priv->dev, (offset >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (offset >> 8) & 0xff); + (void)SPI_SEND(priv->dev, offset & 0xff); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + sst26_waitwritecomplete(priv); + + fvdbg("Erased\n"); +} + +/************************************************************************************ + * Name: sst26_chiperase + ************************************************************************************/ + +static inline int sst26_chiperase(struct sst26_dev_s *priv) +{ + fvdbg("priv: %p\n", priv); + + /* Send write enable instruction */ + + sst26_writeenable(priv); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send the "Chip Erase (CE)" instruction */ + + (void)SPI_SEND(priv->dev, SST26_CE); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + sst26_waitwritecomplete(priv); + + fvdbg("Return: OK\n"); + return OK; +} + +/************************************************************************************ + * Name: sst26_pagewrite + ************************************************************************************/ + +static inline void sst26_pagewrite(struct sst26_dev_s *priv, + FAR const uint8_t *buffer, off_t page) +{ + off_t offset = page << priv->pageshift; + + fvdbg("page: %08lx offset: %08lx\n", (long)page, (long)offset); + + /* Enable the write access to the FLASH */ + + sst26_writeenable(priv); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Page Program (PP)" command */ + + (void)SPI_SEND(priv->dev, SST26_PP); + + /* Send the page offset high byte first. */ + + (void)SPI_SEND(priv->dev, (offset >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (offset >> 8) & 0xff); + (void)SPI_SEND(priv->dev, offset & 0xff); + + /* Then write the specified number of bytes */ + + SPI_SNDBLOCK(priv->dev, buffer, 1 << priv->pageshift); + + /* Deselect the FLASH: Chip Select high */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + sst26_waitwritecomplete(priv); + + fvdbg("Written\n"); +} + +/************************************************************************************ + * Name: sst26_bytewrite + ************************************************************************************/ + +#ifdef CONFIG_MTD_BYTE_WRITE +static inline void sst26_bytewrite(struct sst26_dev_s *priv, + FAR const uint8_t *buffer, off_t offset, + uint16_t count) +{ + fvdbg("offset: %08lx count:%d\n", (long)offset, count); + + /* Enable the write access to the FLASH */ + + sst26_writeenable(priv); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Page Program (PP)" command */ + + (void)SPI_SEND(priv->dev, SST26_PP); + + /* Send the page offset high byte first. */ + + (void)SPI_SEND(priv->dev, (offset >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (offset >> 8) & 0xff); + (void)SPI_SEND(priv->dev, offset & 0xff); + + /* Then write the specified number of bytes */ + + SPI_SNDBLOCK(priv->dev, buffer, count); + priv->lastwaswrite = true; + + /* Deselect the FLASH: Chip Select high */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + + sst26_waitwritecomplete(priv); + + fvdbg("Written\n"); +} +#endif + +/* Driver routines */ + +/************************************************************************************ + * Name: sst26_erase + ************************************************************************************/ + +static int sst26_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks) +{ + FAR struct sst26_dev_s *priv = (FAR struct sst26_dev_s *)dev; + size_t blocksleft = nblocks; + + fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + /* Lock access to the SPI bus until we complete the erase */ + + sst26_lock(priv->dev); + while (blocksleft > 0) + { + /* SST26VF parts have complex block overlay structure for the moment + * we just erase in 4k blocks. + */ + + sst26_sectorerase(priv, startblock, SST26_SE); + startblock++; + blocksleft--; + } + + sst26_unlock(priv->dev); + return (int)nblocks; +} + +/************************************************************************************ + * Name: sst26_bread + ************************************************************************************/ + +static ssize_t sst26_bread(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR uint8_t *buffer) +{ + FAR struct sst26_dev_s *priv = (FAR struct sst26_dev_s *)dev; + ssize_t nbytes; + + fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + /* On this device, we can handle the block read just like the byte-oriented read */ + + nbytes = sst26_read(dev, startblock << priv->pageshift, nblocks << priv->pageshift, + buffer); + if (nbytes > 0) + { + return nbytes >> priv->pageshift; + } + + return (int)nbytes; +} + +/************************************************************************************ + * Name: sst26_bwrite + ************************************************************************************/ + +static ssize_t sst26_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, + FAR const uint8_t *buffer) +{ + FAR struct sst26_dev_s *priv = (FAR struct sst26_dev_s *)dev; + size_t blocksleft = nblocks; + size_t pagesize = 1 << priv->pageshift; + + fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + /* Lock the SPI bus and write each page to FLASH */ + + sst26_lock(priv->dev); + while (blocksleft-- > 0) + { + sst26_pagewrite(priv, buffer, startblock); + buffer += pagesize; + startblock++; + } + + sst26_unlock(priv->dev); + return nblocks; +} + +/************************************************************************************ + * Name: sst26_read + ************************************************************************************/ + +static ssize_t sst26_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR uint8_t *buffer) +{ + FAR struct sst26_dev_s *priv = (FAR struct sst26_dev_s *)dev; + + fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes); + + /* Lock the SPI bus and select this FLASH part */ + + sst26_lock(priv->dev); + SPI_SELECT(priv->dev, SPIDEV_FLASH, true); + + /* Send "Read from Memory " instruction */ + + (void)SPI_SEND(priv->dev, SST26_FAST_READ); + + /* Send the page offset high byte first. */ + + (void)SPI_SEND(priv->dev, (offset >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (offset >> 8) & 0xff); + (void)SPI_SEND(priv->dev, offset & 0xff); + + /* dummy read */ + (void)SPI_SEND(priv->dev, SST26_DUMMY); + + /* Then read all of the requested bytes */ + + SPI_RECVBLOCK(priv->dev, buffer, nbytes); + + /* Deselect the FLASH and unlock the SPI bus */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH, false); + sst26_unlock(priv->dev); + fvdbg("return nbytes: %d\n", (int)nbytes); + return nbytes; +} + +/************************************************************************************ + * Name: sst26_write + ************************************************************************************/ + +#ifdef CONFIG_MTD_BYTE_WRITE +static ssize_t sst26_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR const uint8_t *buffer) +{ + FAR struct sst26_dev_s *priv = (FAR struct sst26_dev_s *)dev; + int startpage; + int endpage; + int count; + int index; + int pagesize; + int bytestowrite; + + fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes); + + /* We must test if the offset + count crosses one or more pages + * and perform individual writes. The devices can only write in + * page increments. + */ + + startpage = offset / (1 << priv->pageshift); + endpage = (offset + nbytes) / (1 << priv->pageshift); + + if (startpage == endpage) + { + /* All bytes within one programmable page. Just do the write. */ + + sst26_bytewrite(priv, buffer, offset, nbytes); + } + else + { + /* Write the 1st partial-page */ + + count = nbytes; + pagesize = (1 << priv->pageshift); + bytestowrite = pagesize - (offset & (pagesize-1)); + sst26_bytewrite(priv, buffer, offset, bytestowrite); + + /* Update offset and count */ + + offset += bytestowrite; + count -= bytestowrite; + index = bytestowrite; + + /* Write full pages */ + + while (count >= pagesize) + { + sst26_bytewrite(priv, &buffer[index], offset, pagesize); + + /* Update offset and count */ + + offset += pagesize; + count -= pagesize; + index += pagesize; + } + + /* Now write any partial page at the end */ + + if (count > 0) + { + sst26_bytewrite(priv, &buffer[index], offset, count); + } + + priv->lastwaswrite = true; + } + + return nbytes; +} +#endif /* CONFIG_MTD_BYTE_WRITE */ + +/************************************************************************************ + * Name: sst26_ioctl + ************************************************************************************/ + +static int sst26_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) +{ + FAR struct sst26_dev_s *priv = (FAR struct sst26_dev_s *)dev; + int ret = -EINVAL; /* Assume good command with bad parameters */ + + fvdbg("cmd: %d \n", cmd); + + switch (cmd) + { + case MTDIOC_GEOMETRY: + { + FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg); + if (geo) + { + /* Populate the geometry structure with information need to know + * the capacity and how to access the device. + * + * NOTE: that the device is treated as though it where just an array + * of fixed size blocks. That is most likely not true, but the client + * will expect the device logic to do whatever is necessary to make it + * appear so. + */ + + geo->blocksize = (1 << priv->pageshift); + geo->erasesize = (1 << priv->sectorshift); + geo->neraseblocks = priv->nsectors; + + ret = OK; + + fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n", + geo->blocksize, geo->erasesize, geo->neraseblocks); + } + } + break; + + case MTDIOC_BULKERASE: + { + /* Erase the entire device */ + + sst26_lock(priv->dev); + ret = sst26_chiperase(priv); + sst26_unlock(priv->dev); + } + break; + + case MTDIOC_XIPBASE: + default: + ret = -ENOTTY; /* Bad command */ + break; + } + + fvdbg("return %d\n", ret); + return ret; +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sst26_initialize + * + * Description: + * Create an initialize MTD device instance. MTD devices are not registered + * in the file system, but are created as instances that can be bound to + * other functions (such as a block or character driver front end). + * + ************************************************************************************/ + +FAR struct mtd_dev_s *sst26_initialize_spi(FAR struct spi_dev_s *dev) +{ + FAR struct sst26_dev_s *priv; + int ret; + + fvdbg("dev: %p\n", dev); + + /* Allocate a state structure (we allocate the structure instead of using + * a fixed, static allocation so that we can handle multiple FLASH devices. + * The current implementation would handle only one FLASH part per SPI + * device (only because of the SPIDEV_FLASH definition) and so would have + * to be extended to handle multiple FLASH parts on the same SPI bus. + */ + + priv = (FAR struct sst26_dev_s *)kmm_zalloc(sizeof(struct sst26_dev_s)); + if (priv) + { + /* Initialize the allocated structure. (unsupported methods were + * nullified by kmm_zalloc). + */ + + priv->mtd.erase = sst26_erase; + priv->mtd.bread = sst26_bread; + priv->mtd.bwrite = sst26_bwrite; + priv->mtd.read = sst26_read; +#ifdef CONFIG_MTD_BYTE_WRITE + priv->mtd.write = sst26_write; +#endif + priv->mtd.ioctl = sst26_ioctl; + priv->dev = dev; + + /* Deselect the FLASH */ + + SPI_SELECT(dev, SPIDEV_FLASH, false); + + /* Identify the FLASH chip and get its capacity */ + + ret = sst26_readid(priv); + if (ret != OK) + { + /* Unrecognized! Discard all of that work we just did and return NULL */ + + fdbg("Unrecognized\n"); + kmm_free(priv); + priv = NULL; + } + else + { + /* Make sure that the FLASH is unprotected so that we can write into it */ + + sst26_globalunlock(priv); + +#ifdef CONFIG_MTD_REGISTRATION + /* Register the MTD with the procfs system if enabled */ + + mtd_register(&priv->mtd, "sst26"); +#endif + } + } + + /* Return the implementation-specific state structure as the MTD device */ + + fvdbg("Return %p\n", priv); + return (FAR struct mtd_dev_s *)priv; +} diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 8b8eb82564d..c7de1031a38 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -520,6 +520,7 @@ static inline void u16550_restoreuartint(FAR struct u16550_s *priv, uint32_t ier static inline void u16550_enablebreaks(FAR struct u16550_s *priv, bool enable) { uint32_t lcr = u16550_serialin(priv, UART_LCR_OFFSET); + if (enable) { lcr |= UART_LCR_BRK; @@ -528,6 +529,7 @@ static inline void u16550_enablebreaks(FAR struct u16550_s *priv, bool enable) { lcr &= ~UART_LCR_BRK; } + u16550_serialout(priv, UART_LCR_OFFSET, lcr); } diff --git a/fs/Kconfig b/fs/Kconfig index 8f25c3d43f8..150bbcdde99 100644 --- a/fs/Kconfig +++ b/fs/Kconfig @@ -43,10 +43,21 @@ config DISABLE_PSEUDOFS_OPERATIONS config FS_READABLE bool default n + ---help--- + Automatically selected if any readable file system is selected config FS_WRITABLE - bool + bool "Writable file system" default n + ---help--- + Automatically selected if any writable file system is selected. If + not selected, support for writing will be disabled in all block + drivers and also the block-to-character (BCH) layer and the MTD FTL + layer. + + This selection can also be manually selected. You might want to do + this if there are no writable file systems enabled, but you still + want support for write access in block drivers and/or FTL. source fs/aio/Kconfig source fs/semaphore/Kconfig diff --git a/fs/Makefile b/fs/Makefile index e60af07ae09..5ef45f84ee2 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -1,7 +1,7 @@ ############################################################################ # fs/Makefile # -# Copyright (C) 2007, 2008, 2011-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2008, 2011-2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -84,6 +84,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libfs$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/fs/mount/fs_mount.c b/fs/mount/fs_mount.c index 1fd2864c351..f3ab72bc933 100644 --- a/fs/mount/fs_mount.c +++ b/fs/mount/fs_mount.c @@ -103,9 +103,6 @@ extern const struct mountpt_operations fat_operations; #ifdef CONFIG_FS_ROMFS extern const struct mountpt_operations romfs_operations; #endif -#ifdef CONFIG_FS_TMPFS -extern const struct mountpt_operations tmpfs_operations; -#endif #ifdef CONFIG_FS_SMARTFS extern const struct mountpt_operations smartfs_operations; #endif @@ -129,6 +126,9 @@ static const struct fsmap_t g_bdfsmap[] = #ifdef CONFIG_FS_NXFFS extern const struct mountpt_operations nxffs_operations; #endif +#ifdef CONFIG_FS_TMPFS +extern const struct mountpt_operations tmpfs_operations; +#endif #ifdef CONFIG_NFS extern const struct mountpt_operations nfs_operations; #endif @@ -298,7 +298,7 @@ int mount(FAR const char *source, FAR const char *target, * incremented. */ - DEBUGASSERT(mountpt_inode->u.i_mops == NULL); + DEBUGASSERT(mountpt_inode->u.i_mops != NULL); } else #endif diff --git a/include/nuttx/can.h b/include/nuttx/can.h index 6f8b3d72aa9..573edd16b2b 100644 --- a/include/nuttx/can.h +++ b/include/nuttx/can.h @@ -219,7 +219,8 @@ # define CAN_ERROR_BUSOFF (1 << 6) /* Bit 6: Bus off */ # define CAN_ERROR_BUSERROR (1 << 7) /* Bit 7: Bus error */ # define CAN_ERROR_RESTARTED (1 << 8) /* Bit 8: Controller restarted */ - /* Bits 9-10: Available */ +# define CAN_ERROR_INTERNAL (1 << 9) /* Bit 9: Stack internal error (See CAN_ERROR5_* definitions) */ + /* Bit 10: Available */ /* The remaining definitions described the error report payload that follows the * CAN header. @@ -295,6 +296,11 @@ # define CANL_ERROR4_SHORT2GND 0x40 # define CANL_ERROR4_SHORT2CANH 0x50 +/* Data[5]: Error status of stack internals */ + +# define CAN_ERROR5_UNSPEC 0x00 /* Unspecified error */ +# define CAN_ERROR5_RXOVERFLOW (1 << 0) /* Bit 0: RX buffer overflow */ + #endif /* CONFIG_CAN_ERRORS */ /* CAN filter support ***************************************************************/ @@ -494,6 +500,9 @@ struct can_dev_s uint8_t cd_npendrtr; /* Number of pending RTR messages */ volatile uint8_t cd_ntxwaiters; /* Number of threads waiting to enqueue a message */ volatile uint8_t cd_nrxwaiters; /* Number of threads waiting to receive a message */ +#ifdef CONFIG_CAN_ERRORS + uint8_t cd_error; /* Flags to indicate internal device errors */ +#endif sem_t cd_closesem; /* Locks out new opens while close is in progress */ struct can_txfifo_s cd_xmit; /* Describes transmit FIFO */ struct can_rxfifo_s cd_recv; /* Describes receive FIFO */ diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h index 80b1c4215d4..8d1ee6db705 100644 --- a/include/nuttx/mtd/mtd.h +++ b/include/nuttx/mtd/mtd.h @@ -476,6 +476,18 @@ FAR struct mtd_dev_s *sst25_initialize(FAR struct spi_dev_s *dev); FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev); +/**************************************************************************** + * Name: sst26_initialize_spi + * + * Description: + * Initializes the driver for SPI-based SST26 FLASH + * + * Supports SST26VF016 SST26VF032 SST26VF064 + * + ****************************************************************************/ + +FAR struct mtd_dev_s *sst26_initialize_spi(FAR struct spi_dev_s *dev); + /**************************************************************************** * Name: sst39vf_initialize * diff --git a/lib/Makefile b/lib/Makefile index 58857dbd410..92a774d28a4 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -1,7 +1,7 @@ ############################################################################ # lib/Makefile # -# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -36,6 +36,7 @@ -include $(TOPDIR)/Make.defs all: +.PHONY: depend clean distclean depend: diff --git a/libxx/Makefile b/libxx/Makefile index 2fee7011865..02402dbf7db 100644 --- a/libxx/Makefile +++ b/libxx/Makefile @@ -1,7 +1,7 @@ ############################################################################ # libxx/Makefile # -# Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2009, 2012, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -88,6 +88,7 @@ OBJS = $(AOBJS) $(COBJS) $(CXXOBJS) BIN = libcxx$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/net/Makefile b/net/Makefile index 5cfc2349e28..2487ce96091 100644 --- a/net/Makefile +++ b/net/Makefile @@ -1,7 +1,7 @@ ############################################################################ # net/Makefile # -# Copyright (C) 2007, 2008, 2011-2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2008, 2011-2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -75,18 +75,19 @@ include procfs/Make.defs include utils/Make.defs endif -ASRCS = $(SOCK_ASRCS) $(NETDEV_ASRCS) $(NET_ASRCS) -AOBJS = $(ASRCS:.S=$(OBJEXT)) +ASRCS = $(SOCK_ASRCS) $(NETDEV_ASRCS) $(NET_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) -CSRCS = $(SOCK_CSRCS) $(NETDEV_CSRCS) $(NET_CSRCS) -COBJS = $(CSRCS:.c=$(OBJEXT)) +CSRCS = $(SOCK_CSRCS) $(NETDEV_CSRCS) $(NET_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) -SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) -BIN = libnet$(LIBEXT) +BIN = libnet$(LIBEXT) -all: $(BIN) +all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) diff --git a/tools/README.txt b/tools/README.txt index 55140d7fadc..44b0427427f 100644 --- a/tools/README.txt +++ b/tools/README.txt @@ -135,6 +135,12 @@ mkexport.sh and Makefile.export Makefile.export is used only by the mkexport.sh script to parse out options from the top-level Make.defs file. + USAGE: tools/mkexport.sh [-d] [-z] [-u] [-w|wy|wn] -t [-x ] -l "lib1 [lib2 [lib3 ...]]" + + Thais script also depends on the environment variable MAKE which is set + in the top-level Makefile before starting mkexport.sh. If MAKE is not + defined, the script will set it to `which make`. + mkfsdata.pl ----------- diff --git a/tools/mkconfig.c b/tools/mkconfig.c index 70160aa0bb5..710a0926e28 100644 --- a/tools/mkconfig.c +++ b/tools/mkconfig.c @@ -99,7 +99,9 @@ int main(int argc, char **argv, char **envp) printf("#ifndef __INCLUDE_NUTTX_CONFIG_H\n"); printf("#define __INCLUDE_NUTTX_CONFIG_H\n\n"); printf("/* Architecture-specific options *************************/\n\n"); + generate_definitions(stream); + printf("\n/* Sanity Checks *****************************************/\n\n"); printf("/* If this is an NXFLAT, external build, then make sure that\n"); printf(" * NXFLAT support is enabled in the base code.\n"); @@ -107,31 +109,36 @@ int main(int argc, char **argv, char **envp) printf("#if defined(__NXFLAT__) && !defined(CONFIG_NXFLAT)\n"); printf("# error \"NXFLAT support not enabled in this configuration\"\n"); printf("#endif\n\n"); + printf("/* NXFLAT requires PIC support in the TCBs. */\n\n"); printf("#if defined(CONFIG_NXFLAT)\n"); - printf("# undef CONFIG_PIC\n"); - printf("# define CONFIG_PIC 1\n"); + printf("# undef CONFIG_PIC\n"); + printf("# define CONFIG_PIC 1\n"); printf("#endif\n\n"); + printf("/* Binary format support is disabled if no binary formats are\n"); printf(" * configured (at present, NXFLAT is the only supported binary.\n"); printf(" * format).\n"); printf(" */\n\n"); printf("#if !defined(CONFIG_NXFLAT) && !defined(CONFIG_ELF) && !defined(CONFIG_BUILTIN)\n"); - printf("# undef CONFIG_BINFMT_DISABLE\n"); - printf("# define CONFIG_BINFMT_DISABLE 1\n"); + printf("# undef CONFIG_BINFMT_DISABLE\n"); + printf("# define CONFIG_BINFMT_DISABLE 1\n"); printf("#endif\n\n"); + printf("/* The correct way to disable RR scheduling is to set the\n"); printf(" * timeslice to zero.\n"); printf(" */\n\n"); printf("#ifndef CONFIG_RR_INTERVAL\n"); - printf("# define CONFIG_RR_INTERVAL 0\n"); + printf("# define CONFIG_RR_INTERVAL 0\n"); printf("#endif\n\n"); + printf("/* The correct way to disable filesystem supuport is to set the number of\n"); printf(" * file descriptors to zero.\n"); printf(" */\n\n"); printf("#ifndef CONFIG_NFILE_DESCRIPTORS\n"); - printf("# define CONFIG_NFILE_DESCRIPTORS 0\n"); + printf("# define CONFIG_NFILE_DESCRIPTORS 0\n"); printf("#endif\n\n"); + printf("/* If a console is selected, then make sure that there are resources for\n"); printf(" * three file descriptors and, if any streams are selected, also for three\n"); printf(" * file streams.\n"); @@ -156,131 +163,149 @@ int main(int argc, char **argv, char **envp) printf("# undef CONFIG_DEV_LOWCONSOLE\n"); printf("# undef CONFIG_RAMLOG_CONSOLE\n"); printf("#endif\n\n"); + printf("/* If priority inheritance is disabled, then do not allocate any\n"); printf(" * associated resources.\n"); printf(" */\n\n"); printf("#if !defined(CONFIG_PRIORITY_INHERITANCE) || !defined(CONFIG_SEM_PREALLOCHOLDERS)\n"); - printf("# undef CONFIG_SEM_PREALLOCHOLDERS\n"); - printf("# define CONFIG_SEM_PREALLOCHOLDERS 0\n"); + printf("# undef CONFIG_SEM_PREALLOCHOLDERS\n"); + printf("# define CONFIG_SEM_PREALLOCHOLDERS 0\n"); printf("#endif\n\n"); printf("#if !defined(CONFIG_PRIORITY_INHERITANCE) || !defined(CONFIG_SEM_NNESTPRIO)\n"); - printf("# undef CONFIG_SEM_NNESTPRIO\n"); - printf("# define CONFIG_SEM_NNESTPRIO 0\n"); + printf("# undef CONFIG_SEM_NNESTPRIO\n"); + printf("# define CONFIG_SEM_NNESTPRIO 0\n"); printf("#endif\n\n"); + printf("/* If no file descriptors are configured, then make certain no\n"); printf(" * streams are configured either.\n"); printf(" */\n\n"); printf("#if CONFIG_NFILE_DESCRIPTORS == 0\n"); - printf("# undef CONFIG_NFILE_STREAMS\n"); - printf("# define CONFIG_NFILE_STREAMS 0\n"); + printf("# undef CONFIG_NFILE_STREAMS\n"); + printf("# define CONFIG_NFILE_STREAMS 0\n"); printf("#endif\n\n"); + printf("/* There must be at least one memory region. */\n\n"); printf("#ifndef CONFIG_MM_REGIONS\n"); - printf("# define CONFIG_MM_REGIONS 1\n"); + printf("# define CONFIG_MM_REGIONS 1\n"); printf("#endif\n\n"); + printf("/* If the end of RAM is not specified then it is assumed to be the beginning\n"); printf(" * of RAM plus the RAM size.\n"); printf(" */\n\n"); printf("#ifndef CONFIG_RAM_END\n"); - printf("# define CONFIG_RAM_END (CONFIG_RAM_START+CONFIG_RAM_SIZE)\n"); + printf("# define CONFIG_RAM_END (CONFIG_RAM_START+CONFIG_RAM_SIZE)\n"); printf("#endif\n\n"); printf("#ifndef CONFIG_RAM_VEND\n"); - printf("# define CONFIG_RAM_VEND (CONFIG_RAM_VSTART+CONFIG_RAM_SIZE)\n"); + printf("# define CONFIG_RAM_VEND (CONFIG_RAM_VSTART+CONFIG_RAM_SIZE)\n"); printf("#endif\n\n"); + printf("/* If the end of FLASH is not specified then it is assumed to be the beginning\n"); printf(" * of FLASH plus the FLASH size.\n"); printf(" */\n\n"); printf("#ifndef CONFIG_FLASH_END\n"); - printf("# define CONFIG_FLASH_END (CONFIG_FLASH_START+CONFIG_FLASH_SIZE)\n"); + printf("# define CONFIG_FLASH_END (CONFIG_FLASH_START+CONFIG_FLASH_SIZE)\n"); printf("#endif\n\n"); + printf("/* If no file streams are configured, then make certain that buffered I/O\n"); printf(" * support is disabled\n"); printf(" */\n\n"); printf("#if CONFIG_NFILE_STREAMS == 0\n"); - printf("# undef CONFIG_STDIO_BUFFER_SIZE\n"); - printf("# define CONFIG_STDIO_BUFFER_SIZE 0\n"); + printf("# undef CONFIG_STDIO_BUFFER_SIZE\n"); + printf("# define CONFIG_STDIO_BUFFER_SIZE 0\n"); printf("#endif\n\n"); + printf("/* If no standard C buffered I/O is not supported, then line-oriented buffering\n"); printf(" * cannot be supported.\n"); printf(" */\n\n"); printf("#if CONFIG_STDIO_BUFFER_SIZE == 0\n"); - printf("# undef CONFIG_STDIO_LINEBUFFER\n"); + printf("# undef CONFIG_STDIO_LINEBUFFER\n"); printf("#endif\n\n"); + printf("/* If the maximum message size is zero, then we assume that message queues\n"); printf(" * support should be disabled\n"); printf(" */\n\n"); printf("#if !defined(CONFIG_MQ_MAXMSGSIZE) || defined(CONFIG_DISABLE_MQUEUE)\n"); - printf("# undef CONFIG_MQ_MAXMSGSIZE\n"); - printf("# define CONFIG_MQ_MAXMSGSIZE 0\n"); + printf("# undef CONFIG_MQ_MAXMSGSIZE\n"); + printf("# define CONFIG_MQ_MAXMSGSIZE 0\n"); printf("#endif\n\n"); printf("#if CONFIG_MQ_MAXMSGSIZE <= 0 && !defined(CONFIG_DISABLE_MQUEUE)\n"); - printf("# define CONFIG_DISABLE_MQUEUE 1\n"); + printf("# define CONFIG_DISABLE_MQUEUE 1\n"); printf("#endif\n\n"); + printf("/* If mountpoint support in not included, then no filesystem can be supported */\n\n"); printf("#ifdef CONFIG_DISABLE_MOUNTPOINT\n"); - printf("# undef CONFIG_FS_FAT\n"); - printf("# undef CONFIG_FS_ROMFS\n"); - printf("# undef CONFIG_FS_NXFFS\n"); - printf("# undef CONFIG_FS_SMARTFS\n"); - printf("# undef CONFIG_FS_BINFS\n"); - printf("# undef CONFIG_NFS\n"); - printf("#endif\n\n"); - printf("/* Check if any readable and writable filesystem (OR USB storage) is supported */\n\n"); - printf("#if defined(CONFIG_FS_FAT) || defined(CONFIG_FS_ROMFS) || defined(CONFIG_USBMSC) || \\\n"); - printf(" defined(CONFIG_FS_NXFFS) || defined(CONFIG_FS_SMARTFS) || defined(CONFIG_FS_BINFS) || \\\n"); - printf(" defined(CONFIG_NFS) || defined(CONFIG_FS_PROCFS)\n"); - printf("# undef CONFIG_FS_READABLE\n"); - printf("# define CONFIG_FS_READABLE 1\n"); - printf("#endif\n\n"); - printf("#if defined(CONFIG_FS_FAT) || defined(CONFIG_USBMSC) || defined(CONFIG_FS_NXFFS) || \\\n"); - printf(" defined(CONFIG_FS_SMARTFS) || defined(CONFIG_NFS)\n"); - printf("# undef CONFIG_FS_WRITABLE\n"); - printf("# define CONFIG_FS_WRITABLE 1\n"); + printf("# undef CONFIG_FS_BINFS\n"); + printf("# undef CONFIG_FS_FAT\n"); + printf("# undef CONFIG_FS_HOSTFS\n"); + printf("# undef CONFIG_NFS\n"); + printf("# undef CONFIG_FS_NXFFS\n"); + printf("# undef CONFIG_FS_PROCFS\n"); + printf("# undef CONFIG_FS_ROMFS\n"); + printf("# undef CONFIG_FS_SMARTFS\n"); + printf("# undef CONFIG_FS_TMPFS\n"); printf("#endif\n\n"); + printf("/* There can be no network support with no socket descriptors */\n\n"); printf("#if CONFIG_NSOCKET_DESCRIPTORS <= 0\n"); - printf("# undef CONFIG_NET\n"); + printf("# undef CONFIG_NET\n"); printf("#endif\n\n"); printf("/* Conversely, if there is no network support, there is no need for\n"); printf(" * socket descriptors\n"); printf(" */\n\n"); printf("#ifndef CONFIG_NET\n"); - printf("# undef CONFIG_NSOCKET_DESCRIPTORS\n"); - printf("# define CONFIG_NSOCKET_DESCRIPTORS 0\n"); + printf("# undef CONFIG_NSOCKET_DESCRIPTORS\n"); + printf("# define CONFIG_NSOCKET_DESCRIPTORS 0\n"); printf("#endif\n\n"); + printf("/* Protocol support can only be provided on top of basic network support */\n\n"); printf("#ifndef CONFIG_NET\n"); - printf("# undef CONFIG_NET_TCP\n"); - printf("# undef CONFIG_NET_UDP\n"); - printf("# undef CONFIG_NET_ICMP\n"); + printf("# undef CONFIG_NET_TCP\n"); + printf("# undef CONFIG_NET_UDP\n"); + printf("# undef CONFIG_NET_ICMP\n"); printf("#endif\n\n"); + printf("/* NFS client can only be provided on top of UDP network support */\n\n"); printf("#if !defined(CONFIG_NET) || !defined(CONFIG_NET_UDP)\n"); - printf("# undef CONFIG_NFS\n"); + printf("# undef CONFIG_NFS\n"); printf("#endif\n\n"); + printf("/* Verbose debug and sub-system debug only make sense if debug is enabled */\n\n"); printf("#ifndef CONFIG_DEBUG\n"); - printf("# undef CONFIG_DEBUG_VERBOSE\n"); - printf("# undef CONFIG_DEBUG_SCHED\n"); - printf("# undef CONFIG_DEBUG_MM\n"); - printf("# undef CONFIG_DEBUG_PAGING\n"); - printf("# undef CONFIG_DEBUG_DMA\n"); - printf("# undef CONFIG_DEBUG_FS\n"); - printf("# undef CONFIG_DEBUG_LIB\n"); - printf("# undef CONFIG_DEBUG_BINFMT\n"); - printf("# undef CONFIG_DEBUG_NET\n"); - printf("# undef CONFIG_DEBUG_USB\n"); - printf("# undef CONFIG_DEBUG_GRAPHICS\n"); - printf("# undef CONFIG_DEBUG_GPIO\n"); - printf("# undef CONFIG_DEBUG_SPI\n"); - printf("# undef CONFIG_DEBUG_HEAP\n"); - printf("#endif\n\n"); - printf("/* User entry point. This is provided as a fall-back to keep compatibility\n"); - printf(" * with existing code, for builds which do not define CONFIG_USER_ENTRYPOINT.\n"); - printf(" */\n\n"); - printf("#ifndef CONFIG_USER_ENTRYPOINT\n"); - printf("# define CONFIG_USER_ENTRYPOINT main\n"); + printf("# undef CONFIG_DEBUG_VERBOSE\n"); + printf("# undef CONFIG_DEBUG_ANALOG\n"); + printf("# undef CONFIG_DEBUG_AUDIO\n"); + printf("# undef CONFIG_DEBUG_BINFMT\n"); + printf("# undef CONFIG_DEBUG_CRYPTO\n"); + printf("# undef CONFIG_DEBUG_CAN\n"); + printf("# undef CONFIG_DEBUG_DMA\n"); + printf("# undef CONFIG_DEBUG_FS\n"); + printf("# undef CONFIG_DEBUG_GPIO\n"); + printf("# undef CONFIG_DEBUG_GRAPHICS\n"); + printf("# undef CONFIG_DEBUG_HEAP\n"); + printf("# undef CONFIG_DEBUG_I2C\n"); + printf("# undef CONFIG_DEBUG_I2S\n"); + printf("# undef CONFIG_DEBUG_INPUT\n"); + printf("# undef CONFIG_DEBUG_IRQ\n"); + printf("# undef CONFIG_DEBUG_LCD\n"); + printf("# undef CONFIG_DEBUG_LEDS\n"); + printf("# undef CONFIG_DEBUG_LIB\n"); + printf("# undef CONFIG_DEBUG_MM\n"); + printf("# undef CONFIG_DEBUG_NET\n"); + printf("# undef CONFIG_DEBUG_PAGING\n"); + printf("# undef CONFIG_DEBUG_PWM\n"); + printf("# undef CONFIG_DEBUG_RTC\n"); + printf("# undef CONFIG_DEBUG_SCHED\n"); + printf("# undef CONFIG_DEBUG_SDIO\n"); + printf("# undef CONFIG_DEBUG_SENSORS\n"); + printf("# undef CONFIG_DEBUG_SHM\n"); + printf("# undef CONFIG_DEBUG_SPI\n"); + printf("# undef CONFIG_DEBUG_SYSCALL\n"); + printf("# undef CONFIG_DEBUG_TIMER\n"); + printf("# undef CONFIG_DEBUG_USB\n"); + printf("# undef CONFIG_DEBUG_WATCHDOG\n"); + printf("# undef CONFIG_DEBUG_WIRELESS\n"); printf("#endif\n\n"); + printf("#endif /* __INCLUDE_NUTTX_CONFIG_H */\n"); fclose(stream); diff --git a/tools/mkexport.sh b/tools/mkexport.sh index 37a78394bd1..348a14cf5c5 100755 --- a/tools/mkexport.sh +++ b/tools/mkexport.sh @@ -1,7 +1,7 @@ #!/bin/bash # tools/mkexport.sh # -# Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -115,6 +115,12 @@ if [ ! -f "${TOPDIR}/.version" ]; then exit 1 fi +# Check if the make environment variable has been defined + +if [ -z "${MAKE}" ]; then + MAKE=`which make` +fi + # Get the version string source "${TOPDIR}/.version" @@ -162,7 +168,7 @@ grep -v "WINTOOL[ \t]*=[ \t]y" "${TOPDIR}/Make.defs" > "${EXPORTDIR}/Make.defs" # Extract information from the Make.defs file. A Makefile can do this best -make -C "${TOPDIR}/tools" -f Makefile.export TOPDIR="${TOPDIR}" EXPORTDIR="${EXPORTDIR}" +${MAKE} -C "${TOPDIR}/tools" -f Makefile.export TOPDIR="${TOPDIR}" EXPORTDIR="${EXPORTDIR}" source "${EXPORTDIR}/makeinfo.sh" rm -f "${EXPORTDIR}/makeinfo.sh" rm -f "${EXPORTDIR}/Make.defs" @@ -236,7 +242,7 @@ cp -LR -p "${TOPDIR}/include" "${EXPORTDIR}/." || \ # Copy the startup object file(s) -make -C ${ARCHDIR} export_startup TOPDIR=${TOPDIR} EXPORT_DIR="${EXPORTDIR}" +${MAKE} -C ${ARCHDIR} export_startup TOPDIR=${TOPDIR} EXPORT_DIR="${EXPORTDIR}" # Copy architecture-specific header files into the arch export sub-directory. # This is tricky because each architecture does things in a little different diff --git a/wireless/Makefile b/wireless/Makefile index 85f69bd118f..008d23ff1c8 100644 --- a/wireless/Makefile +++ b/wireless/Makefile @@ -69,6 +69,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libwireless$(LIBEXT) all: $(BIN) +.PHONY: depend clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@)