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stm32 f72xx and f73xx: Add register definition header files and clocking logic
This commit is contained in:
Bob Feretich
committed by
Gregory Nutt
Gregory Nutt
parent
4f0c4b798f
commit
13b52da3fa
@@ -0,0 +1,198 @@
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/****************************************************************************************************
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* arch/arm/include/stm32f7/stm32f72xx73xx_irq.h.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Bob Feretich <bob.feretich@rafresearch.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*Change Record:
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* bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the
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* exclusions noted by this tag, and the addition of the last IRQ
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* for SDMMC2 (IRQ103).
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****************************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
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#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
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* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
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* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
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*
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* External interrupts (vectors >= 16)
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
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#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
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#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
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#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
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#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
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#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
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#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
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#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
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#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
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#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
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#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
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#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
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#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
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#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
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#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
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#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
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#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
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#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
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#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
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#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
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#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
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#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
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#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
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#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
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#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
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#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
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#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
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#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
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#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
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#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
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#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
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#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
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#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
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#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
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#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
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#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI */
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#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
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#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
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#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
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#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
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#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
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#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
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#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
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#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
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#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
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#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
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#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
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#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
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#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
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#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
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#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
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#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
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#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
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#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
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#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
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#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
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#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
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#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
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#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
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#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
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#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
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#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
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#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
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#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
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#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
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#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
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#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
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#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
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#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
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#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
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#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
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#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
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#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
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#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
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#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
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#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
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#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
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#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
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#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
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#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
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#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
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#define NR_INTERRUPTS 103
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#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
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/* EXTI interrupts (Do not use IRQ numbers) */
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#define NR_IRQS NR_VECTORS
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H */
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@@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_dbgmcu.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -44,7 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# include "chip/stm32f72xx73xx_dbgmcu.h"
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_dbgmcu.h"
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "chip/stm32f76xx77xx_dbgmcu.h"
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_dma.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -44,7 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# include "chip/stm32f72xx73xx_dma.h"
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_dma.h"
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "chip/stm32f76xx77xx_dma.h"
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_flash.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -44,7 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# include "chip/stm32f72xx73xx_flash.h"
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_flash.h"
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "chip/stm32f76xx77xx_flash.h"
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_gpio.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -44,7 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# include "chip/stm32f72xx73xx_gpio.h"
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_gpio.h"
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "chip/stm32f76xx77xx_gpio.h"
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_memorymap.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -44,7 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
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# include "chip/stm32f72xx73xx_memorymap.h"
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#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "chip/stm32f74xx75xx_memorymap.h"
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# include "chip/stm32f76xx77xx_memorymap.h"
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_pinmap.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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@@ -44,7 +44,9 @@
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#include <nuttx/config.h>
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#include "chip.h"
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|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_pinmap.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_pinmap.h"
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_pwr.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
@@ -44,7 +44,9 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_pwr.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_pwr.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_pwr.h"
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_rcc.h
|
||||
*
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
@@ -43,7 +44,9 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_rcc.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_rcc.h"
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
@@ -44,7 +44,9 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_syscfg.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_syscfg.h"
|
||||
|
||||
@@ -44,7 +44,9 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_tim.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "chip/stm32f74xx75xx_tim.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f76xx77xx_tim.h"
|
||||
|
||||
@@ -44,7 +44,9 @@
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_uart.h"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "chip/stm32f74xx77xx_uart.h"
|
||||
#else
|
||||
|
||||
@@ -0,0 +1,108 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XXDBGMCU_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XXDBGMCU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */
|
||||
#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */
|
||||
#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */
|
||||
#define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* MCU identifier */
|
||||
|
||||
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
|
||||
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
|
||||
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
|
||||
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
|
||||
|
||||
/* MCU debug */
|
||||
|
||||
#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */
|
||||
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */
|
||||
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */
|
||||
#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */
|
||||
|
||||
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignement */
|
||||
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
|
||||
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
|
||||
|
||||
/* Debug MCU APB1 freeze register */
|
||||
|
||||
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */
|
||||
#define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 8: TIM14 stopped when core is halted */
|
||||
#define DBGMCU_APB1_LPTIM1STOP (1 << 9) /* Bit 9: LPTIM1 stopped when core is halted */
|
||||
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
|
||||
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
|
||||
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
|
||||
#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
|
||||
|
||||
/* Debug MCU APB2 freeze register */
|
||||
|
||||
#define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */
|
||||
#define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX74XXDBGMCU_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,212 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h
|
||||
*
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F72XX73XX_FLASH_H
|
||||
#define __ARCH_ARM_SRC_STM327_CHIP_STM32F72XX73XX_FLASH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Flash size is known from the chip selection:
|
||||
*
|
||||
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
|
||||
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip
|
||||
* part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
|
||||
*
|
||||
* Parts STM32F72xxC have 256Kb of FLASH
|
||||
* Parts STM32F72xxE have 512Kb of FLASH
|
||||
* Parts STM32F73xxC have 256Kb of FLASH
|
||||
* Parts STM32F73xxE have 512Kb of FLASH
|
||||
*
|
||||
* N.B. Only Single bank mode is supported
|
||||
*/
|
||||
|
||||
#define _K(x) ((x)*1024)
|
||||
|
||||
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
|
||||
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \
|
||||
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \
|
||||
!defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \
|
||||
!defined(CONFIG_STM32F7_FLASH_CONFIG_C)
|
||||
# define CONFIG_STM32F7_FLASH_OVERRIDE_C
|
||||
# warning "Flash size not defined defaulting to 256KiB (C)"
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT)
|
||||
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_C
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_E
|
||||
# undef CONFIG_STM32F7_FLASH_CONFIG_G
|
||||
|
||||
# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C)
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_C
|
||||
|
||||
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E)
|
||||
# define CONFIG_STM32F7_FLASH_CONFIG_E
|
||||
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_FLASH_CONFIG_C)
|
||||
|
||||
# define STM32_FLASH_NPAGES 6
|
||||
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128))
|
||||
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
|
||||
_K(64), _K(128)}
|
||||
|
||||
#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E)
|
||||
|
||||
# define STM32_FLASH_NPAGES 8
|
||||
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128))
|
||||
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
|
||||
_K(64), _K(128), _K(128), _K(128)}
|
||||
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_SR_OFFSET 0x000c
|
||||
#define STM32_FLASH_CR_OFFSET 0x0010
|
||||
#define STM32_FLASH_OPTCR_OFFSET 0x0014
|
||||
#define STM32_FLASH_OPTCR1_OFFSET 0x0018
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
|
||||
#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */
|
||||
#define FLASH_ACR_LATENCY_MASK (15 << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
|
||||
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
|
||||
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
|
||||
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
|
||||
# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
|
||||
# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
|
||||
# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */
|
||||
# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
|
||||
# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */
|
||||
# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
|
||||
# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
|
||||
# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
|
||||
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */
|
||||
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */
|
||||
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
|
||||
#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
|
||||
#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */
|
||||
#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
|
||||
#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
|
||||
#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
|
||||
#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
|
||||
#define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */
|
||||
#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
|
||||
#define FLASH_SR_PGRERR (1 << 7) /* Bit 7: PCROP protection error */
|
||||
#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
|
||||
|
||||
/* Flash Control Register (CR) */
|
||||
|
||||
#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
|
||||
#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
|
||||
#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
|
||||
#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
|
||||
#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
|
||||
# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT)) /* Sector n, n=0..7 */
|
||||
#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
|
||||
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
|
||||
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */
|
||||
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */
|
||||
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */
|
||||
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */
|
||||
#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
|
||||
#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
|
||||
#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
|
||||
#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP error interrupt enable */
|
||||
#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
|
||||
|
||||
/* Flash Option Control Register (OPTCR) */
|
||||
|
||||
#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
|
||||
#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
|
||||
#define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */
|
||||
#define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT)
|
||||
# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 3 */
|
||||
# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */
|
||||
# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */
|
||||
# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */
|
||||
#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */
|
||||
#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT)
|
||||
# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */
|
||||
# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */
|
||||
# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */
|
||||
# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */
|
||||
#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */
|
||||
#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT)
|
||||
# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT)
|
||||
#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-23: Not write protect */
|
||||
#define FLASH_OPTCR_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT)
|
||||
# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT)
|
||||
#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */
|
||||
#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */
|
||||
|
||||
/* Flash Option Control Register (OPTCR1) */
|
||||
|
||||
#define FLASH_OPTCR1_BOOTADD0_SHIFT (0) /* Bits 0-15: Boot base address when Boot pin=0 */
|
||||
#define FLASH_OPTCR1_BOOTADD0_MASK (0xffff << FLASH_OPTCR1_BOOTADD0_SHIFT)
|
||||
# define FLASH_OPTCR1_BOOTADD0(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD0_SHIFT)
|
||||
#define FLASH_OPTCR1_BOOTADD1_SHIFT (16) /* Bits 16-31:Boot base address when Boot pin=1 */
|
||||
#define FLASH_OPTCR1_BOOTADD1_MASK (0xffff << FLASH_OPTCR1_BOOTADD1_SHIFT)
|
||||
# define FLASH_OPTCR1_BOOTADD1(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD1_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32F72XX73XX_FLASH_H */
|
||||
@@ -0,0 +1,404 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f72xxx73xx_gpio.h
|
||||
*
|
||||
* Copyright (C) 2005 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/stm32f7/chip.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NGPIO > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPI O_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 6
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 7
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 8
|
||||
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 9
|
||||
# define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOJ_PUPDR (STM32_GPIOJ_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOJ_IDR (STM32_GPIOJ_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOJ_ODR (STM32_GPIOJ_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOJ_BSRR (STM32_GPIOJ_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NGPIO > 10
|
||||
# define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOK_PUPDR (STM32_GPIOK_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOK_IDR (STM32_GPIOK_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOK_ODR (STM32_GPIOK_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOK_BSRR (STM32_GPIOK_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* GPIO port mode register */
|
||||
|
||||
#define GPIO_MODER_INPUT (0) /* Input */
|
||||
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
|
||||
#define GPIO_MODER_ALT (2) /* Alternate mode */
|
||||
#define GPIO_MODER_ANALOG (3) /* Analog mode */
|
||||
|
||||
#define GPIO_MODER_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
|
||||
|
||||
#define GPIO_MODER0_SHIFT (0)
|
||||
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
|
||||
#define GPIO_MODER1_SHIFT (2)
|
||||
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
|
||||
#define GPIO_MODER2_SHIFT (4)
|
||||
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
|
||||
#define GPIO_MODER3_SHIFT (6)
|
||||
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
|
||||
#define GPIO_MODER4_SHIFT (8)
|
||||
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
|
||||
#define GPIO_MODER5_SHIFT (10)
|
||||
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
|
||||
#define GPIO_MODER6_SHIFT (12)
|
||||
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
|
||||
#define GPIO_MODER7_SHIFT (14)
|
||||
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
|
||||
#define GPIO_MODER8_SHIFT (16)
|
||||
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
|
||||
#define GPIO_MODER9_SHIFT (18)
|
||||
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
|
||||
#define GPIO_MODER10_SHIFT (20)
|
||||
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
|
||||
#define GPIO_MODER11_SHIFT (22)
|
||||
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
|
||||
#define GPIO_MODER12_SHIFT (24)
|
||||
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
|
||||
#define GPIO_MODER13_SHIFT (26)
|
||||
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
|
||||
#define GPIO_MODER14_SHIFT (28)
|
||||
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
|
||||
#define GPIO_MODER15_SHIFT (30)
|
||||
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
|
||||
|
||||
/* GPIO port output type register */
|
||||
|
||||
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
|
||||
#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */
|
||||
|
||||
/* GPIO port output speed register */
|
||||
|
||||
#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */
|
||||
#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */
|
||||
#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */
|
||||
#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */
|
||||
|
||||
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
|
||||
|
||||
#define GPIO_OSPEED0_SHIFT (0)
|
||||
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
|
||||
#define GPIO_OSPEED1_SHIFT (2)
|
||||
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
|
||||
#define GPIO_OSPEED2_SHIFT (4)
|
||||
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
|
||||
#define GPIO_OSPEED3_SHIFT (6)
|
||||
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
|
||||
#define GPIO_OSPEED4_SHIFT (8)
|
||||
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
|
||||
#define GPIO_OSPEED5_SHIFT (10)
|
||||
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
|
||||
#define GPIO_OSPEED6_SHIFT (12)
|
||||
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
|
||||
#define GPIO_OSPEED7_SHIFT (14)
|
||||
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
|
||||
#define GPIO_OSPEED8_SHIFT (16)
|
||||
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
|
||||
#define GPIO_OSPEED9_SHIFT (18)
|
||||
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
|
||||
#define GPIO_OSPEED10_SHIFT (20)
|
||||
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
|
||||
#define GPIO_OSPEED11_SHIFT (22)
|
||||
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
|
||||
#define GPIO_OSPEED12_SHIFT (24)
|
||||
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
|
||||
#define GPIO_OSPEED13_SHIFT (26)
|
||||
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
|
||||
#define GPIO_OSPEED14_SHIFT (28)
|
||||
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
|
||||
#define GPIO_OSPEED15_SHIFT (30)
|
||||
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
|
||||
|
||||
/* GPIO port pull-up/pull-down register */
|
||||
|
||||
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
|
||||
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
|
||||
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
|
||||
|
||||
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
|
||||
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
|
||||
|
||||
#define GPIO_PUPDR0_SHIFT (0)
|
||||
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
|
||||
#define GPIO_PUPDR1_SHIFT (2)
|
||||
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
|
||||
#define GPIO_PUPDR2_SHIFT (4)
|
||||
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
|
||||
#define GPIO_PUPDR3_SHIFT (6)
|
||||
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
|
||||
#define GPIO_PUPDR4_SHIFT (8)
|
||||
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
|
||||
#define GPIO_PUPDR5_SHIFT (10)
|
||||
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
|
||||
#define GPIO_PUPDR6_SHIFT (12)
|
||||
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
|
||||
#define GPIO_PUPDR7_SHIFT (14)
|
||||
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
|
||||
#define GPIO_PUPDR8_SHIFT (16)
|
||||
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
|
||||
#define GPIO_PUPDR9_SHIFT (18)
|
||||
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
|
||||
#define GPIO_PUPDR10_SHIFT (20)
|
||||
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
|
||||
#define GPIO_PUPDR11_SHIFT (22)
|
||||
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
|
||||
#define GPIO_PUPDR12_SHIFT (24)
|
||||
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
|
||||
#define GPIO_PUPDR13_SHIFT (26)
|
||||
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
|
||||
#define GPIO_PUPDR14_SHIFT (28)
|
||||
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
|
||||
#define GPIO_PUPDR15_SHIFT (30)
|
||||
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
|
||||
|
||||
/* GPIO port input data register */
|
||||
|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H */
|
||||
@@ -0,0 +1,202 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/chip/stm32f72xx73xx_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XXX_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XXX_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* STM32F72XX STM32F73XX Address Blocks *********************************************/
|
||||
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */
|
||||
#define STM32_FMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FMC bank1&2 block */
|
||||
# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
# define STM32_FMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
|
||||
#define STM32_FMC_BASE34 0x80000000 /* 0x80000000-0x9fffffff: 512Mb FMC bank3&4 block */
|
||||
# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32_FMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */
|
||||
#define STM32_FMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC SDRAM Bank 1 */
|
||||
#define STM32_FMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC SDRAM Bank 2 */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */
|
||||
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1)
|
||||
|
||||
/* Code Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
#define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */
|
||||
#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */
|
||||
#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */
|
||||
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */
|
||||
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
|
||||
|
||||
/* Information Addresses ************************************************************/
|
||||
|
||||
#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff076D7: System memory (AXIM) */
|
||||
#define STM32_SYSMEM_UID 0x1ff07A10 /* The 96-bit unique device identifier */
|
||||
#define STM32_OTP_ICTM 0x00107800 /* 0x00107800-0x00107A0F: OTP (ITCM) */
|
||||
#define STM32_OTP_AXIM 0x1ff07800 /* 0x1ff07800-0x1ff07A0F: OTP (AXIM) */
|
||||
|
||||
/* SRAM Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2000ffff: DTCM-RAM on TCM interface */
|
||||
#define STM32_SRAM1_BASE 0x20010000 /* 0x20010000-0x2003bfff: System SRAM1 */
|
||||
#define STM32_SRAM2_BASE 0x2003C000 /* 0x2003c000-0x2003ffff: System SRAM2 */
|
||||
|
||||
/* Peripheral Base Addresses ********************************************************/
|
||||
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */
|
||||
#define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x50060bff: AHB2 */
|
||||
#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */
|
||||
|
||||
/* APB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */
|
||||
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff: TIM4 */
|
||||
#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00-0x40000fff: TIM5 */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff: TIM6 */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff: TIM7 */
|
||||
#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff: TIM12 */
|
||||
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 */
|
||||
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
|
||||
#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
|
||||
#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
|
||||
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
|
||||
#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
|
||||
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */
|
||||
#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff: USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff: USART3 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff: UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff: UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff: I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff: I2C2 */
|
||||
#define STM32_I2C3_BASE 0x40005c00 /* 0x40005c00-0x40005fff: I2C3 */
|
||||
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: CAN1 */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: PWR */
|
||||
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */
|
||||
#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */
|
||||
#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */
|
||||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */
|
||||
#define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */
|
||||
#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */
|
||||
#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */
|
||||
#define STM32_SDMMC2_BASE 0x40011C00 /* 0x4001C000-0x40011fff: SDMMC2 */
|
||||
#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */
|
||||
# define STM32_ADC1_BASE 0x40012000 /* ADC1 */
|
||||
# define STM32_ADC2_BASE 0x40012100 /* ADC2 */
|
||||
# define STM32_ADC3_BASE 0x40012200 /* ADC3 */
|
||||
# define STM32_ADCCMN_BASE 0x40012300 /* Common */
|
||||
#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */
|
||||
#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */
|
||||
#define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */
|
||||
#define STM32_EXTI_BASE 0x40013c00 /* 0x40013c00-0x40013fff: EXTI */
|
||||
#define STM32_TIM9_BASE 0x40014000 /* 0x40014000-0x400143ff: TIM9 */
|
||||
#define STM32_TIM10_BASE 0x40014400 /* 0x40014400-0x400147ff: TIM10 */
|
||||
#define STM32_TIM11_BASE 0x40014800 /* 0x40014800-0x40014bff: TIM11 */
|
||||
#define STM32_SPI5_BASE 0x40015000 /* 0x40015000-0x400153ff: SPI5 */
|
||||
#define STM32_SAI1_BASE 0x40015800 /* 0x40015800-0x40015bff: SAI1 */
|
||||
#define STM32_SAI2_BASE 0x40015c00 /* 0x40015c00-0x40015fff: SAI2 */
|
||||
#define STM32_OTGPHY_BASE 0x40017c00 /* 0x40017C00-0x40017fff: OTG PHY HS */
|
||||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */
|
||||
#define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */
|
||||
#define STM32_GPIOC_BASE 0x40020800 /* 0x40020800-0x40020bff: GPIOC */
|
||||
#define STM32_GPIOD_BASE 0x40020c00 /* 0x40020c00-0x40020fff: GPIOD */
|
||||
#define STM32_GPIOE_BASE 0x40021000 /* 0x40021000-0x400213ff: GPIOE */
|
||||
#define STM32_GPIOF_BASE 0x40021400 /* 0x40021400-0x400217ff: GPIOF */
|
||||
#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIOG */
|
||||
#define STM32_GPIOH_BASE 0x40021c00 /* 0x40021c00-0x40021fff: GPIOH */
|
||||
#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIOI */
|
||||
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
|
||||
#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */
|
||||
#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash interface */
|
||||
#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: BKPSRAM */
|
||||
#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */
|
||||
#define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */
|
||||
|
||||
/* AHB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */
|
||||
#define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */
|
||||
|
||||
/* AHB3 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */
|
||||
#define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */
|
||||
#define STM32_FMCBANK3_BASE 0x80000000 /* 0x80000000-0x8fffffff: FMC bank 3 */
|
||||
#define STM32_FMCBANK4_BASE 0x90000000 /* 0x90000000-0x9fffffff: FMC bank 4 */
|
||||
#define STM32_FMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */
|
||||
#define STM32_QUADSPI_BASE 0xa0001000 /* 0xa0001000-0xa0001fff: QuadSPI Control */
|
||||
#define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */
|
||||
#define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */
|
||||
|
||||
/* Cortex-M7 Base Addresses *********************************************************/
|
||||
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
|
||||
* address range */
|
||||
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_MEMORYMAP_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,161 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h
|
||||
*
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */
|
||||
#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Power control register 1 */
|
||||
|
||||
#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */
|
||||
#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */
|
||||
#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */
|
||||
#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */
|
||||
#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */
|
||||
#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT)
|
||||
# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */
|
||||
# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */
|
||||
# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */
|
||||
# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */
|
||||
# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */
|
||||
# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */
|
||||
# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */
|
||||
# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */
|
||||
#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */
|
||||
#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
|
||||
#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */
|
||||
#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */
|
||||
#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */
|
||||
#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */
|
||||
#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT)
|
||||
# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */
|
||||
# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */
|
||||
# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */
|
||||
#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */
|
||||
#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */
|
||||
#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */
|
||||
#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT)
|
||||
# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */
|
||||
# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */
|
||||
|
||||
/* Power control/status register 1 */
|
||||
|
||||
#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */
|
||||
#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */
|
||||
#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */
|
||||
#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */
|
||||
#define PWR_CSR1_EIWUP (1 << 8) /* Bit 8: Enable internal wakeup */
|
||||
#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */
|
||||
#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
|
||||
#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */
|
||||
#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */
|
||||
#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */
|
||||
#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT)
|
||||
# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */
|
||||
# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */
|
||||
|
||||
/* Power control register 2 */
|
||||
|
||||
#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */
|
||||
#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */
|
||||
#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */
|
||||
#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */
|
||||
#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */
|
||||
#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */
|
||||
#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */
|
||||
# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */
|
||||
# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */
|
||||
# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */
|
||||
# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */
|
||||
# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */
|
||||
#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */
|
||||
# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */
|
||||
# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */
|
||||
|
||||
/* Power control/status register 2 */
|
||||
|
||||
#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */
|
||||
#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */
|
||||
#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */
|
||||
#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */
|
||||
#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */
|
||||
#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */
|
||||
#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */
|
||||
#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */
|
||||
#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */
|
||||
#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */
|
||||
#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
|
||||
#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f72xx74xx_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
|
||||
#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
|
||||
#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
|
||||
/* SYSCFG memory remap register */
|
||||
|
||||
#define SYSCFG_MEMRMP_MEMBOOT (1 << 0) /* Bit 0: Memory boot mapping */
|
||||
#define SYSCFG_MEMRMP_MEMBOOT_ADD0 (0 << 0) /* 0=BOOT_ADD0 defines */
|
||||
#define SYSCFG_MEMRMP_MEMBOOT_ADD1 (1 << 0) /* 1=BOOT_ADD1 defines */
|
||||
#define SYSCFG_MEMRMP_SWPFMC_SHIFT (10) /* Bits 10-11: FMC memory mapping swap */
|
||||
#define SYSCFG_MEMRMP_SWPFMC_MASK (3 << SYSCFG_MEMRMP_SWPFMC_SHIFT)
|
||||
# define SYSCFG_MEMRMP_SWPFMC_NONE (0 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* No FMC memory mapping swapping */
|
||||
# define SYSCFG_MEMRMP_SWPFMC_NORRAM (1 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* NOR/RAM and SDRAM memory mapping swapped */
|
||||
|
||||
/* SYSCFG peripheral mode configuration register */
|
||||
|
||||
#define SYSCFG_PMC_I2C1_FMP (1 << 0) /* Bit 0: Forces FM+ drive capability on I2C1 SCL & SDA */
|
||||
#define SYSCFG_PMC_I2C2_FMP (1 << 1) /* Bit 1: Forces FM+ drive capability on I2C2 SCL & SDA */
|
||||
#define SYSCFG_PMC_I2C3_FMP (1 << 2) /* Bit 2: Forces FM+ drive capability on I2C3 SCL & SDA */
|
||||
#define SYSCFG_PMC_PB6_FMP (1 << 4) /* Bit 4: Forces FM+ drive capability on the PB6 pin */
|
||||
#define SYSCFG_PMC_PB7_FMP (1 << 5) /* Bit 5: Forces FM+ drive capability on the PB7 pin */
|
||||
#define SYSCFG_PMC_PB8_FMP (1 << 6) /* Bit 7: Forces FM+ drive capability on the PB8 pin */
|
||||
#define SYSCFG_PMC_PB9_FMP (1 << 7) /* Bit 4: Forces FM+ drive capability on the PB9 pin */
|
||||
#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
|
||||
#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
|
||||
|
||||
/* SYSCFG external interrupt configuration register 1-4 */
|
||||
|
||||
#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */
|
||||
#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */
|
||||
#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */
|
||||
|
||||
#define SYSCFG_EXTICR_PORT_MASK (15)
|
||||
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
|
||||
#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
|
||||
|
||||
#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
|
||||
#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */
|
||||
#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
|
||||
#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */
|
||||
#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
|
||||
#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */
|
||||
#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
|
||||
|
||||
#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
|
||||
#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */
|
||||
#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
/* Compensation cell control register */
|
||||
|
||||
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
|
||||
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,371 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h
|
||||
*
|
||||
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32F7_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUSART > 3
|
||||
# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART6_RTOR (STM32_USART6_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART6_RQR (STM32_USART6_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART6_ISR (STM32_USART6_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART6_ICR (STM32_USART6_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART6_RDR (STM32_USART6_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUART > 0
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUART > 1
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUART > 2
|
||||
# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART7_GTPR (STM32_UART7_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART7_RTOR (STM32_UART7_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART7_RQR (STM32_UART7_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART7_GTPR (STM32_UART7_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART7_ISR (STM32_UART7_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART7_ICR (STM32_UART7_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART7_RDR (STM32_UART7_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32F7_NUART > 3
|
||||
# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART8_GTPR (STM32_UART8_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART8_RTOR (STM32_UART8_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART8_RQR (STM32_UART8_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART8_GTPR (STM32_UART8_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART8_ISR (STM32_UART8_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART8_ICR (STM32_UART8_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART8_RDR (STM32_UART8_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART8_TDR (STM32_UART8_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */
|
||||
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */
|
||||
#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT)
|
||||
# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT)
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */
|
||||
#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT)
|
||||
# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT)
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */
|
||||
#define USART_CR1_M1 (1 << 28) /* Bit 31: Word length, bit 1 */
|
||||
|
||||
#define USART_CR1_ALLINTS \
|
||||
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\
|
||||
USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */
|
||||
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */
|
||||
# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */
|
||||
# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */
|
||||
# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */
|
||||
#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT)
|
||||
# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT)
|
||||
#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */
|
||||
#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT)
|
||||
# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT)
|
||||
#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */
|
||||
#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT)
|
||||
# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT)
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
|
||||
#define USART_CR1_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR1_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */
|
||||
#define USART_CR1_DEM (1 << 14) /* Bit 14: Driver enable mode */
|
||||
#define USART_CR1_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */
|
||||
#define USART_CR1_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */
|
||||
#define USART_CR1_SCARCNT_MASK (7 << USART_CR1_SCARCNT_SHIFT)
|
||||
# define USART_CR1_SCARCNT(n) ((uint32_t)(n) << USART_CR1_SCARCNT_SHIFT)
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/
|
||||
#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT)
|
||||
# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT)
|
||||
#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */
|
||||
#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT)
|
||||
# define USART_BRR_0_3(n) ((uint32_t)(n) << USART_BRR_0_3_SHIFT)
|
||||
#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/
|
||||
#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT)
|
||||
# define USART_BRR_4_7(n) ((uint32_t)(n) << USART_BRR_4_7_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT)
|
||||
|
||||
/* Request register */
|
||||
|
||||
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */
|
||||
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */
|
||||
#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */
|
||||
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */
|
||||
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */
|
||||
|
||||
/* Interrupt & status register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */
|
||||
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */
|
||||
|
||||
#define USART_ISR_ALLBITS (0x0027dfff)
|
||||
|
||||
/* Interrupt flag clear register */
|
||||
|
||||
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
|
||||
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */
|
||||
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
|
||||
|
||||
#define USART_ICR_ALLBITS (0x00021b5f)
|
||||
|
||||
/* Receive data register */
|
||||
|
||||
#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */
|
||||
#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
|
||||
|
||||
/* Transmit data register */
|
||||
|
||||
#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */
|
||||
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H */
|
||||
@@ -75,7 +75,9 @@
|
||||
|
||||
/* Include chip-specific clocking initialization logic */
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
|
||||
# include "chip/stm32f72xx73xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
|
||||
# include "stm32f74xx75xx_rcc.c"
|
||||
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# include "stm32f76xx77xx_rcc.c"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,115 @@
|
||||
############################################################################
|
||||
# configs/nucleo-144/f722-nsh/Make.defs
|
||||
#
|
||||
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
# Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
# David Sidrane <david_s5@nscdg.com>
|
||||
# Bob Feretich <bob.feretich@rafresearch.com>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Change Log:
|
||||
# bf20171114 Added support for nucleo-144 stm32f72ze
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = f722-flash.ld
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ASMEXT = .S
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
@@ -0,0 +1,51 @@
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
# CONFIG_NSH_DISABLE_IFCONFIG is not set
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
CONFIG_ARCH_BOARD_NUCLEO_144=y
|
||||
CONFIG_ARCH_BOARD="nucleo-144"
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP_STM32F7=y
|
||||
CONFIG_ARCH_CHIP_STM32F722ZE=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
|
||||
CONFIG_ARMV7M_DCACHE=y
|
||||
CONFIG_ARMV7M_DTCM=y
|
||||
CONFIG_ARMV7M_ICACHE=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=43103
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DISABLE_POLL=y
|
||||
CONFIG_EXAMPLES_NSH=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_MAX_TASKS=16
|
||||
CONFIG_MAX_WDOGPARMS=2
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_NFILE_DESCRIPTORS=8
|
||||
CONFIG_NFILE_STREAMS=8
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_MQ_MSGS=4
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_PREALLOC_WDOGS=4
|
||||
CONFIG_RAM_SIZE=245760
|
||||
CONFIG_RAM_START=0x20010000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_SERIAL_DISABLE_REORDERING=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_STACK_COLORATION=y
|
||||
CONFIG_START_DAY=30
|
||||
CONFIG_START_MONTH=11
|
||||
CONFIG_START_YEAR=2015
|
||||
CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y
|
||||
CONFIG_STM32F7_USART_BREAKS=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_USART6_SERIAL_CONSOLE=y
|
||||
CONFIG_USER_ENTRYPOINT="nsh_main"
|
||||
CONFIG_WDOG_INTRESERVE=0
|
||||
@@ -0,0 +1,148 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-144/scripts/f722-flash.ld
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Bob Feretich <bob.feretich@rafresearch.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Change Log:
|
||||
* bf20171114 Created from configs/nucleo-144/scripts/f746-flash.ld
|
||||
****************************************************************************/
|
||||
|
||||
/* The STM32F722ZE has 512 KiB of main FLASH memory. This FLASH memory
|
||||
* can be accessed from either the AXIM interface at address 0x0800:0000 or
|
||||
* from the ITCM interface at address 0x0020:0000.
|
||||
*
|
||||
* Additional information, including the option bytes, is available at at
|
||||
* FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
|
||||
*
|
||||
* In the STM32F722ZE, two different boot spaces can be selected through
|
||||
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
|
||||
* BOOT_ADD1 option bytes:
|
||||
*
|
||||
* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
|
||||
* ST programmed value: Flash on ITCM at 0x0020:0000
|
||||
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
|
||||
* ST programmed value: System bootloader at 0x0010:0000
|
||||
*
|
||||
* NuttX does not modify these option byes. On the unmodified NUCLEO-144
|
||||
* board, the BOOT0 pin is at ground so by default, the STM32F722ZE will
|
||||
* boot from address 0x0020:0000 in ITCM FLASH.
|
||||
*
|
||||
* The STM32F722ZE also has 256 KiB of data SRAM (in addition to ITCM SRAM).
|
||||
* SRAM is split up into three blocks:
|
||||
*
|
||||
* 1) 64 KiB of DTCM SRM beginning at address 0x2000:0000
|
||||
* 2) 176 KiB of SRAM1 beginning at address 0x2001:0000
|
||||
* 3) 16 KiB of SRAM2 beginning at address 0x2003:c000
|
||||
*
|
||||
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
|
||||
* where the code expects to begin execution by jumping to the entry point in
|
||||
* the 0x0800:0000 address range.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 512K
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 176K
|
||||
sram2 (rwx) : ORIGIN = 0x2003c000, LENGTH = 16K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
EXTERN(_vectors)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
*(.init_array .init_array.*)
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram1 AT > flash
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram1
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
Reference in New Issue
Block a user