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https://github.com/apache/nuttx.git
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SAM4L: Add logic to enable selected peripherals on power up; Extend configuration so that each peripheral can be selected -- even though the drivers are not yet implemented
This commit is contained in:
Gregory Nutt
+207
-31
@@ -3,10 +3,10 @@
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# see misc/tools/kconfig-language.txt.
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#
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comment "AT91SAM3/SAM4 Configuration Options"
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comment "AT91SAM3/4 Configuration Options"
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choice
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prompt "AT91SAM3 Chip Selection"
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prompt "AT91SAM3/4 Chip Selection"
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default ARCH_CHIP_AT91SAM3U4E
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depends on ARCH_CHIP_SAM34
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@@ -147,47 +147,223 @@ config SAM_PICOCACHE
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depends on ARCH_CHIP_SAM4L
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default y
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config SAM34_DMA
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bool "DMA"
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default n
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select ARCH_DMA
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config SAM34_OCD
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bool "On-chip DEBUG"
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depends on ARCH_CHIP_SAM4L
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default y if DEBUG_SYMBOLS
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default n if !DEBUG_SYMBOLS
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config SAM34_NAND
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bool "NAND support"
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config SAM34_APBA
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bool "APBA bridge"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HSMCI
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bool "HSMCI"
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config SAM34_AESA
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bool "Advanced Encryption Standard"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_UART
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bool "UART"
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default y
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select ARCH_HAVE_UART
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config SAM34_USART0
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bool "USART0"
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default n
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config SAM34_USART1
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bool "USART1"
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default n
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config SAM34_USART2
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bool "USART2"
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default n
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config SAM34_USART3
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bool "USART3"
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config SAM34_IISC
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bool "Inter-IC Sound (I2S) Controller"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_SPI
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bool "SPI"
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default n
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config SAM34_TC0
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bool "Timer/Counter 0"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TC1
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bool "Timer/Counter 1"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TWIM0
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bool "Two-wire Master Interface 0"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TWIS0
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bool "Two-wire Slave Interface 0"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TWIM1
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bool "Two-wire Master Interface 1"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TWIS1
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bool "Two-wire Slave Interface 1"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TWIM2
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bool "Two-wire Master Interface 2"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TWIM3
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bool "Two-wire Master Interface 3"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_UART
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bool "UART"
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default y
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depends on ARCH_CHIP_SAM3U
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select ARCH_HAVE_UART
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config SAM34_PICOUART
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bool "PicoUART"
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default n
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depends on ARCH_CHIP_SAM4L
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select ARCH_HAVE_UART
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config SAM34_USART0
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bool "USART0"
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default n
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select ARCH_HAVE_USART0
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config SAM34_USART1
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bool "USART1"
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default n
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select ARCH_HAVE_USART1
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config SAM34_USART2
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bool "USART2"
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default n
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select ARCH_HAVE_USART2
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config SAM34_USART3
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bool "USART3"
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default n
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select ARCH_HAVE_USART3
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config SAM34_ADCIFE
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bool "ADC controller interface"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_DACC
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bool "DAC Controller"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_ACIFC
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bool "Analog Comparator Interface"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_GLOC
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bool "GLOC"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_ABDACB
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bool "Audio Bitstream DAC"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TRNG
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bool "True Random Number Generator"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_PARC
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bool "Parallel Capture"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_CATB
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bool "Capacitive Touch Module B"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_LCDCA
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bool " LCD Controller A"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HRAMC1
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bool "HRAMC1 (picoCache RAM)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_NAND
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bool "NAND support"
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default n
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depends on ARCH_CHIP_SAM3U
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config SAM34_HMATRIX
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bool "HMATRIX"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_PDCA
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bool "Peripheral DMA controller"
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default n
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depends on ARCH_CHIP_SAM4L
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select ARCH_DMA
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config SAM34_DMA
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bool "DMA"
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default n
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depends on ARCH_CHIP_SAM3U
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select ARCH_DMA
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config SAM34_CRCCU
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bool "CRC Calculation Unit"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_USBC
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bool "USB 2.0 Interface"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_PEVC
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bool "Peripheral Event Controller"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_CHIPID
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bool "Chip ID"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_FREQM
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bool "Frequency Mete"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_AST
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bool "Asynchronous Timer"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_WDT
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bool "Watchdog Timer"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_EIC
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bool "External Interrupt Controller"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HSMCI
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bool "HSMCI"
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default n
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depends on ARCH_CHIP_SAM3U
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endmenu
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menu "AT91SAM3 UART Configuration"
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menu "AT91SAM3/4 USART Configuration"
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config USART0_ISUART
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bool "USART0 is a UART"
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@@ -215,7 +391,7 @@ config USART3_ISUART
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endmenu
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menu "AT91SAM3 GPIO Interrupt Configuration"
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menu "AT91SAM3/4 GPIO Interrupt Configuration"
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config GPIOA_IRQ
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bool "GPIOA interrupts"
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@@ -145,7 +145,7 @@
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/* CPU Mask Register Bit-field Definitions */
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#define PM_CPUMASK_OCD (1 << 0) /* Bit 0: OCD */
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#define PM_CPUMASK_OCD (1 << 0) /* Bit 0: On-Chip Debug */
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/* HSB Mask Register Bit-field Definitions */
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@@ -53,6 +53,7 @@
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#include "chip/sam4l_bscif.h"
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#include "chip/sam4l_flashcalw.h"
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#include "sam_periphclks.h"
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#include "sam_clockconfig.h"
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/****************************************************************************
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@@ -80,11 +81,11 @@
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* either PLL0 or DFPLL. It might also be needed if OSC0 is the source
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* clock for GCLK9.
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*
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* By selecting CONFIG_SAM_OSC0, you can also force the clock to be enabled
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* By selecting CONFIG_SAM34_OSC0, you can also force the clock to be enabled
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* at boot time.
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*/
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#if defined(CONFIG_SAM_OSC0) || defined(BOARD_SYSCLK_SOURCE_OSC0) || \
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#if defined(CONFIG_SAM34_OSC0) || defined(BOARD_SYSCLK_SOURCE_OSC0) || \
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defined(BOARD_DFLL0_SOURCE_OSC0) || defined(BOARD_PLL0_SOURCE_OSC0) || \
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defined(BOARD_GLCK9_SOURCE_OSC0)
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# define NEED_OSC0 1
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@@ -143,12 +144,12 @@
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/* OSC32. The 32K oscillator may be the source clock for DFPLL0 or
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* the source clock for GLK9 that might be used to driver PLL0.
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*
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* By selecting CONFIG_SAM_OSC32K, you can also force the clock to be
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* By selecting CONFIG_SAM34_OSC32K, you can also force the clock to be
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* enabled at boot time. OSC32 may needed by other devices as well
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* (AST, WDT, PICUART, RTC).
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*/
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#if defined(CONFIG_SAM_OSC32K) || defined(BOARD_DFLL0_SOURCE_OSC32K) || \
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#if defined(CONFIG_SAM34_OSC32K) || defined(BOARD_DFLL0_SOURCE_OSC32K) || \
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defined(BOARD_GLCK9_SOURCE_OSC32K)
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# define NEED_OSC32K 1
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#endif
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@@ -190,58 +191,58 @@
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/* RC80M. This might be the system clock or the source clock for the DFPLL
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* or it could be the source for GCLK9 that drives PLL0.
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*
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* By selecting CONFIG_SAM_RC80M, you can also force the clock to be enabled
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* By selecting CONFIG_SAM34_RC80M, you can also force the clock to be enabled
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* at boot time.
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*/
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#if defined(CONFIG_SAM_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \
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#if defined(CONFIG_SAM34_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \
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defined(BOARD_DFLL0_SOURCE_RC80M) || BOARD_GLCK9_SOURCE_RC80M
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# define NEED_RC80M 1
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#endif
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/* RCFAST. The 12/8/4 fast RC oscillator may be used as the system clock
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* or as the source for GLCK9 that drives PLL0.
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* If not then, it may be enabled by setting the CONFIG_SAM_RCFASTxM
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* If not then, it may be enabled by setting the CONFIG_SAM34_RCFASTxM
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* configuration variable.
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*/
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#if defined(CONFIG_SAM_RCFAST12M)
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# undef CONFIG_SAM_RCFAST8M
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# undef CONFIG_SAM_RCFAST4M
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#elif defined(CONFIG_SAM_RCFAST8M)
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# undef CONFIG_SAM_RCFAST4M
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#if defined(CONFIG_SAM34_RCFAST12M)
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# undef CONFIG_SAM34_RCFAST8M
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# undef CONFIG_SAM34_RCFAST4M
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#elif defined(CONFIG_SAM34_RCFAST8M)
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# undef CONFIG_SAM34_RCFAST4M
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#endif
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#if defined(BOARD_SYSCLK_SOURCE_FCFAST12M)
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# if defined(CONFIG_SAM_RCFAST8M) || defined(CONFIG_SAM_RCFAST4M)
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# error BOARD_SYSCLK_SOURCE_FCFAST12M inconsistent with CONFIG_SAM_RCFAST8/4M
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# if defined(CONFIG_SAM34_RCFAST8M) || defined(CONFIG_SAM34_RCFAST4M)
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# error BOARD_SYSCLK_SOURCE_FCFAST12M inconsistent with CONFIG_SAM34_RCFAST8/4M
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# endif
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY
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#elif defined(BOARD_SYSCLK_SOURCE_FCFAST8M)
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# if defined(CONFIG_SAM_RCFAST12M) || defined(CONFIG_SAM_RCFAST4M)
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# error BOARD_SYSCLK_SOURCE_FCFAST8M inconsistent with CONFIG_SAM_RCFAST12/4M
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# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST4M)
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# error BOARD_SYSCLK_SOURCE_FCFAST8M inconsistent with CONFIG_SAM34_RCFAST12/4M
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# endif
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY
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#elif defined(BOARD_SYSCLK_SOURCE_FCFAST4M)
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# if defined(CONFIG_SAM_RCFAST12M) || defined(CONFIG_SAM_RCFAST8M)
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# error BOARD_SYSCLK_SOURCE_FCFAST4M inconsistent with CONFIG_SAM_RCFAST12/8M
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# if defined(CONFIG_SAM34_RCFAST12M) || defined(CONFIG_SAM34_RCFAST8M)
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# error BOARD_SYSCLK_SOURCE_FCFAST4M inconsistent with CONFIG_SAM34_RCFAST12/8M
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# endif
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY
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#elif defined(CONFIG_SAM_RCFAST12M)
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#elif defined(CONFIG_SAM34_RCFAST12M)
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_12MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST12M_FREQUENCY
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#elif defined(CONFIG_SAM_RCFAST8M)
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#elif defined(CONFIG_SAM34_RCFAST8M)
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_8MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST8M_FREQUENCY
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#elif defined(CONFIG_SAM_RCFAST4M)
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#elif defined(CONFIG_SAM34_RCFAST4M)
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# define NEED_RCFAST 1
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# define SAM_RCFAST_RANGE SCIF_RCFASTCFG_FRANGE_4MHZ
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# define SAM_RCFAST_FREQUENCY SAM_RCFAST4M_FREQUENCY
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@@ -250,11 +251,11 @@
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/* RC1M. The 1M RC oscillator may be used as the system block or
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* may be the source clock for GLCK9 that drives PLL0
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*
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* By selecting CONFIG_SAM_RC1M, you can also force the clock to be
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* By selecting CONFIG_SAM34_RC1M, you can also force the clock to be
|
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* enabled at boot time.
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*/
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#if defined(CONFIG_SAM_RC1M) || defined(BOARD_SYSCLK_SOURCE_RC1M) || \
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#if defined(CONFIG_SAM34_RC1M) || defined(BOARD_SYSCLK_SOURCE_RC1M) || \
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defined(BOARD_GLCK9_SOURCE_RC1M)
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# define NEED_RC1M 1
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#endif
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@@ -262,11 +263,11 @@
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/* RC32K. The 32KHz RC oscillator may be used as the input to DFLL0
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* or as the input to GCLK9 that drives PLL0.
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*
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* By selecting CONFIG_SAM_RC32K, you can also force the clock to be
|
||||
* By selecting CONFIG_SAM34_RC32K, you can also force the clock to be
|
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* enabled at boot time.
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*/
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#if defined(CONFIG_SAM_RC32K) || defined(BOARD_DFLL0_SOURCE_RC32K) || \
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#if defined(CONFIG_SAM34_RC32K) || defined(BOARD_DFLL0_SOURCE_RC32K) || \
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defined(BOARD_GLCK9_SOURCE_RC32K)
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# define NEED_RC32K 1
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#endif
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@@ -448,7 +449,7 @@
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*
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****************************************************************************/
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#ifdef CONFIG_SAM_PICOCACHE
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#ifdef CONFIG_SAM34_PICOCACHE
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static inline void sam_picocache(void)
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{
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/* Enable clocking to the PICOCACHE */
|
||||
@@ -1068,7 +1069,7 @@ void sam_clockconfig(void)
|
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* ------- ---- ----- -------- ---------- ----------
|
||||
*/
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||||
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#ifdef CONFIG_SAM_FLASH_HSEN
|
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#ifdef CONFIG_SAM34_FLASH_HSEN
|
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/* The high speed FLASH mode has been enabled. Select power scaling
|
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* mode 2, no fast wakeup.
|
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*/
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@@ -1238,6 +1239,10 @@ void sam_clockconfig(void)
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sam_setpsm(psm);
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||||
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/* Enable all selected peripheral cloks */
|
||||
|
||||
sam_init_periphclks();
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||||
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||||
#ifdef CONFIG_USBDEV
|
||||
void sam_usbclock();
|
||||
#endif
|
||||
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||||
@@ -52,7 +52,7 @@
|
||||
#include "sam4l_periphclks.h"
|
||||
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||||
/****************************************************************************
|
||||
* Private Definitions
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
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||||
/****************************************************************************
|
||||
@@ -75,10 +75,316 @@
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_cpumask
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on selected peripherals in the
|
||||
* CPU mask register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void sam_init_cpumask(void)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM34_OCD
|
||||
mask |= PM_CPUMASK_OCD; /* On-Chip Debug */
|
||||
#endif
|
||||
|
||||
/* Save the new CPU mask */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(mask, SAM_PM_CPUMASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_hsbmask
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on selected peripherals in the
|
||||
* HSB mask register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void sam_init_hsbmask(void)
|
||||
{
|
||||
/* Select the non-optional peripherals */
|
||||
|
||||
uint32_t mask = (PM_HSBMASK_FLASHCALW | PM_HSBMASK_APBB |
|
||||
PM_HSBMASK_APBC | PM_HSBMASK_APBD)
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM34_PDCA
|
||||
mask |= PM_HSBMASK_PDCA; /* PDCA */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_HRAMC1
|
||||
mask |= PM_HSBMASK_HRAMC1; /* HRAMC1 (picoCache RAM) */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
mask |= PM_HSBMASK_USBC; /* USBC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_CRCCU
|
||||
mask |= PM_HSBMASK_CRCCU; /* CRCCU */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_APBA
|
||||
mask |= PM_HSBMASK_APBA; /* APBA bridge */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_AESA
|
||||
mask |= PM_HSBMASK_AESA; /* AESA */
|
||||
#endif
|
||||
|
||||
/* Save the new HSB mask */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_HSBMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(mask, SAM_PM_HSBMASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_pbamask
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on selected peripherals in the
|
||||
* PBA mask register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void sam_init_pbamask(void)
|
||||
{
|
||||
/* Select the non-optional peripherals */
|
||||
|
||||
uint32_t mask = 0;
|
||||
uint32_t divmask = 0;
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM34_IISC
|
||||
mask |= PM_PBAMASK_IISC; /* IISC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_SPI
|
||||
mask |= PM_PBAMASK_SPI; /* SPI */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TC0
|
||||
mask |= PM_PBAMASK_TC0; /* TC0 */
|
||||
divmask |= PM_PBADIVMASK_TIMER_CLOCKS;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TC1
|
||||
mask |= PM_PBAMASK_TC1; /* TC1 */
|
||||
divmask |= PM_PBADIVMASK_TIMER_CLOCKS;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TWIM0
|
||||
mask |= PM_PBAMASK_TWIM0; /* TWIM0 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TWIS0
|
||||
mask |= PM_PBAMASK_TWIS0; /* TWIS0 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TWIM1
|
||||
mask |= PM_PBAMASK_TWIM1; /* TWIM1 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TWIS1
|
||||
mask |= PM_PBAMASK_TWIS1; /* TWIS1 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART0
|
||||
mask |= PM_PBAMASK_USART0; /* USART0 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART1
|
||||
mask |= PM_PBAMASK_USART1; /* USART1 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART2
|
||||
mask |= PM_PBAMASK_USART2; /* USART2 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART3
|
||||
mask |= PM_PBAMASK_USART3; /* USART3 */
|
||||
divmask |= PBA_DIVMASK_CLK_USART;
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_ADCIFE
|
||||
mask |= PM_PBAMASK_ADCIFE; /* ADCIFE */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_DACC
|
||||
mask |= PM_PBAMASK_DACC; /* DACC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_ACIFC
|
||||
mask |= PM_PBAMASK_ACIFC; /* ACIFC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_GLOC
|
||||
mask |= PM_PBAMASK_GLOC; /* GLOC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_ABDACB
|
||||
mask |= PM_PBAMASK_ABDACB; /* ABDACB */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TRNG
|
||||
mask |= PM_PBAMASK_TRNG; /* TRNG */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_PARC
|
||||
mask |= PM_PBAMASK_PARC; /* PARC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_CATB
|
||||
mask |= PM_PBAMASK_CATB; /* CATB */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TWIM2
|
||||
mask |= PM_PBAMASK_TWIM2; /* TWIM2 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_TWIM3
|
||||
mask |= PM_PBAMASK_TWIM3; /* TWIM3 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_LCDCA
|
||||
mask |= PM_PBAMASK_LCDCA; /* LCDCA*/
|
||||
#endif
|
||||
|
||||
/* Save the new PBA mask */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBAMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(mask, SAM_PM_PBAMASK);
|
||||
|
||||
/* Set the peripheral divider mask as necessary */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(divmask, SAM_PM_PBADIVMASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_pbbmask
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on selected peripherals in the
|
||||
* PBB mask register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void sam_init_pbbmask(void)
|
||||
{
|
||||
/* Select the non-optional peripherals */
|
||||
|
||||
uint32_t mask = PM_PBBMASK_FLASHCALW;
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM34_HRAMC1
|
||||
mask |= PM_PBBMASK_HRAMC1; /* HRAMC1 */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_HMATRIX
|
||||
mask |= PM_PBBMASK_HMATRIX; /* HMATRIX */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_PDCA
|
||||
mask |= PM_PBBMASK_PDCA; /* PDCA */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_CRCCU
|
||||
mask |= PM_PBBMASK_CRCCU; /* CRCCU */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USBC
|
||||
mask |= PM_PBBMASK_USBC; /* USBC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_PEVC
|
||||
mask |= PM_PBBMASK_PEVC; /* PEVC */
|
||||
#endif
|
||||
|
||||
/* Save the new PBB mask */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(mask, SAM_PM_PBBMASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_pbcmask
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on selected peripherals in the
|
||||
* PBC mask register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void sam_init_pbcmask(void)
|
||||
{
|
||||
/* Select the non-optional peripherals */
|
||||
|
||||
uint32_t mask = (PM_PBCMASK_PM | PM_PBCMASK_SCIF | PM_PBCMASK_GPIO);
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM34_CHIPID
|
||||
mask |= PM_PBCMASK_CHIPID; /* CHIPID */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_FREQM
|
||||
mask |= PM_PBCMASK_FREQM; /* FREQM */
|
||||
#endif
|
||||
|
||||
/* Save the new PBC mask */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(mask, SAM_PM_PBCMASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_pbdmask
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on selected peripherals in the
|
||||
* PBD mask register.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void sam_init_pbdmask(void)
|
||||
{
|
||||
/* Select the non-optional peripherals */
|
||||
|
||||
uint32_t mask = (PM_PBDMASK_BPM | PM_PBDMASK_BSCIF);
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM34_AST
|
||||
mask |= PM_PBDMASK_AST; /* AST */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_WDT
|
||||
mask |= PM_PBDMASK_WDT; /* WDT */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_EIC
|
||||
mask |= PM_PBDMASK_EIC; /* EIC */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_PICOUART
|
||||
mask |= PM_PBDMASK_PICOUART; /* PICOUART */
|
||||
#endif
|
||||
|
||||
/* Save the new PBD mask */
|
||||
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(mask, SAM_PM_PBDMASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_init_periphclks
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on all selected peripherals.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_init_periphclks(void)
|
||||
{
|
||||
sam_init_cpumask();
|
||||
sam_init_hsbmask();
|
||||
sam_init_pbamask();
|
||||
sam_init_pbbmask();
|
||||
sam_init_pbcmask();
|
||||
sam_init_pbdmask();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_modifyperipheral
|
||||
*
|
||||
@@ -88,7 +394,8 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits)
|
||||
void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits,
|
||||
uint32_t setbits)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
@@ -102,7 +409,8 @@ void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits)
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~clrbits;
|
||||
regval |= setbits;
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK);
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
irqrestore(flags);
|
||||
@@ -131,7 +439,8 @@ void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits)
|
||||
regval = getreg32(SAM_PM_PBADIVMASK);
|
||||
regval &= ~clrbits;
|
||||
regval |= setbits;
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET), SAM_PM_UNLOCK);
|
||||
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET),
|
||||
SAM_PM_UNLOCK);
|
||||
putreg32(regval, SAM_PM_PBADIVMASK);
|
||||
|
||||
irqrestore(flags);
|
||||
|
||||
@@ -42,6 +42,8 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
@@ -262,83 +264,77 @@ extern "C"
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: sam_init_periphclks
|
||||
*
|
||||
* Description:
|
||||
* Called during boot to enable clocking on all selected peripherals.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void sam_init_periphclks(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: sam_modifyperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function that is intended to be used to enable
|
||||
* or disable module clocking.
|
||||
* This is a convenience function that is intended to be used to enable or disable
|
||||
* module clocking.
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: sam_pba_modifydivmask
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function that is intended to be used to modify
|
||||
* bits in the PBA divided clock (DIVMASK) register.
|
||||
* This is a convenience function that is intended to be used to modify bits in
|
||||
* the PBA divided clock (DIVMASK) register.
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: sam_pba_enableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to enable a peripheral on the APBA
|
||||
* bridge.
|
||||
* This is a convenience function to enable a peripheral on the APBA bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pba_enableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: sam_pba_disableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to disable a peripheral on the APBA
|
||||
* bridge.
|
||||
* This is a convenience function to disable a peripheral on the APBA bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pba_disableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: sam_pbb_enableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to enable a peripheral on the APBB
|
||||
* bridge.
|
||||
* This is a convenience function to enable a peripheral on the APBB bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pbb_enableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: sam_pbb_disableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to disable a peripheral on the APBA
|
||||
* bridge.
|
||||
* This is a convenience function to disable a peripheral on the APBA bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pbb_disableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
@@ -346,4 +342,5 @@ void sam_pbb_disableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_ARCH_CHIP_SAM4L */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H */
|
||||
|
||||
@@ -329,15 +329,61 @@ SAM4L Xplained Pro-specific Configuration Options
|
||||
|
||||
Individual subsystems can be enabled:
|
||||
|
||||
CONFIG_SAM34_DMA
|
||||
CONFIG_SAM34_HSMCI
|
||||
CONFIG_SAM34_NAND
|
||||
CPU
|
||||
---
|
||||
CONFIG_SAM34_OCD
|
||||
|
||||
HSB
|
||||
---
|
||||
CONFIG_SAM34_APBA
|
||||
CONFIG_SAM34_AESA
|
||||
|
||||
PBA
|
||||
---
|
||||
CONFIG_SAM34_IISC
|
||||
CONFIG_SAM34_SPI
|
||||
CONFIG_SAM34_UART
|
||||
CONFIG_SAM34_TC0
|
||||
CONFIG_SAM34_TC1
|
||||
CONFIG_SAM34_TWIM0
|
||||
CONFIG_SAM34_TWIS0
|
||||
CONFIG_SAM34_TWIM1
|
||||
CONFIG_SAM34_TWIS1
|
||||
CONFIG_SAM34_USART0
|
||||
CONFIG_SAM34_USART1
|
||||
CONFIG_SAM34_USART2
|
||||
CONFIG_SAM34_USART3
|
||||
CONFIG_SAM34_ADCIFE
|
||||
CONFIG_SAM34_DACC
|
||||
CONFIG_SAM34_ACIFC
|
||||
CONFIG_SAM34_GLOC
|
||||
CONFIG_SAM34_ABDACB
|
||||
CONFIG_SAM34_TRNG
|
||||
CONFIG_SAM34_PARC
|
||||
CONFIG_SAM34_CATB
|
||||
CONFIG_SAM34_TWIM2
|
||||
CONFIG_SAM34_TWIM3
|
||||
CONFIG_SAM34_LCDCA
|
||||
|
||||
PBB
|
||||
---
|
||||
CONFIG_SAM34_HRAMC1
|
||||
CONFIG_SAM34_HMATRIX
|
||||
CONFIG_SAM34_PDCA
|
||||
CONFIG_SAM34_CRCCU
|
||||
CONFIG_SAM34_USBC
|
||||
CONFIG_SAM34_PEVC
|
||||
|
||||
PBC
|
||||
---
|
||||
CONFIG_SAM34_CHIPID
|
||||
CONFIG_SAM34_FREQM
|
||||
|
||||
PBD
|
||||
---
|
||||
CONFIG_SAM34_AST
|
||||
CONFIG_SAM34_WDT
|
||||
CONFIG_SAM34_EIC
|
||||
CONFIG_SAM34_PICOUART
|
||||
|
||||
Some subsystems can be configured to operate in different ways. The drivers
|
||||
need to know how to configure the subsystem.
|
||||
|
||||
@@ -127,18 +127,47 @@ CONFIG_ARCH_CHIP_SAM4L=y
|
||||
# AT91SAM3 Peripheral Support
|
||||
#
|
||||
CONFIG_SAM_PICOCACHE=y
|
||||
# CONFIG_SAM34_DMA is not set
|
||||
# CONFIG_SAM34_NAND is not set
|
||||
# CONFIG_SAM34_HSMCI is not set
|
||||
# CONFIG_SAM34_UART is not set
|
||||
# CONFIG_SAM34_OCD is not set
|
||||
# CONFIG_SAM34_APBA is not set
|
||||
# CONFIG_SAM34_AESA is not set
|
||||
# CONFIG_SAM34_IISC is not set
|
||||
# CONFIG_SAM34_SPI is not set
|
||||
# CONFIG_SAM34_TC0 is not set
|
||||
# CONFIG_SAM34_TC1 is not set
|
||||
# CONFIG_SAM34_TWIM0 is not set
|
||||
# CONFIG_SAM34_TWIS0 is not set
|
||||
# CONFIG_SAM34_TWIM1 is not set
|
||||
# CONFIG_SAM34_TWIS1 is not set
|
||||
# CONFIG_SAM34_TWIM2 is not set
|
||||
# CONFIG_SAM34_TWIM3 is not set
|
||||
# CONFIG_SAM34_PICOUART is not set
|
||||
# CONFIG_SAM34_USART0 is not set
|
||||
CONFIG_SAM34_USART1=y
|
||||
# CONFIG_SAM34_USART2 is not set
|
||||
# CONFIG_SAM34_USART3 is not set
|
||||
# CONFIG_SAM34_SPI is not set
|
||||
# CONFIG_SAM34_ADCIFE is not set
|
||||
# CONFIG_SAM34_DACC is not set
|
||||
# CONFIG_SAM34_ACIFC is not set
|
||||
# CONFIG_SAM34_GLOC is not set
|
||||
# CONFIG_SAM34_ABDACB is not set
|
||||
# CONFIG_SAM34_TRNG is not set
|
||||
# CONFIG_SAM34_PARC is not set
|
||||
# CONFIG_SAM34_CATB is not set
|
||||
# CONFIG_SAM34_LCDCA is not set
|
||||
# CONFIG_SAM34_HRAMC1 is not set
|
||||
# CONFIG_SAM34_HMATRIX is not set
|
||||
# CONFIG_SAM34_PDCA is not set
|
||||
# CONFIG_SAM34_CRCCU is not set
|
||||
# CONFIG_SAM34_USBC is not set
|
||||
# CONFIG_SAM34_PEVC is not set
|
||||
# CONFIG_SAM34_CHIPID is not set
|
||||
# CONFIG_SAM34_FREQM is not set
|
||||
# CONFIG_SAM34_AST is not set
|
||||
# CONFIG_SAM34_WDT is not set
|
||||
# CONFIG_SAM34_EIC is not set
|
||||
|
||||
#
|
||||
# AT91SAM3 UART Configuration
|
||||
# AT91SAM3/4 USART Configuration
|
||||
#
|
||||
CONFIG_USART1_ISUART=y
|
||||
|
||||
|
||||
Reference in New Issue
Block a user