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Merged in raiden00/nuttx (pull request #595)

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stm32_hritm: add interface to set timer frequency, fix slave timers reset configuration, change POWER_INFO to TIMER_INFO

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
2018-02-11 13:12:00 +00:00
committed by Gregory Nutt
parent 2bb5795e54
commit 118e97ff37
5 changed files with 443 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
+5 -5
View File
@@ -818,7 +818,7 @@
#define HRTIM_TIMARST_TIMCCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMARST_TIMDCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMARST_TIMDCMP2 (1 << 26) /* Bit 26 */
#define HRTIM_TIMARST_TIMDCMP3 (1 << 27) /* Bit 27 */
#define HRTIM_TIMARST_TIMDCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMARST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMARST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMARST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -849,7 +849,7 @@
#define HRTIM_TIMBRST_TIMCCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMBRST_TIMDCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMBRST_TIMDCMP2 (1 << 26) /* Bit 26 */
#define HRTIM_TIMBRST_TIMDCMP3 (1 << 27) /* Bit 27 */
#define HRTIM_TIMBRST_TIMDCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMBRST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMBRST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMBRST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -880,7 +880,7 @@
#define HRTIM_TIMCRST_TIMBCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMCRST_TIMDCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMCRST_TIMDCMP2 (1 << 26) /* Bit 26 */
#define HRTIM_TIMCRST_TIMDCMP3 (1 << 27) /* Bit 27 */
#define HRTIM_TIMCRST_TIMDCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMCRST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMCRST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMCRST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -911,7 +911,7 @@
#define HRTIM_TIMDRST_TIMBCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMDRST_TIMCCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMDRST_TIMCCMP2 (1 << 26) /* Bit 26 */
#define HRTIM_TIMDRST_TIMCCMP3 (1 << 27) /* Bit 27 */
#define HRTIM_TIMDRST_TIMCCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMDRST_TIMECMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMDRST_TIMECMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMDRST_TIMECMP4 (1 << 30) /* Bit 30 */
@@ -942,7 +942,7 @@
#define HRTIM_TIMERST_TIMBCMP4 (1 << 24) /* Bit 24 */
#define HRTIM_TIMERST_TIMCCMP1 (1 << 25) /* Bit 25 */
#define HRTIM_TIMERST_TIMCCMP2 (1 << 26) /* Bit 26 */
#define HRTIM_TIMERST_TIMCCMP3 (1 << 27) /* Bit 27 */
#define HRTIM_TIMERST_TIMCCMP4 (1 << 27) /* Bit 27 */
#define HRTIM_TIMERST_TIMDCMP1 (1 << 28) /* Bit 28 */
#define HRTIM_TIMERST_TIMDCMP2 (1 << 29) /* Bit 29 */
#define HRTIM_TIMERST_TIMDCMP4 (1 << 30) /* Bit 30 */
arch/arm/src/stm32/stm32_hrtim.c
+371 -49
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32_hrtim.h
+65 -37
View File
@@ -216,6 +216,14 @@
(hrtim)->hd_ops->per_get(hrtim, tim)
#define HRTIM_FCLK_GET(hrtim, tim) \
(hrtim)->hd_ops->fclk_get(hrtim, tim)
#define HRTIM_IRQ_GET(hrtim, irq) \
(hrtim)->hd_ops->irq_get(hrtim, irq)
#define HRTIM_IRQ_ACK(hrtim, irq, ack) \
(hrtim)->hd_ops->irq_ack(hrtim, irq, ack)
#define HRTIM_SOFT_UPDATE(hrtim, timer) \
(hrtim)->hd_ops->soft_update(hrtim, timer)
#define HRTIM_FREQ_SET(hrtim, timer,freq) \
(hrtim)->hd_ops->freq_set(hrtim, timer, freq)
#define HRTIM_OUTPUTS_ENABLE(hrtim, outputs, state) \
(hrtim)->hd_ops->outputs_enable(hrtim, outputs, state)
#define HRTIM_OUTPUT_SET_SET(hrtim, output, set) \
@@ -349,48 +357,48 @@ enum stm32_hrtim_tim_rst_e
{
/* Timer owns events */
HRTIM_RST_UPDT,
HRTIM_RST_CMP4,
HRTIM_RST_CMP2,
HRTIM_RST_UPDT = (1<<1),
HRTIM_RST_CMP4 = (1<<2),
HRTIM_RST_CMP2 = (1<<3),
/* Master Timer Events */
HRTIM_RST_MSTCMP4,
HRTIM_RST_MSTCMP3,
HRTIM_RST_MSTCMP2,
HRTIM_RST_MSTCMP1,
HRTIM_RST_MSTPER,
/* TimerX events */
HRTIM_RST_TECMP4,
HRTIM_RST_TECMP2,
HRTIM_RST_TECMP1,
HRTIM_RST_TDCMP4,
HRTIM_RST_TDCMP2,
HRTIM_RST_TDCMP1,
HRTIM_RST_TCCMP4,
HRTIM_RST_TCCMP2,
HRTIM_RST_TCCMP1,
HRTIM_RST_TBCMP4,
HRTIM_RST_TBCMP2,
HRTIM_RST_TBCMP1,
HRTIM_RST_TACMP4,
HRTIM_RST_TACMP2,
HRTIM_RST_TACMP1,
HRTIM_RST_MSTPER = (1<<4),
HRTIM_RST_MSTCMP1 = (1<<5),
HRTIM_RST_MSTCMP2 = (1<<6),
HRTIM_RST_MSTCMP3 = (1<<7),
HRTIM_RST_MSTCMP4 = (1<<8),
/* External Events */
HRTIM_RST_EXTEVNT10,
HRTIM_RST_EXTEVNT9,
HRTIM_RST_EXTEVNT8,
HRTIM_RST_EXTEVNT7,
HRTIM_RST_EXTEVNT6,
HRTIM_RST_EXTEVNT5,
HRTIM_RST_EXTEVNT4,
HRTIM_RST_EXTEVNT3,
HRTIM_RST_EXTEVNT2,
HRTIM_RST_EXTEVNT1
HRTIM_RST_EXTEVNT1 = (1<<9),
HRTIM_RST_EXTEVNT2 = (1<<10),
HRTIM_RST_EXTEVNT3 = (1<<11),
HRTIM_RST_EXTEVNT4 = (1<<12),
HRTIM_RST_EXTEVNT5 = (1<<13),
HRTIM_RST_EXTEVNT6 = (1<<14),
HRTIM_RST_EXTEVNT7 = (1<<15),
HRTIM_RST_EXTEVNT8 = (1<<16),
HRTIM_RST_EXTEVNT9 = (1<<17),
HRTIM_RST_EXTEVNT10 = (1<<18),
/* TimerX events */
HRTIM_RST_TACMP1 = (1<<19),
HRTIM_RST_TACMP2 = (1<<20),
HRTIM_RST_TACMP4 = (1<<21),
HRTIM_RST_TBCMP1 = (1<<22),
HRTIM_RST_TBCMP2 = (1<<23),
HRTIM_RST_TBCMP4 = (1<<24),
HRTIM_RST_TCCMP1 = (1<<25),
HRTIM_RST_TCCMP2 = (1<<26),
HRTIM_RST_TCCMP4 = (1<<27),
HRTIM_RST_TDCMP1 = (1<<28),
HRTIM_RST_TDCMP2 = (1<<29),
HRTIM_RST_TDCMP4 = (1<<30),
HRTIM_RST_TECMP1 = (1<<31),
HRTIM_RST_TECMP2 = (1<<32),
HRTIM_RST_TECMP4 = (1<<33),
};
/* HRTIM Timer X prescaler */
@@ -772,6 +780,21 @@ enum stm32_hrtim_dac_e
HRTIM_DAC_TRIG3 = 3
};
/* HRTIM Timer update events */
enum stm32_tim_update_e
{
HRTIM_UPDATE_NONE = 0,
HRTIM_UPDATE_MSTU = (1 << 0),
HRTIM_UPDATE_TAU = (1 << 2),
HRTIM_UPDATE_TBU = (1 << 3),
HRTIM_UPDATE_TCU = (1 << 4),
HRTIM_UPDATE_TDU = (1 << 5),
HRTIM_UPDATE_TEU = (1 << 6),
HRTIM_UPDATE_RSTU = (1 << 7),
HRTIM_UPDATE_REPU = (1 << 8),
};
/* HRTIM Master Timer interrupts */
enum stm32_irq_master_e
@@ -981,8 +1004,13 @@ struct stm32_hrtim_ops_s
uint16_t (*cmp_get)(FAR struct hrtim_dev_s *dev, uint8_t timer,
uint8_t index);
uint64_t (*fclk_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
int (*soft_update)(FAR struct hrtim_dev_s *dev, uint8_t timer);
int (*freq_set)(FAR struct hrtim_dev_s *hrtim, uint8_t timer,
uint64_t freq);
#ifdef CONFIG_STM32_HRTIM_INTERRUPTS
void (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
int (*irq_ack)(FAR struct hrtim_dev_s *dev, uint8_t timer, int source);
uint16_t (*irq_get)(FAR struct hrtim_dev_s *dev, uint8_t timer);
#endif
#ifdef CONFIG_STM32_HRTIM_PWM
int (*outputs_enable)(FAR struct hrtim_dev_s *dev, uint16_t outputs,
drivers/power/powerled.c
+1 -1
View File
@@ -413,7 +413,7 @@ int powerled_register(FAR const char *path, FAR struct powerled_dev_s *dev, FAR
DEBUGASSERT(dev->ops->fault_clean != NULL);
DEBUGASSERT(dev->ops->ioctl != NULL);
/* Initialize the HRTIM device structure */
/* Initialize the powerled device structure */
dev->ocount = 0;
drivers/power/smps.c
+1 -1
View File
@@ -506,7 +506,7 @@ int smps_register(FAR const char *path, FAR struct smps_dev_s *dev, FAR void *lo
DEBUGASSERT(dev->ops->fault_clean != NULL);
DEBUGASSERT(dev->ops->ioctl != NULL);
/* Initialize the HRTIM device structure */
/* Initialize the SMPS device structure */
dev->ocount = 0;