mirror of
https://github.com/apache/nuttx.git
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boards/nucleo-h743zi: Add nxboot bootloader support
Add nxboot bootloader board integration for nucleo-h743zi. nxboot uses a three-slot layout (primary, secondary, tertiary) with no scratch partition. - add STM32_APP_FORMAT_NXBOOT board support and nxboot-specific OTA slot defaults - gate scratch partition configuration on MCUboot, where it applies - select nxboot linker scripts in the board build logic - add tertiary OTA partition support in stm32_progmem.c - add nxboot-loader and nxboot-app defconfigs and linker scripts - validate the fixed nxboot flash layout used by this board so mismatched config values fail at build time instead of producing a silently broken image Signed-off-by: Neil Berkman <neil@xuku.com>
This commit is contained in:
Neil Berkman
committed by
Alan C. Assis
Alan C. Assis
parent
bd5e017ebd
commit
107b7a9aa1
@@ -674,6 +674,16 @@ config STM32_APP_FORMAT_MCUBOOT
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comment "MCUboot support depends on CONFIG_EXPERIMENTAL"
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depends on !EXPERIMENTAL
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config STM32_APP_FORMAT_NXBOOT
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bool "NuttX nxboot format"
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select STM32_HAVE_OTA_PARTITION
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depends on EXPERIMENTAL
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---help---
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The NuttX nxboot support of loading the firmware images.
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comment "nxboot support depends on CONFIG_EXPERIMENTAL"
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depends on !EXPERIMENTAL
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endchoice # Application Image Format
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endmenu # Application Image Configuration
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@@ -6593,29 +6603,44 @@ config STM32_OTA_SECONDARY_SLOT_DEVPATH
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string "Application image secondary slot device path"
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default "/dev/ota1"
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config STM32_OTA_TERTIARY_SLOT_DEVPATH
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string "Application image tertiary slot device path"
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default "/dev/ota2"
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depends on STM32_APP_FORMAT_NXBOOT
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config STM32_OTA_SCRATCH_DEVPATH
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string "Scratch partition device path"
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default "/dev/otascratch"
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depends on STM32_APP_FORMAT_MCUBOOT
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config STM32_OTA_PRIMARY_SLOT_OFFSET
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hex "MCUboot application image primary slot offset"
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hex "Application image primary slot offset"
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default "0x40000"
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config STM32_OTA_SECONDARY_SLOT_OFFSET
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hex "MCUboot application image secondary slot offset"
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hex "Application image secondary slot offset"
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default "0xc0000" if STM32_APP_FORMAT_NXBOOT
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default "0x100000"
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config STM32_OTA_TERTIARY_SLOT_OFFSET
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hex "Application image tertiary slot offset"
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default "0x140000"
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depends on STM32_APP_FORMAT_NXBOOT
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config STM32_OTA_SCRATCH_OFFSET
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hex "MCUboot scratch partition offset"
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default "0x1c0000"
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depends on STM32_APP_FORMAT_MCUBOOT
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config STM32_OTA_SLOT_SIZE
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hex "MCUboot application image slot size (in bytes)"
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hex "Application image slot size (in bytes)"
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default "0x80000" if STM32_APP_FORMAT_NXBOOT
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default "0xc0000"
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config STM32_OTA_SCRATCH_SIZE
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hex "MCUboot scratch partition size (in bytes)"
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default "0x40000"
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depends on STM32_APP_FORMAT_MCUBOOT
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endif # STM32_PROGMEM_OTA_PARTITION
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endif # STM32_HAVE_OTA_PARTITION
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@@ -0,0 +1,65 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_STANDARD_SERIAL is not set
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# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-h743zi"
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CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y
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CONFIG_ARCH_CHIP="stm32h7"
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CONFIG_ARCH_CHIP_STM32H743ZI=y
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CONFIG_ARCH_CHIP_STM32H7=y
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CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_DTCM=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_BOARDCTL_RESET=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BOOT_NXBOOT=y
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_FAT_LCNAMES=y
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CONFIG_FS_FAT=y
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CONFIG_FS_PROCFS=y
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CONFIG_FS_PROCFS_REGISTER=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBM=y
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CONFIG_LINE_MAX=64
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CONFIG_MM_REGIONS=4
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_MOTD=y
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CONFIG_NSH_MOTD_STRING="Welcome to NuttX from nxboot, this is the FIRST firmware."
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CONFIG_NSH_READLINE=y
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CONFIG_NXBOOT_HEADER_SIZE=0x400
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=245760
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_LPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SPI=y
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CONFIG_START_DAY=28
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2021
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CONFIG_STM32H7_FLASH_OVERRIDE_I=y
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CONFIG_STM32H7_USART3=y
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CONFIG_STM32_APP_FORMAT_NXBOOT=y
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CONFIG_STM32_PROGMEM_OTA_PARTITION=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_USART3_SERIAL_CONSOLE=y
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@@ -0,0 +1,70 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="nucleo-h743zi"
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CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y
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CONFIG_ARCH_CHIP="stm32h7"
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CONFIG_ARCH_CHIP_STM32H743ZI=y
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CONFIG_ARCH_CHIP_STM32H7=y
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CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_DTCM=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_BOARDCTL_RESET=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BOOT_NXBOOT=y
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DRVR_INVALIDATE=y
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CONFIG_DRVR_READAHEAD=y
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CONFIG_DRVR_WRITEBUFFER=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_FAT_LCNAMES=y
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CONFIG_FS_FAT=y
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CONFIG_FS_PROCFS=y
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CONFIG_FS_PROCFS_REGISTER=y
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CONFIG_FTL_WRITEBUFFER=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_INIT_ENTRYPOINT="nxboot_loader_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LIBM=y
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CONFIG_LINE_MAX=64
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CONFIG_MM_IOB=y
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CONFIG_MM_REGIONS=4
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LIBRARY=y
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CONFIG_NSH_MOTD=y
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CONFIG_NSH_MOTD_STRING="Welcome to NuttX nxboot Loader!"
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CONFIG_NSH_READLINE=y
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CONFIG_NXBOOT_BOOTLOADER=y
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CONFIG_NXBOOT_HEADER_SIZE=0x400
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=245760
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_LPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SPI=y
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CONFIG_START_DAY=28
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2021
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CONFIG_STM32H7_FLASH_OVERRIDE_I=y
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CONFIG_STM32H7_USART3=y
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CONFIG_STM32_APP_FORMAT_NXBOOT=y
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CONFIG_STM32_PROGMEM_OTA_PARTITION=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_USART3_SERIAL_CONSOLE=y
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CONFIG_WQUEUE_NOTIFIER=y
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@@ -30,6 +30,12 @@ ifeq ($(CONFIG_STM32_APP_FORMAT_MCUBOOT),y)
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else
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LDSCRIPT = flash-mcuboot-app.ld
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endif
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else ifeq ($(CONFIG_STM32_APP_FORMAT_NXBOOT),y)
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ifeq ($(CONFIG_NXBOOT_BOOTLOADER),y)
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LDSCRIPT = flash-nxboot-loader.ld
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else
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LDSCRIPT = flash-nxboot-app.ld
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endif
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else
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LDSCRIPT = flash.ld
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endif
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@@ -0,0 +1,225 @@
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/****************************************************************************
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* boards/arm/stm32h7/nucleo-h743zi/scripts/flash-nxboot-app.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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/* The STM32H743ZI has 2048Kb of main FLASH memory. The flash memory is
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* partitioned into a User Flash memory and a System Flash memory. Each
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* of these memories has two banks:
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*
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* 1) User Flash memory:
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*
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* Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each
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* Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each
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*
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* 2) System Flash memory:
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*
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* Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector
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* Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector
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*
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* 3) User option bytes for user configuration, only in Bank 1.
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*
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* In the STM32H743ZI, two different boot spaces can be selected through
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* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
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* BOOT_ADD1 option bytes:
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*
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* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
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* ST programmed value: Flash memory at 0x0800:0000
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* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
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* ST programmed value: System bootloader at 0x1FF0:0000
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*
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* TODO: Check next paragraph with nucleo schematics
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*
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* NuttX does not modify these option bytes. On the unmodified NUCLEO-H743ZI
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* board, the BOOT0 pin is at ground so by default, the STM32 will boot
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* to address 0x0800:0000 in FLASH.
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*
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* The STM32H743ZI also has 1024Kb of data SRAM.
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* SRAM is split up into several blocks and into three power domains:
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*
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* 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
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* 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus
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*
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* 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000
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*
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* The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit
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* DTCM ports. The DTCM-RAM could be used for critical real-time
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* data, such as interrupt service routines or stack / heap memory.
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* Both DTCM-RAMs can be used in parallel (for load/store operations)
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* thanks to the Cortex-M7 dual issue capability.
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*
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* 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000
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*
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* This RAM is connected to ITCM 64-bit interface designed for
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* execution of critical real-times routines by the CPU.
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*
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* 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA
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* through D1 domain AXI bus matrix
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*
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* 2.1) 512Kb of SRAM beginning at address 0x2400:0000
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*
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* 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA
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* through D2 domain AHB bus matrix
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*
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* 3.1) 128Kb of SRAM1 beginning at address 0x3000:0000
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* 3.2) 128Kb of SRAM2 beginning at address 0x3002:0000
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* 3.3) 32Kb of SRAM3 beginning at address 0x3004:0000
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*
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* SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000
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*
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* 4) AHB SRAM (D3 domain) accessible by most of system masters
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* through D3 domain AHB bus matrix
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*
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* 4.1) 64Kb of SRAM4 beginning at address 0x3800:0000
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* 4.1) 4Kb of backup RAM beginning at address 0x3880:0000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address range.
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*
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* The nxboot application image starts at 0x08040400, after the bootloader
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* region (256K) and the nxboot image header (1K). The application slot
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* size is 512K - 1K to account for the header.
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*
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* Keep these fixed addresses in sync with the board's nxboot partition
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* layout. On this board the application vector table is linked at
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* 0x08040400, so the nxboot header size must remain 0x400.
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*/
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#if CONFIG_STM32_OTA_PRIMARY_SLOT_OFFSET != 0x40000
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# error "CONFIG_STM32_OTA_PRIMARY_SLOT_OFFSET must be 0x40000 for flash-nxboot-app.ld"
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#endif
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#if CONFIG_STM32_OTA_SLOT_SIZE != 0x80000
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# error "CONFIG_STM32_OTA_SLOT_SIZE must be 0x80000 for flash-nxboot-app.ld"
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#endif
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#if CONFIG_NXBOOT_HEADER_SIZE != 0x400
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# error "CONFIG_NXBOOT_HEADER_SIZE must be 0x400 for flash-nxboot-app.ld"
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#endif
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MEMORY
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{
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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flash (rx) : ORIGIN = 0x08040400, LENGTH = 512K - 1K
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dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
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sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
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sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
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sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
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sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
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sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
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bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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}
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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ENTRY(_stext)
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SECTIONS
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{
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.text :
|
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{
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_stext = ABSOLUTE(.);
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*(.vectors)
|
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*(.text .text.*)
|
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*(.fixup)
|
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*(.gnu.warning)
|
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*(.rodata .rodata.*)
|
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*(.gnu.linkonce.t.*)
|
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*(.glue_7)
|
||||
*(.glue_7t)
|
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*(.got)
|
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
|
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_etext = ABSOLUTE(.);
|
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} > flash
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||||
|
||||
.init_section :
|
||||
{
|
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_sinit = ABSOLUTE(.);
|
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KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
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KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
|
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_einit = ABSOLUTE(.);
|
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} > flash
|
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|
||||
.ARM.extab :
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{
|
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*(.ARM.extab*)
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} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
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.ARM.exidx :
|
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{
|
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*(.ARM.exidx*)
|
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} > flash
|
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__exidx_end = ABSOLUTE(.);
|
||||
|
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_eronly = ABSOLUTE(.);
|
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|
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.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
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*(.gnu.linkonce.d.*)
|
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CONSTRUCTORS
|
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. = ALIGN(4);
|
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_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss :
|
||||
{
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = ABSOLUTE(.);
|
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} > sram
|
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|
||||
/* Emit the the D3 power domain section for locating BDMA data
|
||||
*
|
||||
* Static data with locate_data(".sram4") will be located
|
||||
* at start of SRAM4; the rest of SRAM4 will be added to the heap.
|
||||
*/
|
||||
|
||||
.sram4_reserve (NOLOAD) :
|
||||
{
|
||||
*(.sram4)
|
||||
. = ALIGN(4);
|
||||
_sram4_heap_start = ABSOLUTE(.);
|
||||
} > sram4
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
@@ -0,0 +1,223 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h7/nucleo-h743zi/scripts/flash-nxboot-loader.ld
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* The STM32H743ZI has 2048Kb of main FLASH memory. The flash memory is
|
||||
* partitioned into a User Flash memory and a System Flash memory. Each
|
||||
* of these memories has two banks:
|
||||
*
|
||||
* 1) User Flash memory:
|
||||
*
|
||||
* Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each
|
||||
* Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each
|
||||
*
|
||||
* 2) System Flash memory:
|
||||
*
|
||||
* Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector
|
||||
* Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector
|
||||
*
|
||||
* 3) User option bytes for user configuration, only in Bank 1.
|
||||
*
|
||||
* In the STM32H743ZI, two different boot spaces can be selected through
|
||||
* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
|
||||
* BOOT_ADD1 option bytes:
|
||||
*
|
||||
* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
|
||||
* ST programmed value: Flash memory at 0x0800:0000
|
||||
* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
|
||||
* ST programmed value: System bootloader at 0x1FF0:0000
|
||||
*
|
||||
* TODO: Check next paragraph with nucleo schematics
|
||||
*
|
||||
* NuttX does not modify these option bytes. On the unmodified NUCLEO-H743ZI
|
||||
* board, the BOOT0 pin is at ground so by default, the STM32 will boot
|
||||
* to address 0x0800:0000 in FLASH.
|
||||
*
|
||||
* The STM32H743ZI also has 1024Kb of data SRAM.
|
||||
* SRAM is split up into several blocks and into three power domains:
|
||||
*
|
||||
* 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
|
||||
* 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus
|
||||
*
|
||||
* 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000
|
||||
*
|
||||
* The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit
|
||||
* DTCM ports. The DTCM-RAM could be used for critical real-time
|
||||
* data, such as interrupt service routines or stack / heap memory.
|
||||
* Both DTCM-RAMs can be used in parallel (for load/store operations)
|
||||
* thanks to the Cortex-M7 dual issue capability.
|
||||
*
|
||||
* 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000
|
||||
*
|
||||
* This RAM is connected to ITCM 64-bit interface designed for
|
||||
* execution of critical real-times routines by the CPU.
|
||||
*
|
||||
* 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA
|
||||
* through D1 domain AXI bus matrix
|
||||
*
|
||||
* 2.1) 512Kb of SRAM beginning at address 0x2400:0000
|
||||
*
|
||||
* 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA
|
||||
* through D2 domain AHB bus matrix
|
||||
*
|
||||
* 3.1) 128Kb of SRAM1 beginning at address 0x3000:0000
|
||||
* 3.2) 128Kb of SRAM2 beginning at address 0x3002:0000
|
||||
* 3.3) 32Kb of SRAM3 beginning at address 0x3004:0000
|
||||
*
|
||||
* SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000
|
||||
*
|
||||
* 4) AHB SRAM (D3 domain) accessible by most of system masters
|
||||
* through D3 domain AHB bus matrix
|
||||
*
|
||||
* 4.1) 64Kb of SRAM4 beginning at address 0x3800:0000
|
||||
* 4.1) 4Kb of backup RAM beginning at address 0x3880:0000
|
||||
*
|
||||
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
|
||||
* where the code expects to begin execution by jumping to the entry point in
|
||||
* the 0x0800:0000 address range.
|
||||
*
|
||||
* The nxboot bootloader occupies the first 256K of flash (sectors 0-1).
|
||||
* Application image slots begin at 0x08040000.
|
||||
*
|
||||
* Keep the nxboot loader configuration in sync with the fixed board image
|
||||
* layout used by flash-nxboot-app.ld.
|
||||
*/
|
||||
|
||||
#if CONFIG_STM32_OTA_PRIMARY_SLOT_OFFSET != 0x40000
|
||||
# error "CONFIG_STM32_OTA_PRIMARY_SLOT_OFFSET must be 0x40000 for flash-nxboot-loader.ld"
|
||||
#endif
|
||||
|
||||
#if CONFIG_STM32_OTA_SLOT_SIZE != 0x80000
|
||||
# error "CONFIG_STM32_OTA_SLOT_SIZE must be 0x80000 for flash-nxboot-loader.ld"
|
||||
#endif
|
||||
|
||||
#if CONFIG_NXBOOT_HEADER_SIZE != 0x400
|
||||
# error "CONFIG_NXBOOT_HEADER_SIZE must be 0x400 for flash-nxboot-loader.ld"
|
||||
#endif
|
||||
|
||||
MEMORY
|
||||
{
|
||||
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
|
||||
sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
|
||||
sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
|
||||
sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
|
||||
sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
|
||||
sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
|
||||
bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
EXTERN(_vectors)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section :
|
||||
{
|
||||
_sinit = ABSOLUTE(.);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss :
|
||||
{
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/* Emit the the D3 power domain section for locating BDMA data
|
||||
*
|
||||
* Static data with locate_data(".sram4") will be located
|
||||
* at start of SRAM4; the rest of SRAM4 will be added to the heap.
|
||||
*/
|
||||
|
||||
.sram4_reserve (NOLOAD) :
|
||||
{
|
||||
*(.sram4)
|
||||
. = ALIGN(4);
|
||||
_sram4_heap_start = ABSOLUTE(.);
|
||||
} > sram4
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
@@ -116,9 +116,23 @@ target_sources(board PRIVATE ${SRCS})
|
||||
|
||||
if(CONFIG_STM32_APP_FORMAT_MCUBOOT)
|
||||
if(CONFIG_MCUBOOT_BOOTLOADER)
|
||||
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash-mcuboot-loader.ld")
|
||||
set_property(
|
||||
GLOBAL PROPERTY LD_SCRIPT
|
||||
"${NUTTX_BOARD_DIR}/scripts/flash-mcuboot-loader.ld")
|
||||
else()
|
||||
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash-mcuboot-app.ld")
|
||||
set_property(
|
||||
GLOBAL PROPERTY LD_SCRIPT
|
||||
"${NUTTX_BOARD_DIR}/scripts/flash-mcuboot-app.ld")
|
||||
endif()
|
||||
elseif(CONFIG_STM32_APP_FORMAT_NXBOOT)
|
||||
if(CONFIG_NXBOOT_BOOTLOADER)
|
||||
set_property(
|
||||
GLOBAL PROPERTY LD_SCRIPT
|
||||
"${NUTTX_BOARD_DIR}/scripts/flash-nxboot-loader.ld")
|
||||
else()
|
||||
set_property(
|
||||
GLOBAL PROPERTY LD_SCRIPT
|
||||
"${NUTTX_BOARD_DIR}/scripts/flash-nxboot-app.ld")
|
||||
endif()
|
||||
else()
|
||||
set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
|
||||
@@ -128,5 +142,5 @@ if(NOT CONFIG_BUILD_FLAT)
|
||||
add_subdirectory(${NUTTX_BOARD_DIR}/kernel)
|
||||
set_property(
|
||||
GLOBAL PROPERTY LD_SCRIPT_USER ${NUTTX_BOARD_DIR}/scripts/memory.ld
|
||||
${NUTTX_BOARD_DIR}/scripts/user-space.ld)
|
||||
${NUTTX_BOARD_DIR}/scripts/user-space.ld)
|
||||
endif()
|
||||
|
||||
@@ -96,6 +96,7 @@ static int init_ota_partitions(void);
|
||||
static struct mtd_dev_s *g_progmem_mtd;
|
||||
|
||||
#if defined(CONFIG_STM32_PROGMEM_OTA_PARTITION)
|
||||
|
||||
static const struct ota_partition_s g_ota_partition_table[] =
|
||||
{
|
||||
{
|
||||
@@ -108,11 +109,19 @@ static const struct ota_partition_s g_ota_partition_table[] =
|
||||
.size = CONFIG_STM32_OTA_SLOT_SIZE,
|
||||
.devpath = CONFIG_STM32_OTA_SECONDARY_SLOT_DEVPATH
|
||||
},
|
||||
#ifdef CONFIG_STM32_APP_FORMAT_NXBOOT
|
||||
{
|
||||
.offset = CONFIG_STM32_OTA_TERTIARY_SLOT_OFFSET,
|
||||
.size = CONFIG_STM32_OTA_SLOT_SIZE,
|
||||
.devpath = CONFIG_STM32_OTA_TERTIARY_SLOT_DEVPATH
|
||||
}
|
||||
#else
|
||||
{
|
||||
.offset = CONFIG_STM32_OTA_SCRATCH_OFFSET,
|
||||
.size = CONFIG_STM32_OTA_SCRATCH_SIZE,
|
||||
.devpath = CONFIG_STM32_OTA_SCRATCH_DEVPATH
|
||||
}
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user