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Merged nuttx/arch into master

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This commit is contained in:
Pierre-noel Bouteville
2015-09-03 12:06:38 +02:00
parent a7a52252a8 aff3dbda88
commit 0fb41dd4e7
146 changed files with 12747 additions and 824 deletions
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arch/arm/Kconfig
+1
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@@ -227,6 +227,7 @@ config ARCH_CHIP_MOXART
bool "MoxART"
select ARCH_ARM7TDMI
select ARCH_HAVE_RESET
select ARCH_HAVE_SERIAL_TERMIOS
---help---
MoxART family
arch/arm/include/lpc43xx/chip.h
+1 -1
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@@ -566,7 +566,7 @@
#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN
#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT
#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX
#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_INCR
#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_STEP
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
arch/arm/include/moxart/irq.h
+3 -2
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@@ -81,7 +81,8 @@ extern "C"
#define IRQ_SYSTIMER 19
#define NR_IRQS 32
#define VIRQ_START 32
#define NR_IRQS (VIRQ_START+2)
#endif /* __ARCH_ARM_INCLUDE_MOXART_IRQ_H */
arch/arm/include/sama5/chip.h
+51 -2
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@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/include/sama5/chip.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,49 @@
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* SAMA5D2 Family
*
* SAMA5D21 SAMA5D22 SAMA5D23 SAMA5D24 SAMA5D26 SAMA5D27 SAMA5D28
* ------------------------- --------- --------- --------- --------- --------- --------- ---------
* Pin Count 196 196 196 256 289 289 289
* Max. Operating Frequency 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz 500 MHz
* CPU Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5
* Max I/O Pins 72 72 72 105 128 128 128
* USB Transceiver 1 1 1 1 1 1 1
* USB Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed
* USB Interface 2 2 2 3 3 3 3
* SPI 6 6 6 7 7 7 7
* QuadSPI 2 2 2 2 2 2 2
* TWIHS (I2C) 6 6 6 7 7 7 7
* UART 9 9 9 10 10 10 10
* CAN - 1 1 - - 2 2
* SDIO/SD/MMC 1 1 1 2 2 2 2
* I2SC 2 2 2 2 2 2 2
* SSC 2 2 2 2 2 2 2
* Class D 1 1 1 2 2 2 2
* PDMIC 1 1 1 2 2 2 2
* Camera Interface 1 1 1 1 1 1 1
* ADC Inputs 5 5 5 12 12 12 12
* AESB - 1 1 1 - 1 1
* SRAM (Kbytes) 128 128 128 128 128 128 128
* DDR Bus 16-bit 16-bit 16-bit 16/32-bit 16/32-bit 16/32-bit 16/32-bit
* Timers 6 6 6 6 6 6 6
* Tamper pins 6 6 6 2 8 8 8
* Packages BGA196 BGA196 BGA196 BGA256 BGA289 BGA289 BGA289
*/
#if defined(CONFIG_ARCH_CHIP_ATSAMA5D21) || defined(CONFIG_ARCH_CHIP_ATSAMA5D22) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D22) || defined(CONFIG_ARCH_CHIP_ATSAMA5D23) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D24) || defined(CONFIG_ARCH_CHIP_ATSAMA5D26) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D27) || defined(CONFIG_ARCH_CHIP_ATSAMA5D28)
# define ATSAMA5D2 1 /* SAMA5D2 family */
# undef ATSAMA5D3 /* Not SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) XDMA controllers */
# define SAM_NDMACHAN 16 /* (16) DMA channels per XDMA controller */
/* SAMA5D3 Family
*
* ATSAMA5D31 ATSAMA5D33 ATSAMA5D34 ATSAMA5D35 ATSAMA5D36
@@ -91,7 +134,8 @@
* Packages LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A
*/
#if defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@@ -99,6 +143,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D33)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@@ -106,6 +151,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D34)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@@ -113,6 +159,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D35)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@@ -120,6 +167,7 @@
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D36)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
@@ -141,6 +189,7 @@
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D43) || defined(CONFIG_ARCH_CHIP_ATSAMA5D44)
# undef ATSAMA5D2 /* Not SAMA5D2 family */
# undef ATSAMA5D3 /* Not SAMA5D3 family */
# define ATSAMA5D4 1 /* SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
arch/arm/include/sama5/irq.h
+3 -1
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@@ -53,7 +53,9 @@
/* Chip-Specific External interrupts */
#if defined(ATSAMA5D3)
#if defined(ATSAMA5D2)
# include <arch/sama5/sama5d2_irq.h>
#elif defined(ATSAMA5D3)
# include <arch/sama5/sama5d3_irq.h>
#elif defined(ATSAMA5D4)
# include <arch/sama5/sama5d4_irq.h>
arch/arm/include/sama5/sama5d2_irq.h
+424
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@@ -0,0 +1,424 @@
/****************************************************************************************
* arch/arm/include/sama5/sama5d2_irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D2_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D2_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAMA5D3 Peripheral Identifiers */
#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */
/* 2 Reserved */
#define SAM_PID_ARM (2) /* Performance Monitor Unit */
#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */
#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */
#define SAM_PID_EMAC0 (5) /* Ethernet MAC 0 */
#define SAM_PID_XDMAC0 (6) /* DMA Controller 0 */
#define SAM_PID_XDMAC1 (7) /* DMA Controller 1 */
#define SAM_PID_ICM (8) /* Integrity Check Monitor */
#define SAM_PID_AES (9) /* Advanced Encryption Standard */
#define SAM_PID_AESB (10) /* AES bridge */
#define SAM_PID_TDES (11) /* Triple Data Encryption Standard */
#define SAM_PID_SHA (12) /* Secure Hash Algorithm */
#define SAM_PID_MPDDRC (13) /* MPDDR controller */
#define SAM_PID_MATRIX1 (14) /* H32MX, 32-bit AHB Matrix */
#define SAM_PID_MATRIX0 (15) /* H64MX, 64-bit AHB Matrix */
#define SAM_PID_SECUMOD (16) /* Secure Module */
#define SAM_PID_HSMC (17) /* Multi-bit ECC Interrupt */
#define SAM_PID_PIOA (18) /* Parallel I/O Controller A */
#define SAM_PID_FLEXCOM0 (19) /* FLEXCOM 0 */
#define SAM_PID_FLEXCOM1 (20) /* FLEXCOM 1 */
#define SAM_PID_FLEXCOM2 (21) /* FLEXCOM 2 */
#define SAM_PID_FLEXCOM3 (22) /* FLEXCOM 3 */
#define SAM_PID_FLEXCOM4 (23) /* FLEXCOM 4 */
#define SAM_PID_UART0 (24) /* UART 0 */
#define SAM_PID_UART1 (25) /* UART 1 */
#define SAM_PID_UART2 (26) /* UART 2 */
#define SAM_PID_UART3 (27) /* UART 3 */
#define SAM_PID_UART4 (28) /* UART 4 */
#define SAM_PID_TWI0 (29) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (30) /* Two-Wire Interface 1 */
#define SAM_PID_SDMMC0 (31) /* Secure Data Memory Card Controller 0 */
#define SAM_PID_SDMMC1 (32) /* Secure Data Memory Card Controller 1 */
#define SAM_PID_SPI0 (33) /* Serial Peripheral Interface 0 */
#define SAM_PID_SPI1 (34) /* Serial Peripheral Interface 1 */
#define SAM_PID_TC0 (35) /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_PID_TC1 (36) /* Timer Counter 1 (ch. 3, 4, 5) */
/* 37 Reserved */
#define SAM_PID_PWM (38) /* Pulse Width Modulation Controller */
/* 39 Reserved */
#define SAM_PID_ADC (40) /* Touch Screen ADC Controller */
#define SAM_PID_UHPHS (41) /* USB Host High Speed */
#define SAM_PID_UDPHS (42) /* USB Device High Speed */
#define SAM_PID_SSC0 (43) /* Synchronous Serial Controller 0 */
#define SAM_PID_SSC1 (44) /* Synchronous Serial Controller 1 */
#define SAM_PID_LCDC (45) /* LCD Controller */
#define SAM_PID_ISC (46) /* Image Sensor Controller */
#define SAM_PID_TRNG (47) /* True Random Number Generator */
#define SAM_PID_PDMIC (48) /* Pulse Density Modulation Interface Controller */
#define SAM_PID_IRQID (49) /* IRQ Interrupt ID */
#define SAM_PID_SFC (50) /* Fuse Controller */
#define SAM_PID_SECURAM (51) /* Secured RAM */
#define SAM_PID_QSPI0 (52) /* QuadSPI 0 */
#define SAM_PID_QSPI1 (53) /* QuadSPI 1 */
#define SAM_PID_I2SC0 (54) /* Inter-IC Sound Controller 0 */
#define SAM_PID_I2SC1 (55) /* Inter-IC Sound Controller 1 */
#define SAM_PID_MCAN00 (56) /* MCAN controller 0, Interrupt 0 */
#define SAM_PID_MCAN10 (57) /* MCAN controller 1, Interrupt 0 */
/* 58 Reserved */
#define SAM_PID_CLASSD (59) /* Audio Class D Amplifier */
#define SAM_PID_SFR (60) /* Special Function Register */
#define SAM_PID_SAIC (61) /* Secured Advanced Interrupt Controller */
#define SAM_PID_AIC (62) /* Advanced Interrupt Controller */
#define SAM_PID_L2CC (63) /* L2 Cache Controller */
#define SAM_PID_MCAN01 (64) /* MCAN controller 0, Interrupt 1 */
#define SAM_PID_MCAN11 (65) /* MCAN controller 1, Interrupt 1 */
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
#define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */
#define SAM_PID_PIOB (68) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (69) /* Parallel I/O Controller C */
#define SAM_PID_PIOD (70) /* Parallel I/O Controller D */
#define SAM_PID_SDMMC0T (71) /* Secure Data Memory Card Controller 0 */
#define SAM_PID_SDMMC1T (72) /* Secure Data Memory Card Controller 1 */
/* 73 Reserved */
#define SAM_PID_SYS (74) /* System Controller Interrupt PMC, RTC, RSTC */
#define SAM_PID_ACC (75) /* Analog Comparator */
#define SAM_PID_RXLP (76) /* UART Low-Power */
#define SAM_PID_SFRBU (77) /* Special Function Register BackUp */
#define SAM_PID_CHIPID (78) /* Chip ID */
#define SAM_NPIDS (79)
/* External interrupts vectors numbers (same as peripheral ID) */
#define SAM_IRQ_FIQ SAM_PID_FIQ /* Advanced Interrupt Controller FIQ */
#define SAM_IRQ_ARM SAM_PID_ARM /* Performance Monitor Unit */
#define SAM_IRQ_PIT SAM_PID_PIT /* Periodic Interval Timer Interrupt */
#define SAM_IRQ_WDT SAM_PID_WDT /* Watchdog timer Interrupt */
#define SAM_IRQ_EMAC0 SAM_PID_EMAC0 /* Ethernet MAC 0 */
#define SAM_IRQ_XDMAC0 SAM_PID_XDMAC0 /* DMA Controller 0 */
#define SAM_IRQ_XDMAC1 SAM_PID_XDMAC1 /* DMA Controller 1 */
#define SAM_IRQ_ICM SAM_PID_ICM /* Integrity Check Monitor */
#define SAM_IRQ_AES SAM_PID_AES /* Advanced Encryption Standard */
#define SAM_IRQ_AESB SAM_PID_AESB /* AES bridge */
#define SAM_IRQ_TDES SAM_PID_TDES /* Triple Data Encryption Standard */
#define SAM_IRQ_SHA SAM_PID_SHA /* Secure Hash Algorithm */
#define SAM_IRQ_MPDDRC SAM_PID_MPDDRC /* MPDDR controller */
#define SAM_IRQ_MATRIX1 SAM_PID_MATRIX1 /* H32MX, 32-bit AHB Matrix */
#define SAM_IRQ_MATRIX0 SAM_PID_MATRIX0 /* H64MX, 64-bit AHB Matrix */
#define SAM_IRQ_SECUMOD SAM_PID_SECUMOD /* Secure Module */
#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */
#define SAM_IRQ_FLEXCOM0 SAM_PID_FLEXCOM0 /* FLEXCOM 0 */
#define SAM_IRQ_FLEXCOM1 SAM_PID_FLEXCOM1 /* FLEXCOM 1 */
#define SAM_IRQ_FLEXCOM2 SAM_PID_FLEXCOM2 /* FLEXCOM 2 */
#define SAM_IRQ_FLEXCOM3 SAM_PID_FLEXCOM3 /* FLEXCOM 3 */
#define SAM_IRQ_FLEXCOM4 SAM_PID_FLEXCOM4 /* FLEXCOM 4 */
#define SAM_IRQ_UART0 SAM_PID_UART0 /* UART 0 */
#define SAM_IRQ_UART1 SAM_PID_UART1 /* UART 1 */
#define SAM_IRQ_UART2 SAM_PID_UART2 /* UART 2 */
#define SAM_IRQ_UART3 SAM_PID_UART3 /* UART 3 */
#define SAM_IRQ_UART4 SAM_PID_UART4 /* UART 4 */
#define SAM_IRQ_TWI0 SAM_PID_TWI0 /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 SAM_PID_TWI1 /* Two-Wire Interface 1 */
#define SAM_IRQ_SDMMC0 SAM_PID_SDMMC0 /* Secure Data Memory Card Controller 0 */
#define SAM_IRQ_SDMMC1 SAM_PID_SDMMC1 /* Secure Data Memory Card Controller 1 */
#define SAM_IRQ_SPI0 SAM_PID_SPI0 /* Serial Peripheral Interface 0 */
#define SAM_IRQ_SPI1 SAM_PID_SPI1 /* Serial Peripheral Interface 1 */
#define SAM_IRQ_TC0 SAM_PID_TC0 /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_IRQ_TC1 SAM_PID_TC1 /* Timer Counter 1 (ch. 3, 4, 5) */
#define SAM_IRQ_PWM SAM_PID_PWM /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC SAM_PID_ADC /* Touch Screen ADC Controller */
#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */
#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */
#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */
#define SAM_IRQ_SSC1 SAM_PID_SSC1 /* Synchronous Serial Controller 1 */
#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */
#define SAM_IRQ_ISC SAM_PID_ISC /* Image Sensor Controller */
#define SAM_IRQ_TRNG SAM_PID_TRNG /* True Random Number Generator */
#define SAM_IRQ_PDMIC SAM_PID_PDMIC /* Pulse Density Modulation Interface Controller */
#define SAM_IRQ_IRQID SAM_PID_IRQID /* IRQ Interrupt ID */
#define SAM_IRQ_SFC SAM_PID_SFC /* Fuse Controller */
#define SAM_IRQ_SECURAM SAM_PID_SECURAM /* Secured RAM */
#define SAM_IRQ_QSPI0 SAM_PID_QSPI0 /* QuadSPI 0 */
#define SAM_IRQ_QSPI1 SAM_PID_QSPI1 /* QuadSPI 1 */
#define SAM_IRQ_I2SC0 SAM_PID_I2SC0 /* Inter-IC Sound Controller 0 */
#define SAM_IRQ_I2SC1 SAM_PID_I2SC1 /* Inter-IC Sound Controller 1 */
#define SAM_IRQ_MCAN00 SAM_PID_MCAN00 /* MCAN controller 0, Interrupt 0 */
#define SAM_IRQ_MCAN10 SAM_PID_MCAN10 /* MCAN controller 1, Interrupt 0 */
#define SAM_IRQ_CLASSD SAM_PID_CLASSD /* Audio Class D Amplifier */
/* Special Function Register (no interrupt) */
/* Secured Advanced Interrupt Controller (no interrupt) */
/* Advanced Interrupt Controller (no interrupt) */
#define SAM_IRQ_L2CC SAM_PID_L2CC /* L2 Cache Controller */
#define SAM_IRQ_MCAN01 SAM_PID_MCAN01 /* MCAN controller 0, Interrupt 1 */
#define SAM_IRQ_MCAN11 SAM_PID_MCAN11 /* MCAN controller 1, Interrupt 1 */
#define SAM_IRQ_EMACQ1 SAM_PID_EMACQ1 /* EMAC Queue 1 Interrupt */
#define SAM_IRQ_EMACQ2 SAM_PID_EMACQ2 /* EMAC Queue 2 Interrupt */
#define SAM_IRQ_PIOB SAM_PID_PIOB /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC SAM_PID_PIOC /* Parallel I/O Controller C */
#define SAM_IRQ_PIOD SAM_PID_PIOD /* Parallel I/O Controller D */
#define SAM_IRQ_SDMMC0T SAM_PID_SDMMC0T /* Secure Data Memory Card Controller 0 */
#define SAM_IRQ_SDMMC1T SAM_PID_SDMMC1T /* Secure Data Memory Card Controller 1 */
#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC, RTC, RSTC */
#define SAM_IRQ_ACC SAM_PID_ACC /* Analog Comparator */
#define SAM_IRQ_RXLP SAM_PID_RXLP /* UART Low-Power */
/* Special Function Register BackUp (no interrupt) */
/* Chip ID (no interrupt) */
#define SAM_IRQ_NINT (SAM_PID_RXLP + 1)
/* PIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */
#ifdef CONFIG_SAMA5_PIOA_IRQ
# define SAM_IRQ_PIOA_PINS (SAM_IRQ_NINT)
# define SAM_IRQ_PA0 (SAM_IRQ_PIOA_PINS+0) /* PIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_PIOA_PINS+1) /* PIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_PIOA_PINS+2) /* PIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_PIOA_PINS+3) /* PIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_PIOA_PINS+4) /* PIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_PIOA_PINS+5) /* PIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_PIOA_PINS+6) /* PIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_PIOA_PINS+7) /* PIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_PIOA_PINS+8) /* PIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_PIOA_PINS+9) /* PIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_PIOA_PINS+10) /* PIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_PIOA_PINS+11) /* PIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_PIOA_PINS+12) /* PIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_PIOA_PINS+13) /* PIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_PIOA_PINS+14) /* PIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_PIOA_PINS+15) /* PIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_PIOA_PINS+16) /* PIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_PIOA_PINS+17) /* PIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_PIOA_PINS+18) /* PIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_PIOA_PINS+19) /* PIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_PIOA_PINS+20) /* PIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_PIOA_PINS+21) /* PIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_PIOA_PINS+22) /* PIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_PIOA_PINS+23) /* PIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_PIOA_PINS+24) /* PIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_PIOA_PINS+25) /* PIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_PIOA_PINS+26) /* PIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_PIOA_PINS+27) /* PIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_PIOA_PINS+28) /* PIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_PIOA_PINS+29) /* PIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_PIOA_PINS+30) /* PIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_PIOA_PINS+31) /* PIOA, PIN 31 */
# define SAM_NPIOAIRQS 32
#else
# define SAM_NPIOAIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOB_IRQ
# define SAM_IRQ_PIOB_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_PIOB_PINS+0) /* PIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_PIOB_PINS+1) /* PIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_PIOB_PINS+2) /* PIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_PIOB_PINS+3) /* PIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_PIOB_PINS+4) /* PIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_PIOB_PINS+5) /* PIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_PIOB_PINS+6) /* PIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_PIOB_PINS+7) /* PIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_PIOB_PINS+8) /* PIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_PIOB_PINS+9) /* PIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_PIOB_PINS+10) /* PIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_PIOB_PINS+11) /* PIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_PIOB_PINS+12) /* PIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_PIOB_PINS+13) /* PIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_PIOB_PINS+14) /* PIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_PIOB_PINS+15) /* PIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_PIOB_PINS+16) /* PIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_PIOB_PINS+17) /* PIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_PIOB_PINS+18) /* PIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_PIOB_PINS+19) /* PIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_PIOB_PINS+20) /* PIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_PIOB_PINS+21) /* PIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_PIOB_PINS+22) /* PIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_PIOB_PINS+23) /* PIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_PIOB_PINS+24) /* PIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_PIOB_PINS+25) /* PIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_PIOB_PINS+26) /* PIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_PIOB_PINS+27) /* PIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_PIOB_PINS+28) /* PIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_PIOB_PINS+29) /* PIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_PIOB_PINS+30) /* PIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_PIOB_PINS+31) /* PIOB, PIN 31 */
# define SAM_NPIOBIRQS 32
#else
# define SAM_NPIOBIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOC_IRQ
# define SAM_IRQ_PIOC_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_PIOC_PINS+0) /* PIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_PIOC_PINS+1) /* PIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_PIOC_PINS+2) /* PIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_PIOC_PINS+3) /* PIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_PIOC_PINS+4) /* PIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_PIOC_PINS+5) /* PIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_PIOC_PINS+6) /* PIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_PIOC_PINS+7) /* PIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_PIOC_PINS+8) /* PIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_PIOC_PINS+9) /* PIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_PIOC_PINS+10) /* PIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_PIOC_PINS+11) /* PIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_PIOC_PINS+12) /* PIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_PIOC_PINS+13) /* PIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_PIOC_PINS+14) /* PIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_PIOC_PINS+15) /* PIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_PIOC_PINS+16) /* PIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_PIOC_PINS+17) /* PIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_PIOC_PINS+18) /* PIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_PIOC_PINS+19) /* PIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_PIOC_PINS+20) /* PIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_PIOC_PINS+21) /* PIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_PIOC_PINS+22) /* PIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_PIOC_PINS+23) /* PIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_PIOC_PINS+24) /* PIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_PIOC_PINS+25) /* PIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_PIOC_PINS+26) /* PIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_PIOC_PINS+27) /* PIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_PIOC_PINS+28) /* PIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_PIOC_PINS+29) /* PIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_PIOC_PINS+30) /* PIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_PIOC_PINS+31) /* PIOC, PIN 31 */
# define SAM_NPIOCIRQS 32
#else
# define SAM_NPIOCIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOD_IRQ
# define SAM_IRQ_PIOD_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS + \
SAM_NPIOCIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_PIOD_PINS+0) /* PIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_PIOD_PINS+1) /* PIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_PIOD_PINS+2) /* PIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_PIOD_PINS+3) /* PIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_PIOD_PINS+4) /* PIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_PIOD_PINS+5) /* PIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_PIOD_PINS+6) /* PIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_PIOD_PINS+7) /* PIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_PIOD_PINS+8) /* PIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_PIOD_PINS+9) /* PIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_PIOD_PINS+10) /* PIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_PIOD_PINS+11) /* PIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_PIOD_PINS+12) /* PIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_PIOD_PINS+13) /* PIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_PIOD_PINS+14) /* PIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_PIOD_PINS+15) /* PIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_PIOD_PINS+16) /* PIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_PIOD_PINS+17) /* PIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_PIOD_PINS+18) /* PIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_PIOD_PINS+19) /* PIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_PIOD_PINS+20) /* PIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_PIOD_PINS+21) /* PIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_PIOD_PINS+22) /* PIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_PIOD_PINS+23) /* PIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_PIOD_PINS+24) /* PIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_PIOD_PINS+25) /* PIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_PIOD_PINS+26) /* PIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_PIOD_PINS+27) /* PIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_PIOD_PINS+28) /* PIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_PIOD_PINS+29) /* PIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_PIOD_PINS+30) /* PIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_PIOD_PINS+31) /* PIOD, PIN 31 */
# define SAM_NPIODIRQS 32
#else
# define SAM_NPIODIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (SAM_IRQ_NINT + \
SAM_NPIOAIRQS + SAM_NPIOBIRQS + SAM_NPIOCIRQS + \
SAM_NPIODIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D2_IRQ_H */
arch/arm/include/sama5/sama5d4_irq.h
+4 -4
View File
@@ -1,5 +1,5 @@
/****************************************************************************************
* arch/arm/include/sama5/sama5d4x_irq.h
* arch/arm/include/sama5/sama5d4_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -37,8 +37,8 @@
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4_IRQ_H
/****************************************************************************************
* Included Files
@@ -436,4 +436,4 @@ extern "C"
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4_IRQ_H */
arch/arm/include/samv7/chip.h
+2 -2
View File
@@ -86,7 +86,7 @@
# define SAMV7_NTCCHIO 36 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
@@ -142,7 +142,7 @@
# define SAMV7_NTCCHIO 9 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NQSPI 1 /* 1 Quad SPI */
# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
arch/arm/include/stm32/chip.h
+120
View File
@@ -1212,6 +1212,86 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 1 /* (1) SPI1 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */
# define STM32_NI2C 1 /* (1) I2C1 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 25 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 3 /* (2) 12-bit DAC1-3 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */
# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 1 /* (1) SPI1 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */
# define STM32_NI2C 1 /* (1) I2C1 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 3 /* (2) 12-bit DAC1-3 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@@ -1292,6 +1372,46 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 4 /* (4) SPI1-4 */
# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 3 /* (2) I2C1-3 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-F */
# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
arch/arm/src/armv7-a/arm_copyarmstate.c
+1 -1
View File
@@ -76,7 +76,7 @@ void up_copyarmstate(uint32_t *dest, uint32_t *src)
{
int i;
/* In the Cortex-M3 model, the state is copied from the stack to the TCB,
/* In the Cortex-M model, the state is copied from the stack to the TCB,
* but only a reference is passed to get the state from the TCB. So the
* following check avoids copying the TCB save area onto itself:
*/
arch/arm/src/armv7-m/up_ramvec_initialize.c
+16 -1
View File
@@ -56,6 +56,21 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Alignment ****************************************************************/
/* Per the ARMv7M Architecture reference manual, the NVIC vector table
* requires 7-bit address alignment (i.e, bits 0-6 of the address of the
* vector table must be zero). In this case alignment to a 128 byte address
* boundary is sufficient.
*
* Some parts, such as the LPC17xx family, require alignment to a 256 byte
* address boundary. Any other unusual alignment requirements for the vector
* can be specified for a given architecture be redefining
* NVIC_VECTAB_TBLOFF_MASK in the chip-specific chip.h header file for the
* appropriate mask.
*/
#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
/* Debug ********************************************************************/
/* Non-standard debug that may be enabled just for testing the interrupt
* config. NOTE: that only lldbg types are used so that the output is
@@ -91,7 +106,7 @@
*/
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
/****************************************************************************
* Private Variables
arch/arm/src/calypso/calypso_serial.c
+1 -1
View File
@@ -377,7 +377,7 @@ static inline void up_setrate(struct up_dev_s *priv, unsigned int rate)
break;
}
#if UART_DIV_BIT_RATE_OFFS
#ifdef UART_DIV_BIT_RATE_OFFS
up_serialout(priv, UART_DIV_BIT_RATE_OFFS, div_bit_rate);
#else
up_serialout(priv, UART_DIV_LOW_OFFS, div_bit_rate);
arch/arm/src/common/up_initialize.c
+7
View File
@@ -44,6 +44,7 @@
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/fs/fs.h>
#include <nuttx/net/loopback.h>
#include <nuttx/syslog/ramlog.h>
#include <nuttx/syslog/syslog_console.h>
#include <nuttx/crypto/crypto.h>
@@ -254,6 +255,12 @@ void up_initialize(void)
up_netinitialize();
#endif
#ifdef CONFIG_NETDEV_LOOPBACK
/* Initialize the local loopback device */
(void)localhost_initialize();
#endif
/* Initialize USB -- device and/or host */
up_usbinitialize();
arch/arm/src/common/up_internal.h
+3 -2
View File
@@ -124,10 +124,11 @@
/* If the floating point unit is present and enabled, then save the
* floating point registers as well as normal ARM registers. This only
* applies if "lazy" floating point register save/restore is used
* (i.e., not CONFIG_ARMV7M_CMNVECTOR).
* (i.e., not CONFIG_ARMV7M_CMNVECTOR=y with CONFIG_ARMV7M_LAZYFPU=n).
*/
# if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_ARMV7M_CMNVECTOR)
# if defined(CONFIG_ARCH_FPU) && (!defined(CONFIG_ARMV7M_CMNVECTOR) || \
defined(CONFIG_ARMV7M_LAZYFPU))
# define up_savestate(regs) up_copyarmstate(regs, (uint32_t*)current_regs)
# else
# define up_savestate(regs) up_copyfullstate(regs, (uint32_t*)current_regs)
arch/arm/src/efm32/Make.defs
+2
View File
@@ -87,6 +87,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
arch/arm/src/efm32/efm32_irq.c
+20 -1
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_irq.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -79,8 +79,18 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@@ -363,6 +373,15 @@ void up_irqinitialize(void)
}
#endif
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
arch/arm/src/efm32/efm32_usbdev.c
+2 -2
View File
@@ -683,7 +683,7 @@ static const struct usbdev_ops_s g_devops =
.pullup = efm32_pullup,
};
/* Device error strings that may be enabled for more desciptive USB trace
/* Device error strings that may be enabled for more descriptive USB trace
* output.
*/
@@ -725,7 +725,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
};
#endif
/* Interrupt event strings that may be enabled for more desciptive USB trace
/* Interrupt event strings that may be enabled for more descriptive USB trace
* output.
*/
arch/arm/src/efm32/efm32_usbhost.c
+1 -1
View File
@@ -1171,7 +1171,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
/* Loop, testing for an end of transfer condition. The channel 'result'
* was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter'
* will be set to false and 'result' will be set appropriately when the
* tranfer is completed.
* transfer is completed.
*/
do
arch/arm/src/kinetis/kinetis_enet.c
+4 -4
View File
@@ -191,14 +191,14 @@ struct kinetis_driver_s
#endif
/* The DMA descriptors. A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the desciptor alignment
* memory; 16 is added to assure that we can meet the descriptor alignment
* requirements.
*/
uint8_t desc[NENET_NBUFFERS * sizeof(struct enet_desc_s) + 16];
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the desciptor alignment
* memory; 16 is added to assure that we can meet the descriptor alignment
* requirements.
*/
@@ -1338,7 +1338,7 @@ static inline void kinetis_initphy(struct kinetis_driver_s *priv)
* configuration and the auto negotiation results.
*/
#if CONFIG_ENET_USEMII
#ifdef CONFIG_ENET_USEMII
rcr = ENET_RCR_MII_MODE | ENET_RCR_CRCFWD |
CONFIG_NET_ETH_MTU << ENET_RCR_MAX_FL_SHIFT;
#else
@@ -1527,7 +1527,7 @@ int kinetis_netinitialize(int intf)
/* Configure all ENET/MII pins */
#if CONFIG_ENET_USEMII
#ifdef CONFIG_ENET_USEMII
kinetis_pinconfig(PIN_MII0_MDIO);
kinetis_pinconfig(PIN_MII0_MDC);
kinetis_pinconfig(PIN_MII0_RXDV);
arch/arm/src/kinetis/kinetis_irq.c
+21 -2
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17/kinetis_irq.c
*
* Copyright (C) 2011, 2013-14 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -75,8 +75,18 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
****************************************************************************/
@@ -341,11 +351,20 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
up_ramvec_initialize();
#endif
arch/arm/src/kinetis/kinetis_sdhc.c
+5 -5
View File
@@ -65,7 +65,7 @@
#include "kinetis_sim.h"
#include "kinetis_sdhc.h"
#if CONFIG_KINETIS_SDHC
#ifdef CONFIG_KINETIS_SDHC
/****************************************************************************
* Pre-processor Definitions
@@ -102,7 +102,7 @@
* and divider values.
*/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
# ifndef CONFIG_KINETIS_IDMODE_FREQ
# define CONFIG_KINETIS_IDMODE_FREQ 400000 /* 400 KHz, ID mode */
# endif
@@ -287,7 +287,7 @@ static int kinetis_lock(FAR struct sdio_dev_s *dev, bool lock);
static void kinetis_reset(FAR struct sdio_dev_s *dev);
static uint8_t kinetis_status(FAR struct sdio_dev_s *dev);
static void kinetis_widebus(FAR struct sdio_dev_s *dev, bool enable);
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency);
#endif
static void kinetis_clock(FAR struct sdio_dev_s *dev,
@@ -1387,7 +1387,7 @@ static void kinetis_widebus(FAR struct sdio_dev_s *dev, bool wide)
*
****************************************************************************/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
{
uint32_t sdclkfs;
@@ -1523,7 +1523,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
*
****************************************************************************/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
uint32_t frequency;
arch/arm/src/lpc17xx/Make.defs
+2
View File
@@ -100,6 +100,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
arch/arm/src/lpc17xx/lpc176x_rtc.c
+2 -2
View File
@@ -250,7 +250,7 @@ static int rtc_resume(void)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
#warning "Missing logic"
@@ -285,7 +285,7 @@ int up_rtcinitialize(void)
/* Attach the RTC interrupt handler */
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt);
if (ret == OK)
{
arch/arm/src/lpc17xx/lpc17_allocateheap.c
+22 -3
View File
@@ -155,15 +155,23 @@
/* Sanity checking */
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) && !defined(CONFIG_LPC17_EXTSRAM0HEAP)
# define LPC17_EXT_MM_REGIONS 0
#elif defined(CONFIG_LPC17_EXTDRAMHEAP) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
# define LPC17_EXT_MM_REGIONS 2
#else
# define LPC17_EXT_MM_REGIONS 1
#endif
#ifdef LPC17_AHB_HEAPBASE
# if CONFIG_MM_REGIONS < 2
# if CONFIG_MM_REGIONS < 2 + LPC17_EXT_MM_REGIONS
# warning "CONFIG_MM_REGIONS < 2: Available AHB SRAM Bank(s) not included in HEAP"
# endif
# if CONFIG_MM_REGIONS > 2
# if (CONFIG_MM_REGIONS > 2 + LPC17_EXT_MM_REGIONS)
# warning "CONFIG_MM_REGIONS > 2: Are additional regions handled by application?"
# endif
#else
# if CONFIG_MM_REGIONS > 1
# if CONFIG_MM_REGIONS > 1 + LPC17_EXT_MM_REGIONS
# warning "CONFIG_MM_REGIONS > 1: This configuration has no available AHB SRAM Bank0/1"
# warning "CONFIG_MM_REGIONS > 1: Are additional regions handled by application?"
# endif
@@ -340,5 +348,16 @@ void up_addregion(void)
kumm_addregion((FAR void*)LPC17_AHB_HEAPBASE, LPC17_AHB_HEAPSIZE);
#endif
#if CONFIG_MM_REGIONS >= 3
#if defined(CONFIG_LPC17_EXTDRAM) && defined(CONFIG_LPC17_EXTDRAMHEAP)
kmm_addregion((FAR void*)LPC17_EXTDRAM_CS0, CONFIG_LPC17_EXTDRAMSIZE);
#endif
#if !defined(CONFIG_LPC17_EXTDRAMHEAP) || (CONFIG_MM_REGIONS >= 4)
#if defined(CONFIG_LPC17_EXTSRAM0) && defined(CONFIG_LPC17_EXTSRAM0HEAP)
kmm_addregion((FAR void*)LPC17_EXTSRAM_CS0, CONFIG_LPC17_EXTSRAM0SIZE);
#endif
#endif
#endif
}
#endif
arch/arm/src/lpc17xx/lpc17_can.c
+9 -5
View File
@@ -750,7 +750,8 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
irqstate_t flags;
int ret = OK;
canvdbg("CAN%d ID: %d DLC: %d\n", priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
canvdbg("CAN%d ID: %d DLC: %d\n",
priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
if (msg->cm_hdr.ch_rtr)
{
@@ -971,12 +972,15 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Construct the CAN header */
hdr.ch_id = rid;
hdr.ch_rtr = ((rfs & CAN_RFS_RTR) != 0);
hdr.ch_dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT;
hdr.ch_id = rid;
hdr.ch_rtr = ((rfs & CAN_RFS_RTR) != 0);
hdr.ch_dlc = (rfs & CAN_RFS_DLC_MASK) >> CAN_RFS_DLC_SHIFT;
hdr.ch_error = 0;
#ifdef CONFIG_CAN_EXTID
hdr.ch_extid = ((rfs & CAN_RFS_FF) != 0);
hdr.ch_extid = ((rfs & CAN_RFS_FF) != 0);
#else
hdr.ch_unused = 0;
if ((rfs & CAN_RFS_FF) != 0)
{
canlldbg("ERROR: Received message with extended identifier. Dropped\n");
arch/arm/src/lpc17xx/lpc17_ethernet.c
+1 -1
View File
@@ -1564,7 +1564,7 @@ static void lpc17_poll_process(FAR struct lpc17_driver_s *priv)
if (considx != prodidx)
{
#if CONFIG_NET_NOINTS
#ifdef CONFIG_NET_NOINTS
work_queue(HPWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work,
priv, 0);
arch/arm/src/lpc17xx/lpc17_gpdma.h
+1 -1
View File
@@ -60,7 +60,7 @@ typedef FAR void *DMA_HANDLE;
* function is called at the completion of the DMA transfer. 'arg' is the
* same 'arg' value that was provided when lpc17_dmastart() was called and
* result indicates the result of the transfer: Zero indicates a successful
* tranfers. On failure, a negated errno is returned indicating the general
* transfers. On failure, a negated errno is returned indicating the general
* nature of the DMA faiure.
*/
arch/arm/src/lpc17xx/lpc17_irq.c
+23 -4
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17/lpc17_irq.c
*
* Copyright (C) 2010-2011, 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2010-2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -76,11 +76,17 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/****************************************************************************
* Private Data
****************************************************************************/
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Functions
@@ -313,8 +319,21 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*
* But even in this case NVIC_VECTAB has to point to the initial table
* because up_ramvec_initialize() initializes RAM table from table
* pointed by NVIC_VECTAB register.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
arch/arm/src/lpc17xx/lpc17_lcd.c
+1 -1
View File
@@ -565,7 +565,7 @@ int up_fbinitialize(void)
/* TFT panel */
#if CONFIG_LPC17_LCD_TFTPANEL
#ifdef CONFIG_LPC17_LCD_TFTPANEL
regval |= LCD_CTRL_LCDTFT;
#endif
arch/arm/src/lpc17xx/lpc17_sdcard.c
+1 -1
View File
@@ -67,7 +67,7 @@
#include "chip/lpc17_syscon.h"
#include "chip/lpc17_pinconfig.h"
#if CONFIG_LPC17_SDCARD
#ifdef CONFIG_LPC17_SDCARD
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/lpc17xx/lpc17_usbdev.c
+2 -2
View File
@@ -2088,7 +2088,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
#endif
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
/* USB engine error interrupt */
if ((devintstatus & USBDEV_INT_ERRINT) != 0)
@@ -2457,7 +2457,7 @@ static int lpc17_dmasetup(struct lpc17_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC17_USBDEV_EPDMAEN);
arch/arm/src/lpc214x/lpc214x_usbdev.c
+3 -3
View File
@@ -212,7 +212,7 @@
/* USB RAM ********************************************************************
*
* UBS_UDCA is is list of 32 pointers to DMA desciptors located at the
* UBS_UDCA is is list of 32 pointers to DMA descriptors located at the
* beginning of USB RAM. Each pointer points to a DMA descriptor with
* assocated DMA buffer.
*/
@@ -2052,7 +2052,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
#endif
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
/* USB engine error interrupt */
if ((devintstatus & USBDEV_DEVINT_EPRINT))
@@ -2422,7 +2422,7 @@ static int lpc214x_dmasetup(struct lpc214x_usbdev_s *priv, uint8_t epphy,
dmadesc->size = (uint32_t)packet;
#endif
/* Enable DMA tranfer for this endpoint */
/* Enable DMA transfer for this endpoint */
putreq32(1 << epphy, LPC214X_USBDEV_EPDMAEN);
arch/arm/src/lpc43xx/Kconfig
+145
View File
@@ -163,6 +163,151 @@ config LPC43_ETHERNET
bool "Ethernet"
default n
if LPC43_ETHERNET
menu "Ethernet MAC configuration"
config LPC43_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board. Default: 1
config LPC43_PHYINIT
bool "Board-specific PHY Initialization"
default n
---help---
Some boards require specialized initialization of the PHY before it can be used.
This may include such things as configuring GPIOs, resetting the PHY, etc. If
LPC43_PHYINIT is defined in the configuration then the board specific logic must
provide lpc43_phyinitialize(); The LPC43 Ethernet driver will call this function
one time before it first uses the PHY.
config LPC43_MII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface.
config LPC43_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
config LPC43_ETHFD
bool "Full duplex"
default n
depends on !LPC43_AUTONEG
---help---
If LPC43_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
config LPC43_ETH100MBPS
bool "100 Mbps"
default n
depends on !LPC43_AUTONEG
---help---
If LPC43_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
config LPC43_PHYSR
int "PHY Status Register Address (decimal)"
depends on LPC43_AUTONEG
---help---
This must be provided if LPC43_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
config LPC43_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on LPC43_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config LPC43_PHYSR_SPEED
hex "PHY Speed Mask"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config LPC43_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config LPC43_PHYSR_MODE
hex "PHY Mode Mask"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config LPC43_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config LPC43_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config LPC43_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config LPC43_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config LPC43_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config LPC43_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
---help---
This must be provided if LPC43_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
config LPC43_RMII
bool
default y if !LPC43_MII
config LPC43_ETHERNET_REGDEBUG
bool "Register-Level Debug"
default n
depends on DEBUG
---help---
Enable very low-level register access debug. Depends on DEBUG.
endmenu
endif
config LPC43_EVNTMNTR
bool "Event Monitor"
default n
arch/arm/src/lpc43xx/Make.defs
+7 -1
View File
@@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/lpc43xx/Make.defs
#
# Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
# Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@@ -84,6 +84,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
@@ -116,6 +118,10 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
CHIP_CSRCS += lpc43_gpioint.c
endif
ifeq ($(CONFIG_LPC43_ETHERNET),y)
CHIP_CSRCS += lpc43_ethernet.c
endif
ifeq ($(CONFIG_LPC43_SPI),y)
CHIP_CSRCS += lpc43_spi.c
endif
arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
+1 -1
View File
@@ -73,7 +73,7 @@
#define LPC43_EEPROM_RWSTATE (LPC43_EEPROMC_BASE+LPC43_EEPROM_RWSTATE_OFFSET)
#define LPC43_EEPROM_AUTOPROG (LPC43_EEPROMC_BASE+LPC43_EEPROM_AUTOPROG_OFFSET)
#define LPC43_EEPROM_WSTATE (LPC43_EEPROMC_BASE+LPC43_EEPROM_WSTATE_OFFSET)
# LPC43_EEPROM_CLKDIV (LPC43_EEPROMC_BASE+LPC43_EEPROM_CLKDIV_OFFSET)
#define LPC43_EEPROM_CLKDIV (LPC43_EEPROMC_BASE+LPC43_EEPROM_CLKDIV_OFFSET)
#define LPC43_EEPROM_PWRDWN (LPC43_EEPROMC_BASE+LPC43_EEPROM_PWRDWN_OFFSET)
/* EEPROM interrupt registers */
arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
+16 -16
View File
@@ -181,7 +181,8 @@
/* MAC frame filter register */
#define ETH_MACFFLT_PR (1 << 0) /* Bit 0: Promiscuous mode */
/* Bits 1-2: Reserved */
#define ETH_MACFFLT_HUC (1 << 1) /* Bit 1: Hash Unicast */
#define ETH_MACFFLT_HMC (1 << 2) /* Bit 2: Hash Multicast */
#define ETH_MACFFLT_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */
#define ETH_MACFFLT_PM (1 << 4) /* Bit 4: Pass all multicast */
#define ETH_MACFFLT_DBF (1 << 5) /* Bit 5: Disable Broadcast Frames */
@@ -191,9 +192,9 @@
# define ETH_MACFFLT_PCF_PAUSE (1 << ETH_MACFFLT_PCF_SHIFT) /* Prevents all except Pause control frames */
# define ETH_MACFFLT_PCF_ALL (2 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all control frames */
# define ETH_MACFFLT_PCF_FILTER (3 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all that pass address filter */
#define ETH_MACFFLT_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */
#define ETH_MACFFLT_SAF (1 << 9) /* Bit 9: Source address filter */
/* Bits 10-30: Reserved */
/* Bit 8-9: Reserved */
#define ETH_MACFFLT_HPF (1 << 10) /* Bit 10: Hash or perfect filter */
/* Bits 11-30: Reserved */
#define ETH_MACFFLT_RA (1 << 31) /* Bit 31: Receive all */
/* MAC hash table high/low register (32-bit values) */
@@ -208,7 +209,7 @@
# define ETH_MACMIIA_CR_100_150 (1 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
# define ETH_MACMIIA_CR_20_35 (2 << ETH_MACMIIA_CR_SHIFT) /* 20-35 MHz CLK_M4_ETHERNET/16 */
# define ETH_MACMIIA_CR_35_60 (3 << ETH_MACMIIA_CR_SHIFT) /* 35-60 MHz CLK_M4_ETHERNET/26 */
# define ETH_MACMIIA_CR_150_168 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-168 MHz CLK_M4_ETHERNET/102 */
# define ETH_MACMIIA_CR_150_250 (4 << ETH_MACMIIA_CR_SHIFT) /* 150-250 MHz CLK_M4_ETHERNET/102 */
# define ETH_MACMIIA_CR_250_300 (5 << ETH_MACMIIA_CR_SHIFT) /* 250-300 MHz CLK_M4_ETHERNET/124 */
# define ETH_MACMIIA_CR_DIV42 (8 << ETH_MACMIIA_CR_SHIFT) /* 60-100 MHz CLK_M4_ETHERNET/42 */
# define ETH_MACMIIA_CR_DIV62 (9 << ETH_MACMIIA_CR_SHIFT) /* 100-150 MHz CLK_M4_ETHERNET/62 */
@@ -314,7 +315,7 @@
/* Bits 4-8: Reserved */
#define ETH_MACIM_TSIM (1 << 9) /* Bit 9: Time stamp interrupt mask */
/* Bits 10-31: Reserved */
#define ETH_MACIM_ALLINTS (ETH_MACIM_PMTIM|ETH_MACIM_TSTIM)
#define ETH_MACIM_ALLINTS (ETH_MACIM_PMTIM|ETH_MACIM_TSIM)
/* MAC address 0 high register */
@@ -499,9 +500,9 @@
#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT)
#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */
#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */
#define ETH_TDES0_LC (1 << 9) /* Bit 9: Late collision */
#define ETH_TDES0_LCL (1 << 9) /* Bit 9: Late collision */
#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */
#define ETH_TDES0_LC (1 << 11) /* Bit 11: Loss of carrier */
#define ETH_TDES0_LCR (1 << 11) /* Bit 11: Loss of carrier */
#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */
#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */
#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */
@@ -536,7 +537,7 @@
#define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */
#define ETH_RDES0_DE (1 << 2) /* Bit 2: Dribble bit error */
#define ETH_RDES0_DRE (1 << 2) /* Bit 2: Dribble bit error */
#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */
#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */
#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */
@@ -548,7 +549,7 @@
#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */
#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */
#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */
#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */
#define ETH_RDES0_DS (1 << 14) /* Bit 14: Descriptor error */
#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */
#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */
#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT)
@@ -584,12 +585,12 @@
* transparent clock) */
# define ETH_RDES4_MT_PDELREQMM (6 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp (in peer-to-peer
* transparent clock) */
# define ETH_RDES4_MT_PDELREQFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in
# define ETH_RDES4_MT_PDELRESFUS (7 << ETH_RDES4_MT_SHIFT) /* Pdelay_Resp_Follow_Up (in
* peer-to-peer transparent clock) */
# define ETH_RDES4_MT_PDELREQFUS (8 << ETH_RDES4_MT_SHIFT) /* Announce */
# define ETH_RDES4_MT_PDELREQFUS (9 << ETH_RDES4_MT_SHIFT) /* Management */
# define ETH_RDES4_MT_PDELREQFUS (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
# define ETH_RDES4_MT_PDELREQFUS (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
# define ETH_RDES4_MT_ANNOUNCE (8 << ETH_RDES4_MT_SHIFT) /* Announce */
# define ETH_RDES4_MT_MANAGEMENT (9 << ETH_RDES4_MT_SHIFT) /* Management */
# define ETH_RDES4_MT_SIGNALING (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
# define ETH_RDES4_MT_PTP (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
#define ETH_RDES4_PTPTYPE (1 << 12) /* Bit 12: PTP frame type */
#define ETH_RDES4_PTPVERSION (1 << 13) /* Bit 13: PTP version */
/* Bits 14-31: Reserved */
@@ -662,6 +663,5 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* LPC43_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */
arch/arm/src/lpc43xx/lpc43_ethernet.c
+4008
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/lpc43xx/lpc43_ethernet.h
+93
View File
@@ -0,0 +1,93 @@
/************************************************************************************
* arch/arm/src/lpc43xx/lpc43_eth.h
*
* Copyright (C) 2009-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
#define __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "chip/lpc43_ethernet.h"
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/************************************************************************************
* Function: lpc43_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can be used.
* This may include such things as configuring GPIOs, resetting the PHY, etc. If
* CONFIG_LPC43_PHYINIT is defined in the configuration then the board specific
* logic must provide lpc43_phyinitialize(); The LPC43 Ethernet driver will call
* this function one time before it first uses the PHY.
*
* Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
************************************************************************************/
#ifdef CONFIG_LPC43_PHYINIT
int lpc43_phy_boardinitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H */
arch/arm/src/lpc43xx/lpc43_irq.c
+15 -8
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43/lpc43_irq.c
*
* Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -77,11 +77,17 @@
* Public Data
****************************************************************************/
/* This is the address of current interrupt saved state data. Used for
* context switching. Only value during interrupt handling.
*/
volatile uint32_t *current_regs;
/* This is the address of the vector table */
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern unsigned _vectors[];
extern uint32_t _vectors[];
/****************************************************************************
* Private Data
@@ -316,15 +322,16 @@ void up_irqinitialize(void)
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#ifdef CONFIG_ARCH_RAMVECTORS
up_ramvec_initialize();
#else
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
/* Set all interrupts (and exceptions) to the default priority */
arch/arm/src/lpc43xx/lpc43_spi.c
+6 -25
View File
@@ -54,8 +54,7 @@
#include "up_arch.h"
#include "chip.h"
#include "lpc43_syscon.h"
#include "lpc43_pinconn.h"
#include "lpc43_pinconfig.h"
#include "lpc43_spi.h"
#ifdef CONFIG_LPC43_SPI
@@ -93,7 +92,6 @@
* use the CCLK undivided to get the SPI_CLOCK.
*/
#define SPI_PCLKSET_DIV SYSCON_PCLKSEL_CCLK
#define SPI_CLOCK LPC43_CCLK
/****************************************************************************
@@ -545,36 +543,19 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
FAR struct spi_dev_s *lpc43_spiinitialize(int port)
{
FAR struct lpc43_spidev_s *priv = &g_spidev;
irqstate_t flags;
uint32_t regval;
/* Configure multiplexed pins as connected on the board. Chip select
* pins must be configured by board-specific logic. All SPI pins and
* one SPI1 pin (SCK) have multiple, alternative pin selection.
* one SPI1 pin (SCK) have multiple, alternative pin selections.
* Definitions in the board.h file must be provided to resolve the
* board-specific pin configuration like:
*
* #define GPIO_SPI_SCK GPIO_SPI_SCK_1
* #define PINCONF_SPI_SCK PINCONF_SPI_SCK_1
*/
flags = irqsave();
lpc43_configgpio(GPIO_SPI_SCK);
lpc43_configgpio(GPIO_SPI_MISO);
lpc43_configgpio(GPIO_SPI_MOSI);
/* Configure clocking */
regval = getreg32(LPC43_SYSCON_PCLKSEL0);
regval &= ~SYSCON_PCLKSEL0_SPI_MASK;
regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT);
putreg32(regval, LPC43_SYSCON_PCLKSEL0);
/* Enable peripheral clocking to SPI and SPI1 */
regval = getreg32(LPC43_SYSCON_PCONP);
regval |= SYSCON_PCONP_PCSPI;
putreg32(regval, LPC43_SYSCON_PCONP);
irqrestore(flags);
lpc43_pin_config(PINCONF_SPI_SCK);
lpc43_pin_config(PINCONF_SPI_MISO);
lpc43_pin_config(PINCONF_SPI_MOSI);
/* Configure 8-bit SPI mode and master mode */
arch/arm/src/lpc43xx/lpc43_spifi.c
+1 -1
View File
@@ -1093,7 +1093,7 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
fvdbg(" blksize: %08x\n", priv->blksize);
fvdbg(" nblocks: %d\n", priv->nblocks);
#if CONFIG_SPIFI_SECTOR512
#ifdef CONFIG_SPIFI_SECTOR512
DEBUGASSERT(log2 > 9);
#endif
arch/arm/src/lpc43xx/lpc43_start.c
+1
View File
@@ -63,6 +63,7 @@
#include <nuttx/init.h>
#include <arch/board/board.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "up_internal.h"
arch/arm/src/lpc43xx/lpc43_uart.c
+5 -10
View File
@@ -192,23 +192,18 @@ void up_lowputc(char ch)
* as possible.
*
* The USART0/2/3 and UART1 peripherals are configured using the following registers:
* 1. Power: In the PCONP register, set bits PCUSART0/1/2/3.
* On reset, USART0 and UART 1 are enabled (PCUSART0 = 1 and PCUART1 = 1)
* and USART2/3 are disabled (PCUART1 = 0 and PCUSART3 = 0).
* 2. Peripheral clock: In the PCLKSEL0 register, select PCLK_USART0 and
* PCLK_UART1; in the PCLKSEL1 register, select PCLK_USART2 and PCLK_USART3.
* 3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
* 1. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
* to registers DLL and DLM for setting the baud rate. Also, if needed,
* set the fractional baud rate in the fractional divider
* 4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
* 2. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
* enable FIFO.
* 5. Pins: Select UART pins through the PINSEL registers and pin modes
* 3. Pins: Select UART pins through the PINSEL registers and pin modes
* through the PINMODE registers. UART receive pins should not have
* pull-down resistors enabled.
* 6. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
* 4. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
* register. This enables access to IER. Interrupts are enabled
* in the NVIC using the appropriate Interrupt Set Enable register.
* 7. DMA: UART transmit and receive functions can operate with the
* 5. DMA: UART transmit and receive functions can operate with the
* GPDMA controller.
*
**************************************************************************/
arch/arm/src/moxart/Kconfig
+9
View File
@@ -7,3 +7,12 @@ comment "MoxART Configuration Options"
config UART_MOXA_MODE_REG
hex "16550 UART mode register address"
default 0x982000E0
config UART_MOXA_IRQ_STATUS_REG
hex "16550 UART shared IRQ status register address"
default 0x982000C0
config UART_MOXA_SHARED_IRQ
int "16550 UART shared IRQ number"
default 31
arch/arm/src/moxart/moxart_16550.c
+29 -1
View File
@@ -67,6 +67,30 @@ void uart_putreg(uart_addrwidth_t base, unsigned int offset, uart_datawidth_t va
*((volatile uart_addrwidth_t *)base + offset) = value;
}
void uart_decodeirq(int irq, FAR void *context)
{
int i;
uint32_t status;
static int os = 0;
status = *((volatile uart_addrwidth_t *)CONFIG_UART_MOXA_IRQ_STATUS_REG);
if ((status & 0x3f) == 0x3f)
{
return;
}
i = 0;
do
{
if (!(status & 0x1)) {
irq_dispatch(VIRQ_START + i, context);
}
status >>= 1;
}
while (++i <= 4);
}
#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
{
@@ -109,9 +133,12 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Update mode register with requested mode */
vmode = getreg32(CONFIG_UART_MOXA_MODE_REG);
putreg32(CONFIG_UART_MOXA_MODE_REG, (vmode & ~(OP_MODE_MASK << 2 * bitm_off)) | ((opmode << 2 * bitm_off) & 0xffff));
putreg32(vmode & ~(OP_MODE_MASK << 2 * bitm_off), CONFIG_UART_MOXA_MODE_REG);
vmode = opmode << 2 * bitm_off;
putreg32(getreg32(CONFIG_UART_MOXA_MODE_REG) | vmode, CONFIG_UART_MOXA_MODE_REG);
irqrestore(flags);
ret = OK;
break;
}
@@ -126,6 +153,7 @@ int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
irqrestore(flags);
*(unsigned long *)arg = opmode;
ret = OK;
break;
}
}
arch/arm/src/moxart/moxart_irq.c
+13
View File
@@ -81,6 +81,8 @@ volatile uint32_t *current_regs;
* Public Functions
****************************************************************************/
extern void uart_decodeirq(int irq, uint32_t *regs);
/****************************************************************************
* Name: up_irqinitialize
*
@@ -93,6 +95,10 @@ void up_irqinitialize(void)
{
/* Prepare hardware */
*(volatile int *)0x98700000 |= 0x3f;
/* PMU setup */
(*(volatile uint32_t *)0x98100008) &= ~0x9;
while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; }
@@ -101,6 +107,8 @@ void up_irqinitialize(void)
(*(volatile uint32_t *)0x98800100) = 0xDFF8003F;
/* Check board type */
/* Mask all interrupts off */
putreg32(0, IRQ_REG(IRQ__MASK));
@@ -119,6 +127,11 @@ void up_irqinitialize(void)
current_regs = NULL;
/* Setup UART shared interrupt */
irq_attach(CONFIG_UART_MOXA_SHARED_IRQ, uart_decodeirq);
up_enable_irq(CONFIG_UART_MOXA_SHARED_IRQ);
/* And finally, enable interrupts */
#if 1
arch/arm/src/moxart/moxart_timer.c
-3
View File
@@ -132,9 +132,6 @@ void up_timer_initialize(void)
uint32_t tmp;
// up_disable_irq(IRQ_SYSTIMER);
*(volatile int *)0x98700000 = 0x3f;
putreg32(0, TM1_ADDR + CNTL_TIMER);
putreg32(0, TM1_ADDR + INTR_STATE_TIMER);
putreg32(0x1ff, TM1_ADDR + INTR_MASK_TIMER);
arch/arm/src/nuc1xx/chip/nuc_gcr.h
+1 -1
View File
@@ -356,7 +356,7 @@
# define GCR_REGWRPROT_2 (0x16)
# define GCR_REGWRPROT_3 (0x88)
/* Read: */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protectino disable index */
#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protection disable index */
/********************************************************************************************
* Public Types
arch/arm/src/sam34/Make.defs
+2
View File
@@ -91,6 +91,8 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif
arch/arm/src/sam34/sam4l_clockconfig.c
+1 -1
View File
@@ -1293,7 +1293,7 @@ void sam_clockconfig(void)
* OSC32: Might be source clock for DFLL0
*/
#if NEED_OSC0
#ifdef NEED_OSC0
/* Enable OSC0 using the settings in board.h */
sam_enableosc0();

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