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arch/arm64/src/imx9: Add TPM based PWM driver for IMX9
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
65bd548521
commit
0f596ec496
@@ -67,6 +67,107 @@ config IMX9_FLEXIO2_PWM_CHANNEL_PINS
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hex "FlexIO outputs used for FLEXIO2 timers"
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default 0x0000000000000000
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config IMX9_TPM_PWM
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bool
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select PWM_MULTICHAN
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default n
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config IMX9_TPM1_PWM
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depends on PWM
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bool "Enable TPM1 based PWM generation"
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select IMX9_TPM_PWM
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default n
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config IMX9_TPM1_PWM_NCHANNELS
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depends on IMX9_TPM1_PWM
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int "Number of channels for TPM1"
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default 1
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config IMX9_TPM1_PWM_CHMUX
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depends on IMX9_TPM1_PWM
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hex "Channel mux for TPM1"
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default 0x03020100
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config IMX9_TPM2_PWM
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depends on PWM
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bool "Enable TPM2 based PWM generation"
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select IMX9_TPM_PWM
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default n
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config IMX9_TPM2_PWM_NCHANNELS
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depends on IMX9_TPM2_PWM
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int "Number of channels for TPM2"
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default 1
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config IMX9_TPM2_PWM_CHMUX
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depends on IMX9_TPM2_PWM
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hex "Channel mux for TPM2"
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default 0x03020100
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config IMX9_TPM3_PWM
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depends on PWM
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bool "Enable TPM3 based PWM generation"
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select IMX9_TPM_PWM
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default n
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config IMX9_TPM3_PWM_NCHANNELS
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depends on IMX9_TPM3_PWM
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int "Number of channels for TPM3"
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default 1
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config IMX9_TPM3_PWM_CHMUX
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depends on IMX9_TPM3_PWM
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hex "Channel mux for TPM3"
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default 0x03020100
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config IMX9_TPM4_PWM
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depends on PWM
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bool "Enable TPM4 based PWM generation"
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select IMX9_TPM_PWM
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default n
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config IMX9_TPM4_PWM_NCHANNELS
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depends on IMX9_TPM4_PWM
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int "Number of channels for TPM4"
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default 1
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config IMX9_TPM4_PWM_CHMUX
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depends on IMX9_TPM4_PWM
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hex "Channel mux for TPM4"
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default 0x03020100
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config IMX9_TPM5_PWM
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depends on PWM
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bool "Enable TPM5 based PWM generation"
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select IMX9_TPM_PWM
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default n
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config IMX9_TPM5_PWM_NCHANNELS
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depends on IMX9_TPM5_PWM
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int "Number of channels for TPM5"
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default 1
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config IMX9_TPM5_PWM_CHMUX
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depends on IMX9_TPM5_PWM
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hex "Channel mux for TPM5"
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default 0x03020100
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config IMX9_TPM6_PWM
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depends on PWM
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bool "Enable TPM6 based PWM generation"
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select IMX9_TPM_PWM
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default n
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config IMX9_TPM6_PWM_NCHANNELS
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depends on IMX9_TPM6_PWM
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int "Number of channels for TPM6"
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default 1
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config IMX9_TPM6_PWM_CHMUX
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depends on IMX9_TPM6_PWM
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hex "Channel mux for TPM6"
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default 0x03020100
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config IMX9_USBDEV
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bool
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default n
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@@ -39,6 +39,10 @@ ifeq ($(CONFIG_IMX9_FLEXIO_PWM),y)
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CHIP_CSRCS += imx9_flexio_pwm.c
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endif
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ifeq ($(CONFIG_IMX9_TPM_PWM),y)
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CHIP_CSRCS += imx9_tpm_pwm.c
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endif
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ifeq ($(CONFIG_IMX9_USBDEV),y)
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CHIP_CSRCS += imx9_usbdev.c
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endif
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@@ -0,0 +1,206 @@
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/****************************************************************************
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* arch/arm64/src/imx9/hardware/imx9_tpm.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TPM_H
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#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TPM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define IMX9_TPM_VERID_OFFSET 0x0000 /* Version ID */
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#define IMX9_TPM_PARAM_OFFSET 0x0004 /* Parameter */
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#define IMX9_TPM_GLOBAL_OFFSET 0x0008 /* TPM Global */
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#define IMX9_TPM_SC_OFFSET 0x0010 /* Status and Control */
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#define IMX9_TPM_CNT_OFFSET 0x0014 /* Counter */
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#define IMX9_TPM_MOD_OFFSET 0x0018 /* Modulo */
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#define IMX9_TPM_STATUS_OFFSET 0x001c /* Capture and Compare Status */
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#define IMX9_TPM_CXSC_OFFSET(ch) (0x0020 + (ch) * 8) /* Channel Status and Control */
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#define IMX9_TPM_CXV_OFFSET(ch) (0x0024 + (ch) * 8) /* Channel Value */
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#define IMX9_TPM_C1SC_OFFSET 0x0028 /* Channel n Status and Control */
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#define IMX9_TPM_C1V_OFFSET 0x002c /* Channel n Value */
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#define IMX9_TPM_C2SC_OFFSET 0x0030 /* Channel n Status and Control */
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#define IMX9_TPM_C2V_OFFSET 0x0034 /* Channel n Value */
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#define IMX9_TPM_C3SC_OFFSET 0x0038 /* Channel n Status and Control */
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#define IMX9_TPM_C3V_OFFSET 0x003c /* Channel n Value */
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#define IMX9_TPM_COMBINE_OFFSET 0x0064 /* Combine Channel */
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#define IMX9_TPM_TRIG_OFFSET 0x006c /* Channel Trigger */
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#define IMX9_TPM_POL_OFFSET 0x0070 /* Channel Polarity */
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#define IMX9_TPM_FILTER_OFFSET 0x0078 /* Filter Control */
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#define IMX9_TPM_QDCTRL_OFFSET 0x0080 /* Quadrature Decoder Control and Status */
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#define IMX9_TPM_CONF_OFFSET 0x0084 /* Configuration */
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/* Register Bitfield Definitions ********************************************/
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/* PARAM */
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#define TPM_PARAM_WIDTH_SHIFT (16) /* Bit[23:16]: Width of the counter and timer channels */
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#define TPM_PARAM_WIDTH_MASK (0xff << TPM_PARAM_WIDTH_SHIFT)
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#define TPM_PARAM_TRIG_SHIFT (8) /* Bit[15:8]: Number of triggers that TPM implements */
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#define TPM_PARAM_TRIG_MASK (0xff << LPIT_PARAM_TRIG_SHIFT)
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#define TPM_PARAM_CHAN_SHIFT (0) /* Bit[7:0]: Number of timer channels */
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#define TPM_PARAM_CHAN_MASK (0xff << TPM_PARAM_CHAN_SHIFT)
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/* GLOBAL */
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#define TPM_GLOBAL_RST_SHIFT (1) /* Bit[1]: Software Reset */
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#define TPM_GLOBAL_RST_MASK (0x1 << TPM_GLOBAL_RST_SHIFT)
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#define TPM_GLOBAL_NOUPDATE_SHIFT (0) /* Bit[0]: Block updates to internal registers */
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#define TPM_GLOBAL_NOUPDATE_MASK (0x1 << TPM_GLOBAL_NOUPDATE_SHIFT)
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/* SC */
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#define TPM_SC_DMA_SHIFT (8) /* Bit[8]: DMA Enable */
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#define TPM_SC_DMA_MASK (0x1 << TPM_SC_DMA_SHIFT)
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#define TPM_SC_TOF_SHIFT (7) /* Bit[7]: Timer Overflow Flag */
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#define TPM_SC_TOF_MASK (0x1 << TPM_SC_TOF_SHIFT)
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#define TPM_SC_TOIE_SHIFT (6) /* Bit[6]: Timer Overflow Interrupt Enable */
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#define TPM_SC_TOIE_MASK (0x1 << TPM_SC_TOIE_SHIFT)
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#define TPM_SC_CPWMS_SHIFT (5) /* Bit[5]: Center-Aligned PWM Select */
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#define TPM_SC_CPWMS_MASK (0x1 << TPM_SC_CPWMS_SHIFT)
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#define TPM_SC_CMOD_SHIFT (3) /* Bit[4:3]: Clock Mode Selection */
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#define TPM_SC_CMOD_MASK (0x3 << TPM_SC_CMOD_SHIFT)
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#define TPM_SC_PS_SHIFT (0) /* Bit[2:0]: Prescale Factor Selection */
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#define TPM_SC_PS_MASK (0x7 << TPM_SC_PS_SHIFT)
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/* STATUS */
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#define TPM_STATUS_TOF_SHIFT (8) /* Bit[8]: Timer Overflow Flag */
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#define TPM_STATUS_TOF_MASK (0x1 << TPM_STATUS_TOF_SHIFT)
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#define TPM_STATUS_CH3F_SHIFT (3) /* Bit[3]: Channel 3 Flag */
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#define TPM_STATUS_CH3F_MASK (0x1 << TPM_STATUS_CH3F_SHIFT)
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#define TPM_STATUS_CH2F_SHIFT (2) /* Bit[2]: Channel 2 Flag */
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#define TPM_STATUS_CH2F_MASK (0x1 << TPM_STATUS_CH2F_SHIFT)
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#define TPM_STATUS_CH1F_SHIFT (1) /* Bit[1]: Channel 1 Flag */
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#define TPM_STATUS_CH1F_MASK (0x1 << TPM_STATUS_CH1F_SHIFT)
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#define TPM_STATUS_CH0F_SHIFT (0) /* Bit[0]: Channel 0 Flag */
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#define TPM_STATUS_CH0F_MASK (0x1 << TPM_STATUS_CH0F_SHIFT)
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/* C0SC - C3SC */
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#define TPM_CXSC_CHF_SHIFT (7) /* Bit[7]: Channel Flag */
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#define TPM_CXSC_CHF_MASK (0x1 << TPM_CXSC_CHF_SHIFT)
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#define TPM_CXSC_CHIE_SHIFT (6) /* Bit[6]: Channel Interrupt Enable */
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#define TPM_CXSC_CHIE_MASK (0x1 << TPM_CXSC_CHIE_SHIFT)
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#define TPM_CXSC_MSB_SHIFT (5) /* Bit[5]: Channel Mode Select B */
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#define TPM_CXSC_MSB_MASK (0x1 << TPM_CXSC_MSB_SHIFT)
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#define TPM_CXSC_MSA_SHIFT (4) /* Bit[4]: Channel Mode Select A */
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#define TPM_CXSC_MSA_MASK (0x1 << TPM_CXSC_MSA_SHIFT)
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#define TPM_CXSC_ELSB_SHIFT (3) /* Bit[3]: Edge or Level Select B */
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#define TPM_CXSC_ELSB_MASK (0x1 << TPM_CXSC_ELSB_SHIFT)
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#define TPM_CXSC_ELSA_SHIFT (2) /* Bit[2]: Edge or Level Select A */
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#define TPM_CXSC_ELSA_MASK (0x1 << TPM_CXSC_ELSA_SHIFT)
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#define TPM_CXSC_DMA_SHIFT (0) /* Bit[0]: DMA Enable */
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#define TPM_CXSC_DMA_MASK (0x1 << TPM_CXSC_DMA_SHIFT)
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/* COMBINE */
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#define TPM_COMBINE_COMSWAP1_SHIFT (9) /* Bit[9]: Combine Channels 2 and 3 Swap */
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#define TPM_COMBINE_COMSWAP1_MASK (0x1 << TPM_COMBINE_COMSWAP1_SHIFT)
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#define TPM_COMBINE_COMBINE1_SHIFT (8) /* Bit[8]: Combine Channels 2 and 3 */
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#define TPM_COMBINE_COMBINE1_MASK (0x1 << TPM_COMBINE_COMBINE1_SHIFT)
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#define TPM_COMBINE_COMSWAP0_SHIFT (1) /* Bit[1]: Combine Channel 0 and 1 Swap */
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#define TPM_COMBINE_COMSWAP0_MASK (0x1 << TPM_COMBINE_COMSWAP0_SHIFT)
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#define TPM_COMBINE_COMBINE0_SHIFT (0) /* Bit[0]: Combine Channels 0 and 1 */
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#define TPM_COMBINE_COMBINE0_MASK (0x1 << TPM_COMBINE_COMBINE0_SHIFT)
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/* TRIG */
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#define TPM_TRIG_TRIGX_MASK(ch) (0x1 << (ch)) /* Channel trigger configure */
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/* POL */
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#define TPM_POL_POLX_MASK(ch) (0x1 < (ch)) /* Channel polarity active low */
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/* FILTER */
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#define TPM_FILTER_CHXFVAL_MASK(ch) (0xf << ((ch) * 4))) /* Channel filter value */
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/* QDCTRL */
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#define TPM_QDCTRL_QUADMODE_SHIFT (3) /* Bit[3]: Quadrature Decoder Mode */
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#define TPM_QDCTRL_QUADMODE_MASK (0x1 << TPM_QDCTRL_QUADMODE_SHIFT)
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#define TPM_QDCTRL_QUADIR_SHIFT (2) /* Bit[2]: Counter Direction */
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#define TPM_QDCTRL_QUADIR_MASK (0x1 << TPM_QDCTRL_QUADIR_SHIFT)
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#define TPM_QDCTRL_TOFDIR_SHIFT (1) /* Bit[1]: Timer Overflow Direction */
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#define TPM_QDCTRL_TOFDIR_MASK (0x1 << TPM_QDCTRL_TOFDIR_SHIFT)
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#define TPM_QDCTRL_QUADEN_SHIFT (0) /* Bit[0]: Quadrature Decoder Enable */
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#define TPM_QDCTRL_QUADEN_MASK (0x1 << TPM_QDCTRL_QUADEN_SHIFT)
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/* CONF */
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#define TPM_CONF_TRGSEL_SHIFT (24) /* Bit[25:24]: Trigger Select */
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#define TPM_CONF_TRGSEL_MASK (0x3 << TPM_CONF_TRGSEL_SHIFT)
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#define TPM_CONF_TRGSRC_SHIFT (23) /* Bit[23]: Trigger Source select */
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#define TPM_CONF_TRGSRC_MASK (0x1 << TPM_CONF_TRGSRC_SHIFT)
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#define TPM_CONF_TRGPOL_SHIFT (22) /* Bit[22]: Trigger Polarity */
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#define TPM_CONF_TRGPOL_MASK (0x1 << TPM_CONF_TRGPOL_SHIFT)
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#define TPM_CONF_CPOT_SHIFT (19) /* Bit[19]: Counter Pause on Trigger */
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#define TPM_CONF_CPOT_MASK (0x1 << TPM_CONF_CPOT_SHIFT)
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#define TPM_CONF_CROT_SHIFT (18) /* Bit[18]: Counter Reload on Trigger */
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#define TPM_CONF_CROT_MASK (0x1 << TPM_CONF_CROT_SHIFT)
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#define TPM_CONF_CSOO_SHIFT (17) /* Bit[17]: Counter Stop on Overflow */
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#define TPM_CONF_CSOO_MASK (0x1 << TPM_CONF_CSOO_SHIFT)
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#define TPM_CONF_CSOT_SHIFT (16) /* Bit[16]: Counter Start on Trigger */
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#define TPM_CONF_CSOT_MASK (0x1 << TPM_CONF_CSOT_SHIFT)
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#define TPM_CONF_DBGMODE_SHIFT (6) /* Bit[7:6]: Debug Mode */
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#define TPM_CONF_DBGMODE_MASK (0x3 << TPM_CONF_DBGMODE_SHIFT)
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#define TPM_CONF_DOZEEN_SHIFT (5) /* Bit[5]: Doze Enable */
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#define TPM_CONF_DOZEEN_MASK (0x1 << TPM_CONF_DOZEEN_SHIFT)
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#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TPM_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,97 @@
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/****************************************************************************
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* arch/arm64/src/imx9/imx9_tpm_pwm.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
|
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_TPM_PWM_H
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#define __ARCH_ARM64_SRC_IMX9_IMX9_TPM_PWM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/board/board.h>
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#include "hardware/imx9_tpm.h"
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/* Check if PWM support for any channel is enabled. */
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#ifdef CONFIG_IMX9_TPM_PWM
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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typedef enum
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{
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PWM_TPM1 = 0,
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PWM_TPM2 = 1,
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PWM_TPM3 = 2,
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PWM_TPM4 = 3,
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PWM_TPM5 = 4,
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PWM_TPM6 = 5,
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} tpm_pwm_id_t;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: imx9_tpm_pwm_init
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*
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* Description:
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* Initialize a TPM block for EPWM usage.
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*
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* Input Parameters:
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* pwmid - A number identifying the pwm block.
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*
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* Returned Value:
|
||||
* On success, a pointer to the lower half of the PWM driver is
|
||||
* returned. NULL is returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct pwm_lowerhalf_s *imx9_tpm_pwm_init(tpm_pwm_id_t pwmid);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_IMX9_TPM_PWM */
|
||||
#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_TPM_PWM_H */
|
||||
Reference in New Issue
Block a user