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esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation
This commit provides an interface to register ISRs that run from IRAM and keeps track of the non-IRAM interrupts. It enables, for instance, to avoid disabling all the interrupts during a SPI flash operation: IRAM-enabled ISRs are, then, able to run during these operations.
This commit is contained in:
Tiago Medicci Serrano
committed by
Xiang Xiao
Xiang Xiao
parent
86b118854e
commit
0ddb64555a
@@ -37,6 +37,16 @@
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#define ESP32S3_INT_PRIO_DEF 1
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/* CPU interrupt flags:
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* These flags can be used to specify which interrupt qualities the
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* code calling esp32s3_setup_irq needs.
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*/
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#define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
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#define ESP32S3_CPUINT_FLAG_EDGE (1 << 1) /* Edge-triggered interrupt */
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#define ESP32S3_CPUINT_FLAG_SHARED (1 << 2) /* Interrupt can be shared between ISRs */
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#define ESP32S3_CPUINT_FLAG_IRAM (1 << 3) /* ISR can be called if cache is disabled */
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/* Interrupt Matrix
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*
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* The Interrupt Matrix embedded in the ESP32-S3 independently allocates
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@@ -386,17 +396,13 @@
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* 26 can be mapped to peripheral interrupts:
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*
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* Level triggered peripherals (21 total):
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* 0-5, 8-9, 12-13, 17-18 - Priority 1
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* 19-21 - Priority 2
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* 23, 27 - Priority 3
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* 24-25 - Priority 4
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* 26, 31 - Priority 5
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* Edge triggered peripherals (4 total):
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* 10 - Priority 1
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* 22 - Priority 3
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* 28, 30 - Priority 4
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* 0-5, 8-10, 12-13, 17-18 - Priority 1
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* 19-21 - Priority 2
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* 22-23, 27 - Priority 3
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* 24-25, 28, 30 - Priority 4
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* 26, 31 - Priority 5
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* NMI (1 total):
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* 14 - NMI
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* 14 - NMI
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*
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* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
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* PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
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@@ -734,6 +734,19 @@ menuconfig ESP32S3_WIFI_BT_COEXIST
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depends on ESP32S3_WIFI && ESP32S3_BLE
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select ESP32S3_WIFI_STA_DISCONNECT_PM
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menu "Interrupt Configuration"
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config ESP32S3_IRAM_ISR_DEBUG
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bool "Enable debugging of the IRAM-enabled interrupts"
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default n
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---help---
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This option enables keeping track of the IRAM-enabled interrupts by
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registering its execution when non-IRAM interrupts are disabled. It
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keeps track of the IRQ executed and register how many times since
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boot it was executed.
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endmenu # Interrupt Configuration
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menu "SPI RAM Configuration"
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depends on ESP32S3_SPIRAM
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@@ -1605,6 +1618,17 @@ config ESP32S3_STORAGE_MTD_DEBUG
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If this option is enabled, Storage MTD driver read and write functions
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will output input parameters and return values (if applicable).
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config ESP32S3_SPIFLASH_OP_TASK_STACKSIZE
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int "The SPI flash operation task stack size"
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default 768
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depends on SMP
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---help---
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When SMP is enabled, it is needed to create two tasks (one for each
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core) to be able to run IRAM-enabled interrupts. These tasks ensures
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that the core that isn't performing the SPI flash operation is able
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to disable non-IRAM interrupts and wait for the SPI flash operation
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to be finished.
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endif # ESP32S3_SPIFLASH
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endmenu # SPI Flash configuration
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File diff suppressed because it is too large
Load Diff
@@ -46,8 +46,8 @@ extern "C"
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/* CPU interrupt types. */
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#define ESP32S3_CPUINT_LEVEL 0
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#define ESP32S3_CPUINT_EDGE 1
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#define ESP32S3_CPUINT_LEVEL ESP32S3_CPUINT_FLAG_LEVEL
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#define ESP32S3_CPUINT_EDGE ESP32S3_CPUINT_FLAG_EDGE
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/****************************************************************************
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* Public Functions Prototypes
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@@ -82,7 +82,9 @@ int esp32s3_cpuint_initialize(void);
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* periphid - The peripheral number from irq.h to be assigned to
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* a CPU interrupt.
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* priority - Interrupt's priority (1 - 5).
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* type - Interrupt's type (level or edge).
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* flags - An ORred mask of the ESP32S3_CPUINT_FLAG_* defines. These
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* restrict the choice of interrupts that this routine can
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* choose from.
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*
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* Returned Value:
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* The allocated CPU interrupt on success, a negated errno value on
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@@ -90,7 +92,7 @@ int esp32s3_cpuint_initialize(void);
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*
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****************************************************************************/
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int esp32s3_setup_irq(int cpu, int periphid, int priority, int type);
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int esp32s3_setup_irq(int cpu, int periphid, int priority, int flags);
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/****************************************************************************
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* Name: esp32s3_teardown_irq
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@@ -121,8 +123,8 @@ void esp32s3_teardown_irq(int cpu, int periphid, int cpuint);
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* This function returns the IRQ associated with a CPU interrupt
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*
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* Input Parameters:
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* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
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* cpuint - The CPU interrupt associated to the IRQ
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* cpu - The CPU core of the IRQ being queried
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* cpuint - The CPU interrupt associated to the IRQ
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*
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* Returned Value:
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* The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if
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@@ -132,6 +134,126 @@ void esp32s3_teardown_irq(int cpu, int periphid, int cpuint);
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int esp32s3_getirq(int cpu, int cpuint);
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/****************************************************************************
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* Name: esp32s3_getcpuint_from_irq
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*
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* Description:
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* This function returns the CPU interrupt associated with an IRQ
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*
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* Input Parameters:
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* irq - The IRQ associated with a CPU interrupt
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* cpu - Pointer to store the CPU core of the CPU interrupt
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*
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* Returned Value:
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* The CPU interrupt associated with such IRQ or IRQ_UNMAPPED if
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* CPU interrupt is not mapped to an IRQ.
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*
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****************************************************************************/
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int esp32s3_getcpuint_from_irq(int irq, int *cpu);
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/****************************************************************************
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* Name: esp32s3_irq_noniram_disable
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*
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* Description:
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* Disable interrupts that aren't specifically marked as running from IRAM
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*
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* Input Parameters:
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* None
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*
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* Input Parameters:
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* None
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*
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****************************************************************************/
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void esp32s3_irq_noniram_disable(void);
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/****************************************************************************
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* Name: esp32s3_irq_noniram_enable
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*
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* Description:
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* Re-enable interrupts disabled by esp32s3_irq_noniram_disable
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*
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* Input Parameters:
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* None
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*
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* Input Parameters:
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* None
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*
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****************************************************************************/
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void esp32s3_irq_noniram_enable(void);
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/****************************************************************************
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* Name: esp32s3_irq_noniram_status
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*
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* Description:
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* Get the current status of non-IRAM interrupts on a specific CPU core
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*
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* Input Parameters:
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* cpu - The CPU to check the non-IRAM interrupts state
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*
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* Returned Value:
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* true if non-IRAM interrupts are enabled, false otherwise.
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*
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****************************************************************************/
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bool esp32s3_irq_noniram_status(int cpu);
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/****************************************************************************
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* Name: esp32s3_irq_set_iram_isr
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*
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* Description:
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* Set the ISR associated to an IRQ as a IRAM-enabled ISR.
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*
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* Input Parameters:
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* irq - The associated IRQ to set
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*
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* Returned Value:
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* OK on success; A negated errno value on failure.
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*
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****************************************************************************/
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int esp32s3_irq_set_iram_isr(int irq);
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/****************************************************************************
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* Name: esp32s3_irq_unset_iram_isr
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*
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* Description:
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* Set the ISR associated to an IRQ as a non-IRAM ISR.
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*
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* Input Parameters:
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* irq - The associated IRQ to set
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*
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* Returned Value:
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* OK on success; A negated errno value on failure.
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*
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****************************************************************************/
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int esp32s3_irq_unset_iram_isr(int irq);
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#ifdef CONFIG_ESP32S3_IRAM_ISR_DEBUG
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/****************************************************************************
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* Name: esp32s3_get_iram_interrupt_records
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*
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* Description:
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* This function copies the vector that keeps track of the IRQs that ran
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* when non-IRAM interrupts were disabled.
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*
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* Input Parameters:
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*
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* irq_count - A previously allocated pointer to store the counter of the
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* interrupts that ran when non-IRAM interrupts were disabled.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32s3_get_iram_interrupt_records(uint64_t *irq_count);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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File diff suppressed because it is too large
Load Diff
@@ -521,6 +521,19 @@ static inline bool IRAM_ATTR esp32s3_ptr_extram(const void *p)
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(intptr_t)p < SOC_EXTRAM_DATA_HIGH);
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}
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/****************************************************************************
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* Name: esp32s3_ptr_iram
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*
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* Description:
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* Check if the pointer is in IRAM
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*
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****************************************************************************/
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static inline bool IRAM_ATTR esp32s3_ptr_iram(const void *p)
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{
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return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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}
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/****************************************************************************
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* Name: esp32s3_ptr_exec
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*
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@@ -76,24 +76,30 @@ SECTIONS
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*(.iram1 .iram1.*)
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*libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*)
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*libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*)
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*libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
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*libarch.a:xtensa_modifyreg32.*(.literal.modifyreg32 .text.modifyreg32)
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*libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*)
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*libsched.a:assert.*(.literal .text .literal.* .text.*)
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*libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
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*libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
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*libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*)
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*libsched.a:sched_note.*(.literal .text .literal.* .text.*)
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*libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
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*libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
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*libsched.a:spinlock.*(.literal .text .literal.* .text.*)
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#ifdef CONFIG_ESP32S3_SPEED_UP_ISR
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*libarch.a:xtensa_irqdispatch.*(.literal.xtensa_irq_dispatch .text.xtensa_irq_dispatch)
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*libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context)
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*libarch.a:xtensa_modifyreg32.*(.literal.modifyreg32 .text.modifyreg32)
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*libarch.a:esp32s3_irq.*(.literal.xtensa_int_decode .text.xtensa_int_decode)
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*libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr)
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*libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle)
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*libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \
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@@ -195,6 +201,7 @@ SECTIONS
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*(.dram1 .dram1.*)
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*libphy.a:(.rodata .rodata.*)
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*libarch.a:xtensa_context.*(.rodata .rodata.*)
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_edata = ABSOLUTE(.);
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. = ALIGN(4);
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