mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 08:36:24 +08:00
stm32: add stm32g43x support and nucleo-g431rb board
This commit is contained in:
raiden00pl
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
258fc77999
commit
0c05f2ea38
@@ -2347,6 +2347,141 @@
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
|
||||
|
||||
#elif defined (CONFIG_ARCH_CHIP_STM32G431K)
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */
|
||||
# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA
|
||||
* (1) 32-bit general timers TIM2 with DMA
|
||||
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
|
||||
# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
|
||||
# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
|
||||
# define STM32_NUSART 2 /* USART1-2 */
|
||||
# define STM32_NI2C 3 /* I2C1-3 */
|
||||
# define STM32_NCAN 1 /* FDCAN1 */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
|
||||
* with LPM and BCD support) */
|
||||
# define STM32_NGPIO 26 /* GPIOA-G */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2 */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */
|
||||
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined (CONFIG_ARCH_CHIP_STM32G431C)
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */
|
||||
# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA
|
||||
* (1) 32-bit general timers TIM2 with DMA
|
||||
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
|
||||
# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
|
||||
# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
|
||||
# define STM32_NUSART 3 /* USART1-3 */
|
||||
# define STM32_NI2C 3 /* I2C1-3 */
|
||||
# define STM32_NCAN 1 /* FDCAN1 */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
|
||||
* with LPM and BCD support) */
|
||||
# define STM32_NGPIO 42 /* GPIOA-G */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2 */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */
|
||||
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined (CONFIG_ARCH_CHIP_STM32G431R)
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */
|
||||
# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA
|
||||
* (1) 32-bit general timers TIM2 with DMA
|
||||
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
|
||||
# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
|
||||
# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
|
||||
# define STM32_NUSART 4 /* USART1-3 and UART4*/
|
||||
# define STM32_NI2C 3 /* I2C1-3 */
|
||||
# define STM32_NCAN 1 /* FDCAN1 */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
|
||||
* with LPM and BCD support) */
|
||||
# define STM32_NGPIO 52 /* GPIOA-G */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2 */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */
|
||||
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined (CONFIG_ARCH_CHIP_STM32G431M)
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */
|
||||
# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA
|
||||
* (1) 32-bit general timers TIM2 with DMA
|
||||
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
|
||||
# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
|
||||
# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
|
||||
# define STM32_NUSART 4 /* USART1-3 and UART4*/
|
||||
# define STM32_NI2C 3 /* I2C1-3 */
|
||||
# define STM32_NCAN 1 /* FDCAN1 */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
|
||||
* with LPM and BCD support) */
|
||||
# define STM32_NGPIO 66 /* GPIOA-G */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2 */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */
|
||||
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined (CONFIG_ARCH_CHIP_STM32G431V)
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */
|
||||
# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA
|
||||
* (1) 32-bit general timers TIM2 with DMA
|
||||
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
|
||||
# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */
|
||||
# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
|
||||
# define STM32_NUSART 4 /* USART1-3 and UART4*/
|
||||
# define STM32_NI2C 3 /* I2C1-3 */
|
||||
# define STM32_NCAN 1 /* FDCAN1 */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NLCD 0 /* No LCD */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed
|
||||
* with LPM and BCD support) */
|
||||
# define STM32_NGPIO 86 /* GPIOA-G */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2 */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */
|
||||
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NETHERNET 0 /* No Ethernet MAC */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined (CONFIG_ARCH_CHIP_STM32G474C)
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */
|
||||
|
||||
@@ -1144,6 +1144,36 @@ config ARCH_CHIP_STM32F469N
|
||||
select STM32_STM32F469
|
||||
select STM32_HAVE_ETHMAC
|
||||
|
||||
config ARCH_CHIP_STM32G431K
|
||||
bool "STM32G474C"
|
||||
select STM32_STM32G43XX
|
||||
select STM32_STM32G4XXK
|
||||
select STM32_STM32G431K
|
||||
|
||||
config ARCH_CHIP_STM32G431C
|
||||
bool "STM32G474C"
|
||||
select STM32_STM32G43XX
|
||||
select STM32_STM32G4XXC
|
||||
select STM32_STM32G431C
|
||||
|
||||
config ARCH_CHIP_STM32G431R
|
||||
bool "STM32G474C"
|
||||
select STM32_STM32G43XX
|
||||
select STM32_STM32G4XXR
|
||||
select STM32_STM32G431R
|
||||
|
||||
config ARCH_CHIP_STM32G431M
|
||||
bool "STM32G474C"
|
||||
select STM32_STM32G43XX
|
||||
select STM32_STM32G4XXM
|
||||
select STM32_STM32G431M
|
||||
|
||||
config ARCH_CHIP_STM32G431V
|
||||
bool "STM32G474C"
|
||||
select STM32_STM32G43XX
|
||||
select STM32_STM32G4XXV
|
||||
select STM32_STM32G431V
|
||||
|
||||
config ARCH_CHIP_STM32G474C
|
||||
bool "STM32G474C"
|
||||
select STM32_STM32G47XX
|
||||
@@ -1920,6 +1950,76 @@ config STM32_STM32G4XXQ
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_STM32G43XX
|
||||
bool
|
||||
default n
|
||||
select STM32_STM32G4XXX
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_HAVE_FPU
|
||||
select STM32_HAVE_ADC2
|
||||
select STM32_HAVE_CCM
|
||||
select STM32_HAVE_COMP1
|
||||
select STM32_HAVE_COMP2
|
||||
select STM32_HAVE_COMP3
|
||||
select STM32_HAVE_COMP4
|
||||
select STM32_HAVE_CORDIC
|
||||
select STM32_HAVE_CRS
|
||||
select STM32_HAVE_DAC1
|
||||
select STM32_HAVE_DAC2
|
||||
select STM32_HAVE_FMAC
|
||||
select STM32_HAVE_FDCAN1
|
||||
select STM32_HAVE_I2C2
|
||||
select STM32_HAVE_I2C3
|
||||
select STM32_HAVE_LPTIM1
|
||||
select STM32_HAVE_LPUART1
|
||||
select STM32_HAVE_OPAMP1
|
||||
select STM32_HAVE_OPAMP2
|
||||
select STM32_HAVE_OPAMP3
|
||||
select STM32_HAVE_RNG
|
||||
select STM32_HAVE_SPI2
|
||||
select STM32_HAVE_SPI3
|
||||
select STM32_HAVE_TIM1
|
||||
select STM32_HAVE_TIM15
|
||||
select STM32_HAVE_TIM16
|
||||
select STM32_HAVE_TIM17
|
||||
select STM32_HAVE_TIM2
|
||||
select STM32_HAVE_TIM3
|
||||
select STM32_HAVE_TIM4
|
||||
select STM32_HAVE_TIM8
|
||||
select STM32_HAVE_UCPD
|
||||
select STM32_HAVE_USBDEV
|
||||
select STM32_HAVE_IP_ADC_V2
|
||||
select STM32_HAVE_IP_DMA_V1
|
||||
select STM32_HAVE_IP_I2C_V2
|
||||
select STM32_HAVE_IP_TIMERS_V1
|
||||
|
||||
config STM32_STM32G431K
|
||||
bool
|
||||
default n
|
||||
|
||||
config STM32_STM32G431C
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_USART3
|
||||
|
||||
config STM32_STM32G431R
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_UART4
|
||||
|
||||
config STM32_STM32G431M
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_UART4
|
||||
|
||||
config STM32_STM32G431V
|
||||
bool
|
||||
default n
|
||||
select STM32_HAVE_USART3
|
||||
select STM32_HAVE_UART4
|
||||
|
||||
config STM32_STM32G47XX
|
||||
bool
|
||||
default n
|
||||
|
||||
@@ -530,6 +530,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define SRAM1_END 0x20020000
|
||||
#elif defined(CONFIG_STM32_STM32G43XX)
|
||||
# define SRAM1_END 0x20005800
|
||||
#else
|
||||
# error "Unsupported STM32G4 chip"
|
||||
#endif
|
||||
@@ -540,6 +542,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32_STM32G47XX)
|
||||
# define SRAM2_END 0x10008000
|
||||
#elif defined(CONFIG_STM32_STM32G43XX)
|
||||
# define SRAM2_END 0x10002700
|
||||
#else
|
||||
# error "Unsupported STM32G4 chip"
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user