From 0c05f2ea381fb6923e294013fa86dec91a1a7a18 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 9 Dec 2020 11:28:10 +0100 Subject: [PATCH] stm32: add stm32g43x support and nucleo-g431rb board --- .../introduction/detailed_support.rst | 10 + .../introduction/supported_platforms.rst | 1 + arch/arm/include/stm32/chip.h | 135 +++++++++++++ arch/arm/src/stm32/Kconfig | 100 +++++++++ arch/arm/src/stm32/stm32_allocateheap.c | 4 + boards/Kconfig | 13 ++ boards/README.txt | 3 + boards/arm/stm32/nucleo-g431rb/Kconfig | 8 + boards/arm/stm32/nucleo-g431rb/README.txt | 10 + .../stm32/nucleo-g431rb/configs/nsh/defconfig | 52 +++++ .../arm/stm32/nucleo-g431rb/include/board.h | 191 ++++++++++++++++++ .../arm/stm32/nucleo-g431rb/scripts/Make.defs | 77 +++++++ .../arm/stm32/nucleo-g431rb/scripts/ld.script | 124 ++++++++++++ boards/arm/stm32/nucleo-g431rb/src/.gitignore | 2 + boards/arm/stm32/nucleo-g431rb/src/Make.defs | 38 ++++ .../stm32/nucleo-g431rb/src/nucleo-g431rb.h | 68 +++++++ .../stm32/nucleo-g431rb/src/stm32_appinit.c | 91 +++++++++ .../stm32/nucleo-g431rb/src/stm32_autoleds.c | 78 +++++++ .../arm/stm32/nucleo-g431rb/src/stm32_boot.c | 70 +++++++ .../stm32/nucleo-g431rb/src/stm32_userleds.c | 75 +++++++ 20 files changed, 1150 insertions(+) create mode 100644 boards/arm/stm32/nucleo-g431rb/Kconfig create mode 100644 boards/arm/stm32/nucleo-g431rb/README.txt create mode 100644 boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig create mode 100644 boards/arm/stm32/nucleo-g431rb/include/board.h create mode 100644 boards/arm/stm32/nucleo-g431rb/scripts/Make.defs create mode 100644 boards/arm/stm32/nucleo-g431rb/scripts/ld.script create mode 100644 boards/arm/stm32/nucleo-g431rb/src/.gitignore create mode 100644 boards/arm/stm32/nucleo-g431rb/src/Make.defs create mode 100644 boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h create mode 100644 boards/arm/stm32/nucleo-g431rb/src/stm32_appinit.c create mode 100644 boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c create mode 100644 boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c create mode 100644 boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c diff --git a/Documentation/introduction/detailed_support.rst b/Documentation/introduction/detailed_support.rst index 133872de569..cb21686cc7f 100644 --- a/Documentation/introduction/detailed_support.rst +++ b/Documentation/introduction/detailed_support.rst @@ -1798,6 +1798,16 @@ One board is supported in this family: **NuttX-9.1**. Initial support for booting NuttX to a functional NSH prompt on this board. +STMicro STM32 G431x +------------------- + +One board is supported in this family: + +- **Nucleo-G431RB**. Initial board support for the + Nucleo-G431RB was added in NuttX-10.0. Refer to the NuttX board + `README `__ + file for further information. + STMicro STM32 L475 ------------------ diff --git a/Documentation/introduction/supported_platforms.rst b/Documentation/introduction/supported_platforms.rst index ff2e3e5f21b..544fcf49062 100644 --- a/Documentation/introduction/supported_platforms.rst +++ b/Documentation/introduction/supported_platforms.rst @@ -246,6 +246,7 @@ MCU. Follow the links for the details: - :ref:`introduction/detailed_support:STMicro STM32 F446` (STM32 F4 family, ARM Cortex-M4) - :ref:`introduction/detailed_support:STMicro STM32 F46xx` (STM32 F4 family, ARM Cortex-M4) - :ref:`introduction/detailed_support:STMicro STM32 G474x` (STM32 G4 family, ARM Cortex-M4) + - :ref:`introduction/detailed_support:STMicro STM32 G431x` (STM32 G4 family, ARM Cortex-M4) - :ref:`introduction/detailed_support:STMicro STM32 L4x2` (STM32 L4 family, ARM Cortex-M4) - :ref:`introduction/detailed_support:STMicro STM32 L475` (STM32 L4 family, ARM Cortex-M4) - :ref:`introduction/detailed_support:STMicro STM32 L476` (STM32 L4 family, ARM Cortex-M4) diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index e77c10cd1b7..1b0a8f25a8d 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -2347,6 +2347,141 @@ # define STM32_NRNG 1 /* Random number generator (RNG) */ # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ +#elif defined (CONFIG_ARCH_CHIP_STM32G431K) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 26 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 66 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431V) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + #elif defined (CONFIG_ARCH_CHIP_STM32G474C) # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 1a3fc982971..cf6173fc138 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1144,6 +1144,36 @@ config ARCH_CHIP_STM32F469N select STM32_STM32F469 select STM32_HAVE_ETHMAC +config ARCH_CHIP_STM32G431K + bool "STM32G474C" + select STM32_STM32G43XX + select STM32_STM32G4XXK + select STM32_STM32G431K + +config ARCH_CHIP_STM32G431C + bool "STM32G474C" + select STM32_STM32G43XX + select STM32_STM32G4XXC + select STM32_STM32G431C + +config ARCH_CHIP_STM32G431R + bool "STM32G474C" + select STM32_STM32G43XX + select STM32_STM32G4XXR + select STM32_STM32G431R + +config ARCH_CHIP_STM32G431M + bool "STM32G474C" + select STM32_STM32G43XX + select STM32_STM32G4XXM + select STM32_STM32G431M + +config ARCH_CHIP_STM32G431V + bool "STM32G474C" + select STM32_STM32G43XX + select STM32_STM32G4XXV + select STM32_STM32G431V + config ARCH_CHIP_STM32G474C bool "STM32G474C" select STM32_STM32G47XX @@ -1920,6 +1950,76 @@ config STM32_STM32G4XXQ bool default n +config STM32_STM32G43XX + bool + default n + select STM32_STM32G4XXX + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + select STM32_HAVE_IP_ADC_V2 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_TIMERS_V1 + +config STM32_STM32G431K + bool + default n + +config STM32_STM32G431C + bool + default n + select STM32_HAVE_USART3 + +config STM32_STM32G431R + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431M + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431V + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + config STM32_STM32G47XX bool default n diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index b745881faa3..acd5f0c0d1f 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -530,6 +530,8 @@ #if defined(CONFIG_STM32_STM32G47XX) # define SRAM1_END 0x20020000 +#elif defined(CONFIG_STM32_STM32G43XX) +# define SRAM1_END 0x20005800 #else # error "Unsupported STM32G4 chip" #endif @@ -540,6 +542,8 @@ #if defined(CONFIG_STM32_STM32G47XX) # define SRAM2_END 0x10008000 +#elif defined(CONFIG_STM32_STM32G43XX) +# define SRAM2_END 0x10002700 #else # error "Unsupported STM32G4 chip" #endif diff --git a/boards/Kconfig b/boards/Kconfig index 464f815d248..c6da95ae08f 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1757,6 +1757,15 @@ config ARCH_BOARD_B_G474E_DPOW1 MCU, a Cortex-M4 with FPU, 170 MHz, 128 KB SRAM, 512 KB code. See boards/arm/stm32/b-g474e-dpow1/README.txt. +config ARCH_BOARD_NUCLEO_G431RB + bool "STM32G431RB Nucleo G431RB" + depends on ARCH_CHIP_STM32G431R + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + STMicro Nucleo-G431RB board based on the STMicro STM32G431RB MCU. + config ARCH_BOARD_B_L072Z_LRWAN1 bool "B-L072Z-LRWAN1" depends on ARCH_CHIP_STM32L072CZ @@ -2330,6 +2339,7 @@ config ARCH_BOARD default "stm32h747i-disco" if ARCH_BOARD_STM32H747I_DISCO default "stm32f746-ws" if ARCH_BOARD_STM32F746_WS default "b-g474e-dpow1" if ARCH_BOARD_B_G474E_DPOW1 + default "nucleo-g431rb" if ARCH_BOARD_NUCLEO_G431RB default "b-l072z-lrwan1" if ARCH_BOARD_B_L072Z_LRWAN1 default "b-l475e-iot01a" if ARCH_BOARD_B_L475E_IOT01A default "stm32l476vg-disco" if ARCH_BOARD_STM32L476VG_DISCO @@ -2652,6 +2662,9 @@ endif if ARCH_BOARD_B_G474E_DPOW1 source "boards/arm/stm32/b-g474e-dpow1/Kconfig" endif +if ARCH_BOARD_NUCLEO_G431RB +source "boards/arm/stm32/nucleo-g431rb/Kconfig" +endif if ARCH_BOARD_B_L072Z_LRWAN1 source "boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig" endif diff --git a/boards/README.txt b/boards/README.txt index 5dbdbe3bd2d..0f7afb266c6 100644 --- a/boards/README.txt +++ b/boards/README.txt @@ -186,6 +186,9 @@ boards/arm/stm32/b-g474e-dpow1 Initial support for booting NuttX to a functional NSH prompt on the STMicro B-G474E-DPOW1 Discovery kit with STM32G474RE MCU. +boards/arm/stm32/nucleo-g431rb + STMicro Nucleo G431RB board based on the STMicro STM32G431RB MCU. + boards/arm/stm32f0l0g0/b-l072z-lrwan1 STMicro STM32L0 Discovery kit with LoRa/SigFox based on STM32L072CZ MCU. diff --git a/boards/arm/stm32/nucleo-g431rb/Kconfig b/boards/arm/stm32/nucleo-g431rb/Kconfig new file mode 100644 index 00000000000..8ef0e9b152f --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_G431RB + +endif # ARCH_BOARD_NUCLEO_G431RB diff --git a/boards/arm/stm32/nucleo-g431rb/README.txt b/boards/arm/stm32/nucleo-g431rb/README.txt new file mode 100644 index 00000000000..d706431c836 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/README.txt @@ -0,0 +1,10 @@ +README +====== + +The Nucleo-G431RB is a member of the Nucleo-64 board family. The Nucleo-64 +is a standard board for use with several STM32 parts in the LQFP64 package. + +STATUS +====== + + 2020-06-12: The basic NSH configuration is now functional. diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig new file mode 100644 index 00000000000..abdd78e5479 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32/nucleo-g431rb/include/board.h new file mode 100644 index 00000000000..5d5a0e5b76b --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/include/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#undef STM32_BOARD_XTAL /* Not installed by default */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#undef STM32_HSE_FREQUENCY /* Not installed by default */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The NUCLEO-G431RB has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo G431RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is is sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G431RB supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32G431RB. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32G431RB. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART2 (STLINK Virtual COM Port) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ + +/* Pin Multiplexing Disambiguation ******************************************/ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs new file mode 100644 index 00000000000..827bf5d67de --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32/nucleo-g431rb/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ifeq ($(CONFIG_CYGWIN_WINTOOL),y) + # Windows-native toolchains + ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin -funwind-tables +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -funwind-tables +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -ffunction-sections -fdata-sections -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -ffunction-sections -fdata-sections -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +# Provide map file needed by the "Memory Allocation" view in Eclipse: +LDFLAGS += -Map=$(TOPDIR)/NuttX.map --gc-sections + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script b/boards/arm/stm32/nucleo-g431rb/scripts/ld.script new file mode 100644 index 00000000000..d9b5c13b1d6 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/scripts/ld.script @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431RB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431RB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/.gitignore b/boards/arm/stm32/nucleo-g431rb/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/arm/stm32/nucleo-g431rb/src/Make.defs b/boards/arm/stm32/nucleo-g431rb/src/Make.defs new file mode 100644 index 00000000000..40e35a14929 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/Make.defs @@ -0,0 +1,38 @@ +############################################################################ +# boards/arm/stm32/nucleo-g431rb/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h b/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h new file mode 100644 index 00000000000..b8e261d9d79 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431RB_SRC_NUCLEO_G431RB_H +#define __BOARDS_ARM_STM32_NUCLEO_G431RB_SRC_NUCLEO_G431RB_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ + +/* LED definitions **********************************************************/ + +/* The Nucleo G431RB board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V3. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32G431RB. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN5) + +#define LED_DRIVER_PATH "/dev/userleds" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_SRC_NUCLEO_G431RB_H */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_appinit.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_appinit.c new file mode 100644 index 00000000000..4e173096260 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_appinit.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/src/stm32_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a pointer + * to configuration data read from a file or serial FLASH, or + * whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + int ret; + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c new file mode 100644 index 00000000000..196e787f1e2 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c new file mode 100644 index 00000000000..cb70db41e6f --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_ARCH_LEDS) + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c new file mode 100644 index 00000000000..446921cc2f5 --- /dev/null +++ b/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */