SAMA5D4: Add partial support for secure interrupt controller (SAIC)

arch/arm/src/armv7-a/Kconfig

@@ -55,4 +55,13 @@ config ARMV7A_OABI_TOOLCHAIN
 	default n
 	depends on ARMV7A_TOOLCHAIN_BUILDROOT
 	---help---
-		Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi-
+		Most of the older buildroot toolchains are OABI and are named
+		arm-nuttx-elf- vs. arm-nuttx-eabi-
+
+config ARMV7A_DECODEFIQ
+	bool "FIQ Handler"
+	default n
+	---help---
+		Select this option if your platform supports the function
+		arm_decodefiq().  This is used primarily to support secure TrustZone
+		interrupts received on the FIQ vector.

arch/arm/src/armv7-a/arm_vectors.S

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/armv7-a/arm_vectors.S
  *
- *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -469,7 +469,8 @@ arm_vectorundefinsn:
  * Name: arm_vectorfiq
  *
  * Description:
- *   Shouldn't happen
+ *   Shouldn't happen unless a arm_decodefiq() is provided.  FIQ is primarily used
+ *   with the TrustZone feature in order to handler secure interrupts.
  *
  ************************************************************************************/
 
@@ -477,7 +478,11 @@ arm_vectorundefinsn:
 	.type	arm_vectorfiq, %function
 
 arm_vectorfiq:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+#  error Missing logic
+#else
 	subs	pc, lr, #4
+#endif
 	.size	arm_vectorfiq, . - arm_vectorfiq
 
 /************************************************************************************

arch/arm/src/sama5/Kconfig

@@ -101,6 +101,10 @@ config SAMA5_HAVE_TC2
 	bool
 	default n
 
+config SAMA5_HAVE_TRUSTZONE
+	bool
+	default n
+
 config SAMA5_HAVE_TWI3
 	bool
 	default n
@@ -135,6 +139,7 @@ config ARCH_CHIP_SAMA5D4
 	select SAMA5_HAVE_SPI2
 	select SAMA5_HAVE_TC1
 	select SAMA5_HAVE_TC2
+	select SAMA5_HAVE_TRUSTZONE
 	select SAMA5_HAVE_TWI3
 	select ARCH_NAND_HWECC
 
@@ -522,6 +527,12 @@ config SAMA5_VDEC
 
 endmenu # SAMA5 Peripheral Support
 
+config SAMA5_SECURE
+	bool "Enable secure features"
+	default n
+	depends on SAMA5_HAVE_TRUSTZONE && EXPERIMENTAL
+	select ARMV7A_DECODEFIQ if SAMA5_HAVE_SAIC
+
 config SAMA5_PIO_IRQ
 	bool "PIO pin interrupts"
 	---help---

arch/arm/src/sama5/chip/sam_aic.h

@@ -108,7 +108,7 @@
 #define SAM_AIC_WPMR           (SAM_AIC_VBASE+SAM_AIC_WPMR_OFFSET)
 #define SAM_AIC_WPSR           (SAM_AIC_VBASE+SAM_AIC_WPSR_OFFSET)
 
-#ifdef SAMA5_HAVE_SAIC
+#ifdef CONFIG_SAMA5_HAVE_SAIC
 #  define SAM_SAIC_SSR         (SAM_SAIC_VBASE+SAM_AIC_SSR_OFFSET)
 #  define SAM_SAIC_SMR         (SAM_SAIC_VBASE+SAM_AIC_SMR_OFFSET)
 #  define SAM_SAIC_SVR         (SAM_SAIC_VBASE+SAM_AIC_SVR_OFFSET)

arch/arm/src/sama5/chip/sam_matrix.h

@@ -203,6 +203,7 @@
 #  define SAM_MATRIX_SRTSR11_OFFSET      0x02ac /* Security Region Top Slave 11 Register */
 #  define SAM_MATRIX_SRTSR12_OFFSET      0x02b0 /* Security Region Top Slave 12 Register */
 
+#  define SAM_MATRIX_SPSELR_OFFSET(n)    (0x02c0 + ((n) << 2))
 #  define SAM_MATRIX_SPSELR1_OFFSET      0x02c0 /* Security Peripheral Select 1 Register */
 #  define SAM_MATRIX_SPSELR2_OFFSET      0x02c4 /* Security Peripheral Select 2 Register */
 #  define SAM_MATRIX_SPSELR3_OFFSET      0x02c8 /* Security Peripheral Select 3 Register */
@@ -290,10 +291,7 @@
 #endif /* ATSAMA5D3 */
 
 #ifdef ATSAMA5D4
-/* HMATRIX0 (H64MX)
- *
- *
- */
+/* HMATRIX0 (H64MX) */
 
 #  define SAM_MATRIX0_MCFG(n))           (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG_OFFSET(n))
 #  define SAM_MATRIX0_MCFG0              (SAM_MATRIX64_VBASE+SAM_MATRIX_MCFG0_OFFSET)
@@ -414,6 +412,7 @@
 #  define SAM_MATRIX0_SRTSR11            (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR11_OFFSET)
 #  define SAM_MATRIX0_SRTSR12            (SAM_MATRIX64_VBASE+SAM_MATRIX_SRTSR12_OFFSET)
 
+#  define SAM_MATRIX0_SPSELR(n)          (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR_OFFSET(n))
 #  define SAM_MATRIX0_SPSELR1            (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR1_OFFSET)
 #  define SAM_MATRIX0_SPSELR2            (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR2_OFFSET)
 #  define SAM_MATRIX0_SPSELR3            (SAM_MATRIX64_VBASE+SAM_MATRIX_SPSELR3_OFFSET)
@@ -539,6 +538,7 @@
 #  define SAM_MATRIX1_SRTSR11            (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR11_OFFSET)
 #  define SAM_MATRIX1_SRTSR12            (SAM_MATRIX32_VBASE+SAM_MATRIX_SRTSR12_OFFSET)
 
+#  define SAM_MATRIX1_SPSELR(n)          (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR_OFFSET(n))
 #  define SAM_MATRIX1_SPSELR1            (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR1_OFFSET)
 #  define SAM_MATRIX1_SPSELR2            (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR2_OFFSET)
 #  define SAM_MATRIX1_SPSELR3            (SAM_MATRIX32_VBASE+SAM_MATRIX_SPSELR3_OFFSET)