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nxstyle fixes.

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This commit is contained in:
Fotis Panagiotopoulos
2020-11-14 14:25:26 +02:00
committed by David Sidrane
parent f538839720
commit 09b6aca971
4 changed files with 124 additions and 112 deletions
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arch/arm/src/stm32/stm32f10xxx_rcc.c
+33 -29
View File
@@ -89,7 +89,8 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN,
STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
@@ -98,8 +99,9 @@ static inline void rcc_reset(void)
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
RCC_CFGR_PPRE2_MASK | RCC_CFGR_ADCPRE_MASK | RCC_CFGR_MCO_MASK);
regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK
| RCC_CFGR_PPRE2_MASK | RCC_CFGR_ADCPRE_MASK
| RCC_CFGR_MCO_MASK);
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
@@ -189,7 +191,8 @@ static inline void rcc_enableahb(void)
#ifdef CONFIG_STM32_ETHMAC
/* Ethernet clock enable */
regval |= (RCC_AHBENR_ETHMACEN | RCC_AHBENR_ETHMACTXEN | RCC_AHBENR_ETHMACRXEN);
regval |= (RCC_AHBENR_ETHMACEN | RCC_AHBENR_ETHMACTXEN
| RCC_AHBENR_ETHMACRXEN);
#endif
#endif
@@ -646,39 +649,40 @@ static void stm32_stdclockconfig(void)
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
{
volatile int32_t timeout;
{
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
break;
}
}
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or misconfiguration.
*/
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have
* a strategy. This is almost always a hardware failure or
* misconfiguration.
*/
return;
}
}
return;
}
}
/* If this is a value-line part and we are using the HSE as the PLL */
arch/arm/src/stm32/stm32f30xxx_rcc.c
+30 -27
View File
@@ -89,7 +89,8 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN,
STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
@@ -555,40 +556,40 @@ static void stm32_stdclockconfig(void)
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
{
volatile int32_t timeout;
{
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
break;
}
}
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or
* misconfiguration.
*/
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have
* a strategy. This is almost always a hardware failure or
* misconfiguration.
*/
return;
}
}
return;
}
}
# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
/* If this is a value-line part and we are using the HSE as the PLL */
@@ -607,6 +608,7 @@ static void stm32_stdclockconfig(void)
#ifndef CONFIG_STM32_VALUELINE
/* Value-line devices don't implement flash prefetch/waitstates */
/* Enable FLASH prefetch buffer and set FLASH wait states */
regval = getreg32(STM32_FLASH_ACR);
@@ -638,6 +640,7 @@ static void stm32_stdclockconfig(void)
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
arch/arm/src/stm32/stm32f33xxx_rcc.c
+32 -29
View File
@@ -90,7 +90,8 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN,
STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
@@ -109,8 +110,9 @@ static inline void rcc_reset(void)
putreg32(regval, STM32_RCC_CFGR2);
regval = getreg32(STM32_RCC_CFGR3); /* Reset all U[S]ARTs, I2C1, TIM1 and HRTIM1 bits */
regval &= ~(RCC_CFGR3_USART1SW_MASK | RCC_CFGR3_USART2SW_MASK | RCC_CFGR3_USART3SW_MASK | \
RCC_CFGR3_I2C1SW | RCC_CFGR3_TIM1SW | RCC_CFGR3_HRTIM1SW);
regval &= ~(RCC_CFGR3_USART1SW_MASK | RCC_CFGR3_USART2SW_MASK | \
RCC_CFGR3_USART3SW_MASK | RCC_CFGR3_I2C1SW | \
RCC_CFGR3_TIM1SW | RCC_CFGR3_HRTIM1SW);
putreg32(regval, STM32_RCC_CFGR3);
regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
@@ -374,40 +376,40 @@ static void stm32_stdclockconfig(void)
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
{
volatile int32_t timeout;
{
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
break;
}
}
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or
* misconfiguration.
*/
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have
* a strategy. This is almost always a hardware failure or
* misconfiguration.
*/
return;
}
}
return;
}
}
#endif
@@ -434,6 +436,7 @@ static void stm32_stdclockconfig(void)
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
arch/arm/src/stm32/stm32f37xxx_rcc.c
+29 -27
View File
@@ -90,7 +90,8 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN,
STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
@@ -125,7 +126,6 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
}
/****************************************************************************
* Name: rcc_enableahb
*
@@ -498,39 +498,40 @@ static void stm32_stdclockconfig(void)
/* If the PLL is using the HSE, or the HSE is the system clock */
#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
{
volatile int32_t timeout;
{
volatile int32_t timeout;
/* Enable External High-Speed Clock (HSE) */
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
break;
}
}
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have a
* strategy. This is almost always a hardware failure or misconfiguration.
*/
if (timeout == 0)
{
/* In the case of a timeout starting the HSE, we really don't have
* a strategy. This is almost always a hardware failure or
* misconfiguration.
*/
return;
}
}
return;
}
}
/* If this is a value-line part and we are using the HSE as the PLL */
@@ -575,6 +576,7 @@ static void stm32_stdclockconfig(void)
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);