risc-v/bl808: Add SPI driver

This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.

Documentation/platforms/risc-v/bl808/boards/ox64/index.rst

@@ -143,3 +143,10 @@ adc
 This configuration enables support for the general purpose ADC and the adc example app.
 By default, the ADC will scan external channels 3, 4, 6, 7 and 9 (GPIO pins 11, 6, 12,
 13 and 18). Serial Console is enabled on UART3 at 2 Mbps.
+
+spi
+---
+
+This configuration enables support for SPI0 and spitool.
+By default, GPIO14 is MISO, 13 is MOSI, 15 is SCLK and 12 is SS.
+Serial Console is enabled on UART3 at 2 Mbps.

Documentation/platforms/risc-v/bl808/index.rst

@@ -51,7 +51,7 @@ GPIO         Yes
 I2C          No
 I2S          No
 PWM          No
-SPI          No
+SPI          Yes
 Timers       No
 UART         Yes
 USB          No

arch/risc-v/include/bl808/irq.h

@@ -52,12 +52,14 @@
 /* D0 IRQs ******************************************************************/
 
 #define BL808_IRQ_UART3 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 4)
+#define BL808_IRQ_SPI1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 7)
 #define BL808_IRQ_D0_IPC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 38)
 #define BL808_IRQ_M0IC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 65)
 
 /* M0 IRQs ******************************************************************/
 
 #define BL808_IRQ_GPADC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 25)
+#define BL808_IRQ_SPI0  (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 27)
 #define BL808_IRQ_UART0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 28)
 #define BL808_IRQ_UART1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 29)
 #define BL808_IRQ_UART2 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 30)

arch/risc-v/src/bl808/Kconfig

@@ -130,4 +130,98 @@ config BL808_UART3
 	select UART3_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
+menuconfig BL808_SPI0
+	bool "SPI 0"
+	default n
+	select SPI
+
+if BL808_SPI0
+
+config BL808_SPI0_DEG_ENABLE
+	bool "Deglitch enable"
+	default y
+
+config BL808_SPI0_CONT_ENABLE
+	bool "Continuous transfer mode"
+	default y
+
+config BL808_SPI0_BYTE_INV
+	bool "Invert byte transfer order"
+	default n
+
+config BL808_SPI0_BIT_INV
+	bool "Invert bit transfer order"
+	default n
+
+comment "Refer to datasheet for valid pin assignments"
+
+config BL808_SPI0_MISO
+	int "MISO Pin"
+	default 14
+	range 0 45
+
+config BL808_SPI0_MOSI
+	int "MOSI Pin"
+	default 13
+	range 0 45
+
+config BL808_SPI0_SCLK
+	int "SCLK Pin"
+	default 15
+	range 0 45
+
+config BL808_SPI0_SS
+	int "SS Pin"
+	default 12
+	range 0 45
+
+endif
+
+menuconfig BL808_SPI1
+	bool "SPI 1"
+	default n
+	select SPI
+
+if BL808_SPI1
+
+config BL808_SPI1_DEG_ENABLE
+	bool "Deglitch enable"
+	default y
+
+config BL808_SPI1_CONT_ENABLE
+	bool "Continuous transfer mode"
+	default y
+
+config BL808_SPI1_BYTE_INV
+	bool "Invert byte transfer order"
+	default n
+
+config BL808_SPI1_BIT_INV
+	bool "Invert bit transfer order"
+	default n
+
+comment "Refer to datasheet for valid pin assignments"
+
+config BL808_SPI1_MISO
+	int "MISO Pin"
+	default 14
+	range 0 45
+
+config BL808_SPI1_MOSI
+	int "MOSI Pin"
+	default 13
+	range 0 45
+
+config BL808_SPI1_SCLK
+	int "SCLK Pin"
+	default 15
+	range 0 45
+
+config BL808_SPI1_SS
+	int "SS Pin"
+	default 12
+	range 0 45
+
+endif
+
 endmenu

arch/risc-v/src/bl808/Make.defs

@@ -28,4 +28,4 @@ HEAD_ASRC = bl808_head.S
 CHIP_CSRCS  = bl808_start.c bl808_irq_dispatch.c bl808_irq.c
 CHIP_CSRCS += bl808_timerisr.c bl808_allocateheap.c
 CHIP_CSRCS += bl808_gpio.c bl808_mm_init.c bl808_pgalloc.c bl808_serial.c
-CHIP_CSRCS += bl808_gpadc.c
+CHIP_CSRCS += bl808_gpadc.c bl808_spi.c

arch/risc-v/src/bl808/bl808_gpio.h

@@ -43,7 +43,7 @@
  * 1111 1100 0000 0000
  * 5432 1098 7654 3210
  * ---- ---- ---- ----
- * .... ..MU UDDS FFFF
+ * .... .MUU DDSF FFFF
  */
 
 /* Mode:
@@ -51,10 +51,10 @@
  * 1111 1100 0000 0000
  * 5432 1098 7654 3210
  * ---- ---- ---- ----
- * .... ..M. .... ....
+ * .... .M.. .... ....
  */
 
-#define GPIO_MODE_SHIFT  (9)                     /* Bit 9: Port Mode */
+#define GPIO_MODE_SHIFT  (10)                     /* Bit 10: Port Mode */
 #define GPIO_MODE_MASK   (1 << GPIO_MODE_SHIFT)
 #  define GPIO_INPUT     (1 << GPIO_MODE_SHIFT)  /* Input Enable */
 #  define GPIO_OUTPUT    (0 << GPIO_MODE_SHIFT)  /* Output Enable */
@@ -64,10 +64,10 @@
  * 1111 1100 0000 0000
  * 5432 1098 7654 3210
  * ---- ---- ---- ----
- * .... ...U U... ....
+ * .... ..UU .... ....
  */
 
-#define GPIO_PUPD_SHIFT (7) /* Bits 7-8: Pull-up/down */
+#define GPIO_PUPD_SHIFT (8) /* Bits 8-9: Pull-up/down */
 #define GPIO_PUPD_MASK  (3 << GPIO_PUPD_SHIFT)
 #define GPIO_FLOAT      (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
 #define GPIO_PULLUP     (1 << GPIO_PUPD_SHIFT) /* Pull-up */
@@ -78,10 +78,10 @@
  * 1111 1100 0000 0000
  * 5432 1098 7654 3210
  * ---- ---- ---- ----
- * .... .... .DD. ....
+ * .... .... DD.. ....
  */
 
-#define GPIO_DRV_SHIFT (5) /* Bits 5-6: Drive */
+#define GPIO_DRV_SHIFT (6) /* Bits 6-7: Drive */
 #define GPIO_DRV_MASK  (3 << GPIO_DRV_SHIFT)
 #define GPIO_DRV_0     (0 << GPIO_DRV_SHIFT)
 #define GPIO_DRV_1     (1 << GPIO_DRV_SHIFT)
@@ -93,10 +93,10 @@
  * 1111 1100 0000 0000
  * 5432 1098 7654 3210
  * ---- ---- ---- ----
- * .... .... ...S ....
+ * .... .... ..S. ....
  */
 
-#define GPIO_SMT_SHIFT (4) /* Bit 4: SMT Enable */
+#define GPIO_SMT_SHIFT (5) /* Bit 5: SMT Enable */
 #define GPIO_SMT_MASK  (3 << GPIO_SMT_SHIFT)
 #define GPIO_SMT_DIS   (0 << GPIO_SMT_SHIFT)
 #define GPIO_SMT_EN    (1 << GPIO_SMT_SHIFT)
@@ -106,21 +106,22 @@
  * 1111 1100 0000 0000
  * 5432 1098 7654 3210
  * ---- ---- ---- ----
- * .... .... .... FFFF
+ * .... .... ...F FFFF
  */
 
-#define GPIO_FUNC_SHIFT  (0) /* Bits 0-3: GPIO Type */
+#define GPIO_FUNC_SHIFT  (0) /* Bits 0-4: GPIO Type */
-#define GPIO_FUNC_MASK   (15 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_MASK   (0x1f << GPIO_FUNC_SHIFT)
-#define GPIO_FUNC_SDIO   (1  << GPIO_FUNC_SHIFT)  /* SDIO */
+#define GPIO_FUNC_SDH    (0  << GPIO_FUNC_SHIFT)  /* SDH */
+#define GPIO_FUNC_SPI0   (1  << GPIO_FUNC_SHIFT)  /* SPI0 */
 #define GPIO_FUNC_FLASH  (2  << GPIO_FUNC_SHIFT)  /* Flash */
-#define GPIO_FUNC_SPI    (4  << GPIO_FUNC_SHIFT)  /* SPI */
+#define GPIO_FUNC_I2C1   (6  << GPIO_FUNC_SHIFT)  /* I2C1 */
-#define GPIO_FUNC_I2C    (6  << GPIO_FUNC_SHIFT)  /* I2C */
 #define GPIO_FUNC_UART   (7  << GPIO_FUNC_SHIFT)  /* UART */
-#define GPIO_FUNC_PWM    (8  << GPIO_FUNC_SHIFT)  /* PWM */
+#define GPIO_FUNC_CAM    (9  << GPIO_FUNC_SHIFT)  /* CSI */
-#define GPIO_FUNC_EXT_PA (9  << GPIO_FUNC_SHIFT)  /* Analog */
 #define GPIO_FUNC_ANA    (10 << GPIO_FUNC_SHIFT)  /* Analog */
 #define GPIO_FUNC_SWGPIO (11 << GPIO_FUNC_SHIFT)  /* Software GPIO */
-#define GPIO_FUNC_JTAG   (14 << GPIO_FUNC_SHIFT)  /* JTAG */
+#define GPIO_FUNC_PWM0   (16 << GPIO_FUNC_SHIFT)  /* PWM0 */
+#define GPIO_FUNC_SPI1   (18 << GPIO_FUNC_SHIFT)  /* SPI1 */
+#define GPIO_FUNC_JTAG_D0 (27 << GPIO_FUNC_SHIFT) /* JTAG */
 
 /****************************************************************************
  * Public Types

arch/risc-v/src/bl808/bl808_spi.h

@@ -0,0 +1,72 @@
+/****************************************************************************
+ * arch/risc-v/src/bl808/bl808_spi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL808_BL808_SPI_H
+#define __ARCH_RISCV_SRC_BL808_BL808_SPI_H
+
+/* This file is based on bl602/bl602_spi.h */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#include <nuttx/spi/spi.h>
+#include <nuttx/spi/spi_transfer.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl808_spibus_initialize
+ *
+ * Description:
+ *   Initialize the selected SPI bus
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct spi_dev_s *bl808_spibus_initialize(int bus);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL808_BL808_SPI_H */

arch/risc-v/src/bl808/hardware/bl808_glb.h

@@ -36,6 +36,8 @@
 
 #define BL808_GLB_UART_CFG1_OFFSET    0x154
 #define BL808_GLB_UART_CFG2_OFFSET    0x158
+#define BL808_GLB_SPI_CFG0_OFFSET     0x1b0
+#define BL808_GLB_PARM_CFG0_OFFSET    0x510
 
 #define BL808_GPIO_CFG_OFFSET              0x0008c4  /* gpio_cfg0 */
 
@@ -43,15 +45,32 @@
 
 #define BL808_GLB_UART_CFG1 (BL808_GLB_BASE + BL808_GLB_UART_CFG1_OFFSET)
 #define BL808_GLB_UART_CFG2 (BL808_GLB_BASE + BL808_GLB_UART_CFG2_OFFSET)
+#define BL808_GLB_SPI_CFG0 (BL808_GLB_BASE + BL808_GLB_SPI_CFG0_OFFSET)
+#define BL808_GLB_PARM_CFG0 (BL808_GLB_BASE + BL808_GLB_PARM_CFG0_OFFSET)
 
 #define BL808_GPIO_CFG(n)        (BL808_GLB_BASE + BL808_GPIO_CFG_OFFSET + 4*n)
 
 /* Register bit definitions *************************************************/
 
 /* UART_CFG registers *******************************************************/
+
 #define UART_CFG_SIG_SEL_SHIFT(n)  ((n % 8) * 4)
 #define UART_CFG_SIG_SEL_MASK(n)   (0x0f << UART_CFG_SIG_SEL_SHIFT(n))
 
+/* SPI_CFG0 *****************************************************************/
+
+#define SPI_CFG_CLK_DIV_SHIFT 0
+#define SPI_CFG_CLK_DIV_MASK (0x1f << SPI_CFG_CLK_DIV_SHIFT)
+#define SPI_CFG_CLK_EN_SHIFT 8
+#define SPI_CFG_CLK_SEL_SHIFT 9
+#define SPI_CFG_SWAP_SET_SHIFT 16
+#define SPI_CFG_SWAP_SET_MASK (0x0f << SPI_CFG_SWAP_SET_SHIFT);
+
+/* PARM_CFG0 ****************************************************************/
+
+#define PARM_SPI_0_MASTER_MODE_SHIFT 12
+#define PARM_MM_SPI_MASTER_MODE_SHIFT 27
+
 /* GPIO_CFG registers *******************************************************/
 
 /* bit definitions from lupyuen's wip-nuttx, branch gpio2 *******************/

arch/risc-v/src/bl808/hardware/bl808_memorymap.h

@@ -33,9 +33,12 @@
 #define BL808_GPADC_BASE   0x20002000ul
 #define BL808_UART0_BASE   0x2000a000ul
 #define BL808_UART1_BASE   0x2000a100ul
+#define BL808_SPI0_BASE    0x2000a200ul
 #define BL808_UART2_BASE   0x2000aa00ul
 #define BL808_AON_BASE     0x2000f000ul
 #define BL808_UART3_BASE   0x30002000ul
+#define BL808_MM_GLB_BASE  0x30007000ul
+#define BL808_SPI1_BASE    0x30008000ul
 #define BL808_PLIC_BASE    0xe0000000ul
 
 #endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MEMORYMAP_H */

arch/risc-v/src/bl808/hardware/bl808_mm_glb.h

@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/risc-v/src/bl808/hardware/bl808_mm_glb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MM_GLB_H
+#define __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MM_GLB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "bl808_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define BL808_MM_GLB_CLK_CTRL_PERI_OFFSET 0x10
+
+/* Register definitions *****************************************************/
+
+#define BL808_MM_GLB_CLK_CTRL_PERI (BL808_MM_GLB_BASE \
+                                   + BL808_MM_GLB_CLK_CTRL_PERI_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+/* CLK_CTRL_PERI ************************************************************/
+
+#define CLK_CTRL_PERI_I2C0_DIV_SHIFT 0
+#define CLK_CTRL_PERI_I2C0_DIV_MASK (0xff << CLK_CTRL_PERI_I2C0_DIV_SHIFT)
+#define CLK_CTRL_PERI_I2C0_EN_SHIFT 9
+#define CLK_CTRL_PERI_UART_DIV_EN_SHIFT 16
+#define CLK_CTRL_PERI_UART_DIV_SHIFT 17
+#define CLK_CTRL_PERI_UART_DIV_MASK (0x07 << CLK_CTRL_PERI_UART_DIV_SHIFT)
+#define CLK_CTRL_PERI_SPI_DIV_EN_SHIFT 23
+#define CLK_CTRL_PERI_SPI_DIV_SHIFT 24
+#define CLK_CTRL_PERI_SPI_DIV_MASK (0xff << CLK_CTRL_PERI_SPI_DIV_SHIFT)
+
+#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MM_GLB_H */

arch/risc-v/src/bl808/hardware/bl808_spi.h

@@ -0,0 +1,144 @@
+/****************************************************************************
+ * arch/risc-v/src/bl808/hardware/bl808_spi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_SPI_H
+#define __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_SPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "bl808_memorymap.h"
+
+/* This file is based on bl602/hardware/bl602_spi.h */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BL808_SPI_BASE(n) ((n == 0) ? BL808_SPI0_BASE \
+                           : BL808_SPI1_BASE)
+
+/* Register offsets *********************************************************/
+
+#define BL808_SPI_CFG_OFFSET            0x000000  /* spi_config */
+#define BL808_SPI_INT_STS_OFFSET        0x000004  /* spi_int_sts */
+#define BL808_SPI_BUS_BUSY_OFFSET       0x000008  /* spi_bus_busy */
+#define BL808_SPI_PRD_0_OFFSET          0x000010  /* spi_prd_0 */
+#define BL808_SPI_PRD_1_OFFSET          0x000014  /* spi_prd_1 */
+#define BL808_SPI_RXD_IGNR_OFFSET       0x000018  /* spi_rxd_ignr */
+#define BL808_SPI_STO_VALUE_OFFSET      0x00001c  /* spi_sto_value */
+#define BL808_SPI_FIFO_CFG_0_OFFSET     0x000080  /* spi_fifo_config_0 */
+#define BL808_SPI_FIFO_CFG_1_OFFSET     0x000084  /* spi_fifo_config_1 */
+#define BL808_SPI_FIFO_WDATA_OFFSET     0x000088  /* spi_fifo_wdata */
+#define BL808_SPI_FIFO_RDATA_OFFSET     0x00008c  /* spi_fifo_rdata */
+
+/* Register definitions *****************************************************/
+
+#define BL808_SPI_CFG(n)         (BL808_SPI_BASE(n) + BL808_SPI_CFG_OFFSET)
+#define BL808_SPI_INT_STS(n)     (BL808_SPI_BASE(n) + BL808_SPI_INT_STS_OFFSET)
+#define BL808_SPI_BUS_BUSY(n)    (BL808_SPI_BASE(n) + BL808_SPI_BUS_BUSY_OFFSET)
+#define BL808_SPI_PRD_0(n)       (BL808_SPI_BASE(n) + BL808_SPI_PRD_0_OFFSET)
+#define BL808_SPI_PRD_1(n)       (BL808_SPI_BASE(n) + BL808_SPI_PRD_1_OFFSET)
+#define BL808_SPI_RXD_IGNR(n)    (BL808_SPI_BASE(n) + BL808_SPI_RXD_IGNR_OFFSET)
+#define BL808_SPI_STO_VALUE(n)   (BL808_SPI_BASE(n) + BL808_SPI_STO_VALUE_OFFSET)
+#define BL808_SPI_FIFO_CFG_0(n)  (BL808_SPI_BASE(n) + BL808_SPI_FIFO_CFG_0_OFFSET)
+#define BL808_SPI_FIFO_CFG_1(n)  (BL808_SPI_BASE(n) + BL808_SPI_FIFO_CFG_1_OFFSET)
+#define BL808_SPI_FIFO_WDATA(n)  (BL808_SPI_BASE(n) + BL808_SPI_FIFO_WDATA_OFFSET)
+#define BL808_SPI_FIFO_RDATA(n)  (BL808_SPI_BASE(n) + BL808_SPI_FIFO_RDATA_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+#define SPI_CFG_CR_DEG_CNT_SHIFT      (12)
+#define SPI_CFG_CR_DEG_CNT_MASK       (0x0f << SPI_CFG_CR_DEG_CNT_SHIFT)
+#define SPI_CFG_CR_DEG_EN             (1 << 11)
+#define SPI_CFG_CR_M_CONT_EN          (1 << 9)
+#define SPI_CFG_CR_RXD_IGNR_EN        (1 << 8)
+#define SPI_CFG_CR_BYTE_INV           (1 << 7)
+#define SPI_CFG_CR_BIT_INV            (1 << 6)
+#define SPI_CFG_CR_SCLK_PH            (1 << 5)
+#define SPI_CFG_CR_SCLK_POL           (1 << 4)
+#define SPI_CFG_CR_FRAME_SIZE_SHIFT   (2)
+#define SPI_CFG_CR_FRAME_SIZE_MASK    (0x03 << SPI_CFG_CR_FRAME_SIZE_SHIFT)
+#define SPI_CFG_CR_S_EN               (1 << 1)
+#define SPI_CFG_CR_M_EN               (1 << 0)
+
+#define SPI_INT_STS_CR_FER_EN         (1 << 29)
+#define SPI_INT_STS_CR_TXU_EN         (1 << 28)
+#define SPI_INT_STS_CR_STO_EN         (1 << 27)
+#define SPI_INT_STS_CR_RXF_EN         (1 << 26)
+#define SPI_INT_STS_CR_TXF_EN         (1 << 25)
+#define SPI_INT_STS_CR_END_EN         (1 << 24)
+#define SPI_INT_STS_RSVD_21           (1 << 21)
+#define SPI_INT_STS_CR_TXU_CLR        (1 << 20)
+#define SPI_INT_STS_CR_STO_CLR        (1 << 19)
+#define SPI_INT_STS_RSVD_18           (1 << 18)
+#define SPI_INT_STS_RSVD_17           (1 << 17)
+#define SPI_INT_STS_CR_END_CLR        (1 << 16)
+#define SPI_INT_STS_CR_FER_MASK       (1 << 13)
+#define SPI_INT_STS_CR_TXU_MASK       (1 << 12)
+#define SPI_INT_STS_CR_STO_MASK       (1 << 11)
+#define SPI_INT_STS_CR_RXF_MASK       (1 << 10)
+#define SPI_INT_STS_CR_TXF_MASK       (1 << 9)
+#define SPI_INT_STS_CR_END_MASK       (1 << 8)
+#define SPI_INT_STS_FER_INT           (1 << 5)
+#define SPI_INT_STS_TXU_INT           (1 << 4)
+#define SPI_INT_STS_STO_INT           (1 << 3)
+#define SPI_INT_STS_RXF_INT           (1 << 2)
+#define SPI_INT_STS_TXF_INT           (1 << 1)
+#define SPI_INT_STS_END_INT           (1 << 0)
+
+#define SPI_BUS_BUSY_STS_BUS_BUSY     (1 << 0)
+
+#define SPI_PRD_0_CR_D_PH_1_SHIFT     (24)
+#define SPI_PRD_0_CR_D_PH_1_MASK      (0xff << SPI_PRD_0_CR_D_PH_1_SHIFT)
+#define SPI_PRD_0_CR_D_PH_0_SHIFT     (16)
+#define SPI_PRD_0_CR_D_PH_0_MASK      (0xff << SPI_PRD_0_CR_D_PH_0_SHIFT)
+#define SPI_PRD_0_CR_P_SHIFT          (8)
+#define SPI_PRD_0_CR_P_MASK           (0xff << SPI_PRD_0_CR_P_SHIFT)
+#define SPI_PRD_0_CR_S_MASK           (0xff)
+
+#define SPI_PRD_1_CR_I_MASK           (0xff)
+
+#define SPI_RXD_IGNR_CR_IGNR_S_SHIFT  (16)
+#define SPI_RXD_IGNR_CR_IGNR_S_MASK   (0x1f << SPI_RXD_IGNR_CR_RXD_IGNR_S_SHIFT)
+#define SPI_RXD_IGNR_CR_IGNR_P_MASK   (0x1f)
+
+#define SPI_STO_VALUE_CR_VALUE_MASK   (0xfff)
+
+#define SPI_FIFO_CFG_0_RX_UNDERFLOW   (1 << 7)
+#define SPI_FIFO_CFG_0_RX_OVERFLOW    (1 << 6)
+#define SPI_FIFO_CFG_0_TX_UNDERFLOW   (1 << 5)
+#define SPI_FIFO_CFG_0_TX_OVERFLOW    (1 << 4)
+#define SPI_FIFO_CFG_0_RX_CLR         (1 << 3)
+#define SPI_FIFO_CFG_0_TX_CLR         (1 << 2)
+#define SPI_FIFO_CFG_0_DMA_RX_EN       (1 << 1)
+#define SPI_FIFO_CFG_0_DMA_TX_EN       (1 << 0)
+
+#define SPI_FIFO_CFG_1_RX_TH_SHIFT    (24)
+#define SPI_FIFO_CFG_1_RX_TH_MASK     (0x1f << SPI_FIFO_CFG_1_RX_TH_SHIFT)
+#define SPI_FIFO_CFG_1_TX_TH_SHIFT    (16)
+#define SPI_FIFO_CFG_1_TX_TH_MASK     (0x1f << SPI_FIFO_CFG_1_TX_TH_SHIFT)
+#define SPI_FIFO_CFG_1_RX_CNT_SHIFT   (8)
+#define SPI_FIFO_CFG_1_RX_CNT_MASK    (0x3f << SPI_FIFO_CFG_1_RX_CNT_SHIFT)
+#define SPI_FIFO_CFG_1_TX_CNT_MASK    (0x3f)
+
+#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_SPI_H */

boards/risc-v/bl808/ox64/configs/spi/defconfig

@@ -0,0 +1,100 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_DISABLE_OS_API is not set
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_ADDRENV=y
+CONFIG_ARCH_BOARD="ox64"
+CONFIG_ARCH_BOARD_BL808_OX64=y
+CONFIG_ARCH_CHIP="bl808"
+CONFIG_ARCH_CHIP_BL808=y
+CONFIG_ARCH_DATA_NPAGES=128
+CONFIG_ARCH_DATA_VBASE=0x80100000
+CONFIG_ARCH_HEAP_NPAGES=128
+CONFIG_ARCH_HEAP_VBASE=0x80200000
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_KERNEL_STACKSIZE=3072
+CONFIG_ARCH_PGPOOL_MAPPING=y
+CONFIG_ARCH_PGPOOL_PBASE=0x50600000
+CONFIG_ARCH_PGPOOL_SIZE=4194304
+CONFIG_ARCH_PGPOOL_VBASE=0x50600000
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_TEXT_NPAGES=128
+CONFIG_ARCH_TEXT_VBASE=0x80000000
+CONFIG_ARCH_USE_MMU=y
+CONFIG_ARCH_USE_MPU=y
+CONFIG_ARCH_USE_S_MODE=y
+CONFIG_BL808_SPI0=y
+CONFIG_BL808_UART0=y
+CONFIG_BL808_UART1=y
+CONFIG_BL808_UART2=y
+CONFIG_BL808_UART3=y
+CONFIG_BOARDCTL_ROMDISK=y
+CONFIG_BOARD_LATE_INITIALIZE=y
+CONFIG_BOARD_LOOPSPERMSEC=1120
+CONFIG_BUILD_KERNEL=y
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEV_ZERO=y
+CONFIG_ELF=y
+CONFIG_EXAMPLES_HELLO=m
+CONFIG_FS_PROCFS=y
+CONFIG_FS_ROMFS=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_FILEPATH="/system/bin/init"
+CONFIG_INIT_MOUNT=y
+CONFIG_INIT_MOUNT_FLAGS=0x1
+CONFIG_INIT_MOUNT_TARGET="/system/bin"
+CONFIG_INIT_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_ENVPATH=y
+CONFIG_LIBC_EXECFUNCS=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MEMSET_64BIT=y
+CONFIG_MEMSET_OPTSPEED=y
+CONFIG_MM_PGALLOC=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_FILE_APPS=y
+CONFIG_NSH_READLINE=y
+CONFIG_PATH_INITIAL="/system/bin"
+CONFIG_RAM_SIZE=1048576
+CONFIG_RAM_START=0x50200000
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HAVE_PARENT=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2021
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_PROGNAME="init"
+CONFIG_SYSTEM_SPITOOL=y
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_OSTEST=y
+CONFIG_UART0_BAUD=2000000
+CONFIG_UART0_BITS=7
+CONFIG_UART1_BAUD=2000000
+CONFIG_UART1_BITS=7
+CONFIG_UART2_BAUD=2000000
+CONFIG_UART2_BITS=7
+CONFIG_UART3_BAUD=2000000
+CONFIG_UART3_BITS=7
+CONFIG_UART3_SERIAL_CONSOLE=y
+CONFIG_USEC_PER_TICK=1000
+CONFIG_USERLED=y
+CONFIG_USERLED_LOWER=y

boards/risc-v/bl808/ox64/src/bl808_appinit.c

@@ -38,6 +38,9 @@
 #ifdef CONFIG_USERLED
 #include <nuttx/leds/userled.h>
 #endif
+#if defined(CONFIG_BL808_SPI0) || defined(CONFIG_BL808_SPI1)
+#include "bl808_spi.h"
+#endif
 #include "bl808_gpadc.h"
 
 /****************************************************************************
@@ -170,6 +173,16 @@ void board_late_initialize(void)
 
 #endif
 
+#ifdef CONFIG_BL808_SPI0
+  struct spi_dev_s *spi0 = bl808_spibus_initialize(0);
+  spi_register(spi0, 0);
+#endif
+
+#ifdef CONFIG_BL808_SPI1
+  struct spi_dev_s *spi1 = bl808_spibus_initialize(1);
+  spi_register(spi1, 1);
+#endif
+
 #ifdef CONFIG_NSH_ARCHINIT
 
   mount(NULL, "/proc", "procfs", 0, NULL);