mirror of
https://github.com/apache/nuttx.git
synced 2026-05-21 04:52:02 +08:00
risc-v/bl808: Add SPI driver
This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.
This commit is contained in:
Henry Rovner
Xiang Xiao
@@ -143,3 +143,10 @@ adc
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This configuration enables support for the general purpose ADC and the adc example app.
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By default, the ADC will scan external channels 3, 4, 6, 7 and 9 (GPIO pins 11, 6, 12,
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13 and 18). Serial Console is enabled on UART3 at 2 Mbps.
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spi
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---
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This configuration enables support for SPI0 and spitool.
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By default, GPIO14 is MISO, 13 is MOSI, 15 is SCLK and 12 is SS.
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Serial Console is enabled on UART3 at 2 Mbps.
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@@ -51,7 +51,7 @@ GPIO Yes
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I2C No
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I2S No
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PWM No
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SPI No
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SPI Yes
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Timers No
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UART Yes
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USB No
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@@ -52,12 +52,14 @@
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/* D0 IRQs ******************************************************************/
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#define BL808_IRQ_UART3 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 4)
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#define BL808_IRQ_SPI1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 7)
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#define BL808_IRQ_D0_IPC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 38)
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#define BL808_IRQ_M0IC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + 65)
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/* M0 IRQs ******************************************************************/
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#define BL808_IRQ_GPADC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 25)
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#define BL808_IRQ_SPI0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 27)
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#define BL808_IRQ_UART0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 28)
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#define BL808_IRQ_UART1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 29)
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#define BL808_IRQ_UART2 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 30)
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@@ -130,4 +130,98 @@ config BL808_UART3
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select UART3_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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menuconfig BL808_SPI0
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bool "SPI 0"
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default n
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select SPI
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if BL808_SPI0
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config BL808_SPI0_DEG_ENABLE
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bool "Deglitch enable"
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default y
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config BL808_SPI0_CONT_ENABLE
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bool "Continuous transfer mode"
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default y
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config BL808_SPI0_BYTE_INV
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bool "Invert byte transfer order"
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default n
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config BL808_SPI0_BIT_INV
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bool "Invert bit transfer order"
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default n
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comment "Refer to datasheet for valid pin assignments"
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config BL808_SPI0_MISO
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int "MISO Pin"
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default 14
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range 0 45
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config BL808_SPI0_MOSI
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int "MOSI Pin"
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default 13
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range 0 45
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config BL808_SPI0_SCLK
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int "SCLK Pin"
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default 15
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range 0 45
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config BL808_SPI0_SS
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int "SS Pin"
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default 12
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range 0 45
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endif
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menuconfig BL808_SPI1
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bool "SPI 1"
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default n
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select SPI
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if BL808_SPI1
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config BL808_SPI1_DEG_ENABLE
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bool "Deglitch enable"
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default y
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config BL808_SPI1_CONT_ENABLE
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bool "Continuous transfer mode"
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default y
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config BL808_SPI1_BYTE_INV
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bool "Invert byte transfer order"
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default n
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config BL808_SPI1_BIT_INV
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bool "Invert bit transfer order"
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default n
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comment "Refer to datasheet for valid pin assignments"
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config BL808_SPI1_MISO
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int "MISO Pin"
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default 14
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range 0 45
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config BL808_SPI1_MOSI
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int "MOSI Pin"
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default 13
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range 0 45
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config BL808_SPI1_SCLK
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int "SCLK Pin"
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default 15
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range 0 45
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config BL808_SPI1_SS
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int "SS Pin"
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default 12
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range 0 45
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endif
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endmenu
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@@ -28,4 +28,4 @@ HEAD_ASRC = bl808_head.S
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CHIP_CSRCS = bl808_start.c bl808_irq_dispatch.c bl808_irq.c
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CHIP_CSRCS += bl808_timerisr.c bl808_allocateheap.c
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CHIP_CSRCS += bl808_gpio.c bl808_mm_init.c bl808_pgalloc.c bl808_serial.c
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CHIP_CSRCS += bl808_gpadc.c
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CHIP_CSRCS += bl808_gpadc.c bl808_spi.c
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@@ -43,7 +43,7 @@
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* 1111 1100 0000 0000
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* 5432 1098 7654 3210
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* ---- ---- ---- ----
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* .... ..MU UDDS FFFF
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* .... .MUU DDSF FFFF
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*/
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/* Mode:
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@@ -51,10 +51,10 @@
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* 1111 1100 0000 0000
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* 5432 1098 7654 3210
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* ---- ---- ---- ----
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* .... ..M. .... ....
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* .... .M.. .... ....
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*/
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#define GPIO_MODE_SHIFT (9) /* Bit 9: Port Mode */
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#define GPIO_MODE_SHIFT (10) /* Bit 10: Port Mode */
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#define GPIO_MODE_MASK (1 << GPIO_MODE_SHIFT)
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# define GPIO_INPUT (1 << GPIO_MODE_SHIFT) /* Input Enable */
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# define GPIO_OUTPUT (0 << GPIO_MODE_SHIFT) /* Output Enable */
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@@ -64,10 +64,10 @@
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* 1111 1100 0000 0000
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* 5432 1098 7654 3210
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* ---- ---- ---- ----
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* .... ...U U... ....
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* .... ..UU .... ....
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*/
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#define GPIO_PUPD_SHIFT (7) /* Bits 7-8: Pull-up/down */
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#define GPIO_PUPD_SHIFT (8) /* Bits 8-9: Pull-up/down */
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#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
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#define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
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#define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
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@@ -78,10 +78,10 @@
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* 1111 1100 0000 0000
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* 5432 1098 7654 3210
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* ---- ---- ---- ----
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* .... .... .DD. ....
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* .... .... DD.. ....
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*/
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#define GPIO_DRV_SHIFT (5) /* Bits 5-6: Drive */
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#define GPIO_DRV_SHIFT (6) /* Bits 6-7: Drive */
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#define GPIO_DRV_MASK (3 << GPIO_DRV_SHIFT)
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#define GPIO_DRV_0 (0 << GPIO_DRV_SHIFT)
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#define GPIO_DRV_1 (1 << GPIO_DRV_SHIFT)
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@@ -93,10 +93,10 @@
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* 1111 1100 0000 0000
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* 5432 1098 7654 3210
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* ---- ---- ---- ----
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* .... .... ...S ....
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* .... .... ..S. ....
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*/
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#define GPIO_SMT_SHIFT (4) /* Bit 4: SMT Enable */
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#define GPIO_SMT_SHIFT (5) /* Bit 5: SMT Enable */
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#define GPIO_SMT_MASK (3 << GPIO_SMT_SHIFT)
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#define GPIO_SMT_DIS (0 << GPIO_SMT_SHIFT)
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#define GPIO_SMT_EN (1 << GPIO_SMT_SHIFT)
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@@ -106,21 +106,22 @@
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* 1111 1100 0000 0000
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* 5432 1098 7654 3210
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* ---- ---- ---- ----
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* .... .... .... FFFF
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* .... .... ...F FFFF
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*/
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#define GPIO_FUNC_SHIFT (0) /* Bits 0-3: GPIO Type */
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#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT)
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#define GPIO_FUNC_SDIO (1 << GPIO_FUNC_SHIFT) /* SDIO */
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#define GPIO_FUNC_SHIFT (0) /* Bits 0-4: GPIO Type */
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#define GPIO_FUNC_MASK (0x1f << GPIO_FUNC_SHIFT)
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#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) /* SDH */
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#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT) /* SPI0 */
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#define GPIO_FUNC_FLASH (2 << GPIO_FUNC_SHIFT) /* Flash */
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#define GPIO_FUNC_SPI (4 << GPIO_FUNC_SHIFT) /* SPI */
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#define GPIO_FUNC_I2C (6 << GPIO_FUNC_SHIFT) /* I2C */
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#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT) /* I2C1 */
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#define GPIO_FUNC_UART (7 << GPIO_FUNC_SHIFT) /* UART */
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#define GPIO_FUNC_PWM (8 << GPIO_FUNC_SHIFT) /* PWM */
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#define GPIO_FUNC_EXT_PA (9 << GPIO_FUNC_SHIFT) /* Analog */
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#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT) /* CSI */
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#define GPIO_FUNC_ANA (10 << GPIO_FUNC_SHIFT) /* Analog */
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#define GPIO_FUNC_SWGPIO (11 << GPIO_FUNC_SHIFT) /* Software GPIO */
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#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT) /* JTAG */
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#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) /* PWM0 */
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#define GPIO_FUNC_SPI1 (18 << GPIO_FUNC_SHIFT) /* SPI1 */
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#define GPIO_FUNC_JTAG_D0 (27 << GPIO_FUNC_SHIFT) /* JTAG */
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/****************************************************************************
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* Public Types
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
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/****************************************************************************
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* arch/risc-v/src/bl808/bl808_spi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_BL808_BL808_SPI_H
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#define __ARCH_RISCV_SRC_BL808_BL808_SPI_H
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/* This file is based on bl602/bl602_spi.h */
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#include <nuttx/spi/spi.h>
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#include <nuttx/spi/spi_transfer.h>
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: bl808_spibus_initialize
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*
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* Description:
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* Initialize the selected SPI bus
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*
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* Input Parameters:
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* Port number (for hardware that has multiple SPI interfaces)
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*
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* Returned Value:
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* Valid SPI device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct spi_dev_s *bl808_spibus_initialize(int bus);
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#ifdef __cplusplus
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_RISCV_SRC_BL808_BL808_SPI_H */
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@@ -36,6 +36,8 @@
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#define BL808_GLB_UART_CFG1_OFFSET 0x154
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#define BL808_GLB_UART_CFG2_OFFSET 0x158
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#define BL808_GLB_SPI_CFG0_OFFSET 0x1b0
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#define BL808_GLB_PARM_CFG0_OFFSET 0x510
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#define BL808_GPIO_CFG_OFFSET 0x0008c4 /* gpio_cfg0 */
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@@ -43,15 +45,32 @@
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#define BL808_GLB_UART_CFG1 (BL808_GLB_BASE + BL808_GLB_UART_CFG1_OFFSET)
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#define BL808_GLB_UART_CFG2 (BL808_GLB_BASE + BL808_GLB_UART_CFG2_OFFSET)
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#define BL808_GLB_SPI_CFG0 (BL808_GLB_BASE + BL808_GLB_SPI_CFG0_OFFSET)
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#define BL808_GLB_PARM_CFG0 (BL808_GLB_BASE + BL808_GLB_PARM_CFG0_OFFSET)
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#define BL808_GPIO_CFG(n) (BL808_GLB_BASE + BL808_GPIO_CFG_OFFSET + 4*n)
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/* Register bit definitions *************************************************/
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/* UART_CFG registers *******************************************************/
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#define UART_CFG_SIG_SEL_SHIFT(n) ((n % 8) * 4)
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#define UART_CFG_SIG_SEL_MASK(n) (0x0f << UART_CFG_SIG_SEL_SHIFT(n))
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/* SPI_CFG0 *****************************************************************/
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#define SPI_CFG_CLK_DIV_SHIFT 0
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#define SPI_CFG_CLK_DIV_MASK (0x1f << SPI_CFG_CLK_DIV_SHIFT)
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#define SPI_CFG_CLK_EN_SHIFT 8
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#define SPI_CFG_CLK_SEL_SHIFT 9
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#define SPI_CFG_SWAP_SET_SHIFT 16
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#define SPI_CFG_SWAP_SET_MASK (0x0f << SPI_CFG_SWAP_SET_SHIFT);
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/* PARM_CFG0 ****************************************************************/
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#define PARM_SPI_0_MASTER_MODE_SHIFT 12
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#define PARM_MM_SPI_MASTER_MODE_SHIFT 27
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/* GPIO_CFG registers *******************************************************/
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/* bit definitions from lupyuen's wip-nuttx, branch gpio2 *******************/
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@@ -33,9 +33,12 @@
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#define BL808_GPADC_BASE 0x20002000ul
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#define BL808_UART0_BASE 0x2000a000ul
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#define BL808_UART1_BASE 0x2000a100ul
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#define BL808_SPI0_BASE 0x2000a200ul
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#define BL808_UART2_BASE 0x2000aa00ul
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#define BL808_AON_BASE 0x2000f000ul
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#define BL808_UART3_BASE 0x30002000ul
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#define BL808_MM_GLB_BASE 0x30007000ul
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#define BL808_SPI1_BASE 0x30008000ul
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#define BL808_PLIC_BASE 0xe0000000ul
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#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MEMORYMAP_H */
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@@ -0,0 +1,58 @@
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/****************************************************************************
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* arch/risc-v/src/bl808/hardware/bl808_mm_glb.h
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*
|
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* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
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#ifndef __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MM_GLB_H
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#define __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MM_GLB_H
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/****************************************************************************
|
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* Included Files
|
||||
****************************************************************************/
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#include <nuttx/config.h>
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#include "bl808_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
|
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****************************************************************************/
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|
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/* Register offsets *********************************************************/
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#define BL808_MM_GLB_CLK_CTRL_PERI_OFFSET 0x10
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|
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/* Register definitions *****************************************************/
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#define BL808_MM_GLB_CLK_CTRL_PERI (BL808_MM_GLB_BASE \
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+ BL808_MM_GLB_CLK_CTRL_PERI_OFFSET)
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|
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/* Register bit definitions *************************************************/
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/* CLK_CTRL_PERI ************************************************************/
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#define CLK_CTRL_PERI_I2C0_DIV_SHIFT 0
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#define CLK_CTRL_PERI_I2C0_DIV_MASK (0xff << CLK_CTRL_PERI_I2C0_DIV_SHIFT)
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#define CLK_CTRL_PERI_I2C0_EN_SHIFT 9
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#define CLK_CTRL_PERI_UART_DIV_EN_SHIFT 16
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#define CLK_CTRL_PERI_UART_DIV_SHIFT 17
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#define CLK_CTRL_PERI_UART_DIV_MASK (0x07 << CLK_CTRL_PERI_UART_DIV_SHIFT)
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#define CLK_CTRL_PERI_SPI_DIV_EN_SHIFT 23
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#define CLK_CTRL_PERI_SPI_DIV_SHIFT 24
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#define CLK_CTRL_PERI_SPI_DIV_MASK (0xff << CLK_CTRL_PERI_SPI_DIV_SHIFT)
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||||
|
||||
#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_MM_GLB_H */
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||||
@@ -0,0 +1,144 @@
|
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/****************************************************************************
|
||||
* arch/risc-v/src/bl808/hardware/bl808_spi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_SPI_H
|
||||
#define __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_SPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "bl808_memorymap.h"
|
||||
|
||||
/* This file is based on bl602/hardware/bl602_spi.h */
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define BL808_SPI_BASE(n) ((n == 0) ? BL808_SPI0_BASE \
|
||||
: BL808_SPI1_BASE)
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define BL808_SPI_CFG_OFFSET 0x000000 /* spi_config */
|
||||
#define BL808_SPI_INT_STS_OFFSET 0x000004 /* spi_int_sts */
|
||||
#define BL808_SPI_BUS_BUSY_OFFSET 0x000008 /* spi_bus_busy */
|
||||
#define BL808_SPI_PRD_0_OFFSET 0x000010 /* spi_prd_0 */
|
||||
#define BL808_SPI_PRD_1_OFFSET 0x000014 /* spi_prd_1 */
|
||||
#define BL808_SPI_RXD_IGNR_OFFSET 0x000018 /* spi_rxd_ignr */
|
||||
#define BL808_SPI_STO_VALUE_OFFSET 0x00001c /* spi_sto_value */
|
||||
#define BL808_SPI_FIFO_CFG_0_OFFSET 0x000080 /* spi_fifo_config_0 */
|
||||
#define BL808_SPI_FIFO_CFG_1_OFFSET 0x000084 /* spi_fifo_config_1 */
|
||||
#define BL808_SPI_FIFO_WDATA_OFFSET 0x000088 /* spi_fifo_wdata */
|
||||
#define BL808_SPI_FIFO_RDATA_OFFSET 0x00008c /* spi_fifo_rdata */
|
||||
|
||||
/* Register definitions *****************************************************/
|
||||
|
||||
#define BL808_SPI_CFG(n) (BL808_SPI_BASE(n) + BL808_SPI_CFG_OFFSET)
|
||||
#define BL808_SPI_INT_STS(n) (BL808_SPI_BASE(n) + BL808_SPI_INT_STS_OFFSET)
|
||||
#define BL808_SPI_BUS_BUSY(n) (BL808_SPI_BASE(n) + BL808_SPI_BUS_BUSY_OFFSET)
|
||||
#define BL808_SPI_PRD_0(n) (BL808_SPI_BASE(n) + BL808_SPI_PRD_0_OFFSET)
|
||||
#define BL808_SPI_PRD_1(n) (BL808_SPI_BASE(n) + BL808_SPI_PRD_1_OFFSET)
|
||||
#define BL808_SPI_RXD_IGNR(n) (BL808_SPI_BASE(n) + BL808_SPI_RXD_IGNR_OFFSET)
|
||||
#define BL808_SPI_STO_VALUE(n) (BL808_SPI_BASE(n) + BL808_SPI_STO_VALUE_OFFSET)
|
||||
#define BL808_SPI_FIFO_CFG_0(n) (BL808_SPI_BASE(n) + BL808_SPI_FIFO_CFG_0_OFFSET)
|
||||
#define BL808_SPI_FIFO_CFG_1(n) (BL808_SPI_BASE(n) + BL808_SPI_FIFO_CFG_1_OFFSET)
|
||||
#define BL808_SPI_FIFO_WDATA(n) (BL808_SPI_BASE(n) + BL808_SPI_FIFO_WDATA_OFFSET)
|
||||
#define BL808_SPI_FIFO_RDATA(n) (BL808_SPI_BASE(n) + BL808_SPI_FIFO_RDATA_OFFSET)
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
#define SPI_CFG_CR_DEG_CNT_SHIFT (12)
|
||||
#define SPI_CFG_CR_DEG_CNT_MASK (0x0f << SPI_CFG_CR_DEG_CNT_SHIFT)
|
||||
#define SPI_CFG_CR_DEG_EN (1 << 11)
|
||||
#define SPI_CFG_CR_M_CONT_EN (1 << 9)
|
||||
#define SPI_CFG_CR_RXD_IGNR_EN (1 << 8)
|
||||
#define SPI_CFG_CR_BYTE_INV (1 << 7)
|
||||
#define SPI_CFG_CR_BIT_INV (1 << 6)
|
||||
#define SPI_CFG_CR_SCLK_PH (1 << 5)
|
||||
#define SPI_CFG_CR_SCLK_POL (1 << 4)
|
||||
#define SPI_CFG_CR_FRAME_SIZE_SHIFT (2)
|
||||
#define SPI_CFG_CR_FRAME_SIZE_MASK (0x03 << SPI_CFG_CR_FRAME_SIZE_SHIFT)
|
||||
#define SPI_CFG_CR_S_EN (1 << 1)
|
||||
#define SPI_CFG_CR_M_EN (1 << 0)
|
||||
|
||||
#define SPI_INT_STS_CR_FER_EN (1 << 29)
|
||||
#define SPI_INT_STS_CR_TXU_EN (1 << 28)
|
||||
#define SPI_INT_STS_CR_STO_EN (1 << 27)
|
||||
#define SPI_INT_STS_CR_RXF_EN (1 << 26)
|
||||
#define SPI_INT_STS_CR_TXF_EN (1 << 25)
|
||||
#define SPI_INT_STS_CR_END_EN (1 << 24)
|
||||
#define SPI_INT_STS_RSVD_21 (1 << 21)
|
||||
#define SPI_INT_STS_CR_TXU_CLR (1 << 20)
|
||||
#define SPI_INT_STS_CR_STO_CLR (1 << 19)
|
||||
#define SPI_INT_STS_RSVD_18 (1 << 18)
|
||||
#define SPI_INT_STS_RSVD_17 (1 << 17)
|
||||
#define SPI_INT_STS_CR_END_CLR (1 << 16)
|
||||
#define SPI_INT_STS_CR_FER_MASK (1 << 13)
|
||||
#define SPI_INT_STS_CR_TXU_MASK (1 << 12)
|
||||
#define SPI_INT_STS_CR_STO_MASK (1 << 11)
|
||||
#define SPI_INT_STS_CR_RXF_MASK (1 << 10)
|
||||
#define SPI_INT_STS_CR_TXF_MASK (1 << 9)
|
||||
#define SPI_INT_STS_CR_END_MASK (1 << 8)
|
||||
#define SPI_INT_STS_FER_INT (1 << 5)
|
||||
#define SPI_INT_STS_TXU_INT (1 << 4)
|
||||
#define SPI_INT_STS_STO_INT (1 << 3)
|
||||
#define SPI_INT_STS_RXF_INT (1 << 2)
|
||||
#define SPI_INT_STS_TXF_INT (1 << 1)
|
||||
#define SPI_INT_STS_END_INT (1 << 0)
|
||||
|
||||
#define SPI_BUS_BUSY_STS_BUS_BUSY (1 << 0)
|
||||
|
||||
#define SPI_PRD_0_CR_D_PH_1_SHIFT (24)
|
||||
#define SPI_PRD_0_CR_D_PH_1_MASK (0xff << SPI_PRD_0_CR_D_PH_1_SHIFT)
|
||||
#define SPI_PRD_0_CR_D_PH_0_SHIFT (16)
|
||||
#define SPI_PRD_0_CR_D_PH_0_MASK (0xff << SPI_PRD_0_CR_D_PH_0_SHIFT)
|
||||
#define SPI_PRD_0_CR_P_SHIFT (8)
|
||||
#define SPI_PRD_0_CR_P_MASK (0xff << SPI_PRD_0_CR_P_SHIFT)
|
||||
#define SPI_PRD_0_CR_S_MASK (0xff)
|
||||
|
||||
#define SPI_PRD_1_CR_I_MASK (0xff)
|
||||
|
||||
#define SPI_RXD_IGNR_CR_IGNR_S_SHIFT (16)
|
||||
#define SPI_RXD_IGNR_CR_IGNR_S_MASK (0x1f << SPI_RXD_IGNR_CR_RXD_IGNR_S_SHIFT)
|
||||
#define SPI_RXD_IGNR_CR_IGNR_P_MASK (0x1f)
|
||||
|
||||
#define SPI_STO_VALUE_CR_VALUE_MASK (0xfff)
|
||||
|
||||
#define SPI_FIFO_CFG_0_RX_UNDERFLOW (1 << 7)
|
||||
#define SPI_FIFO_CFG_0_RX_OVERFLOW (1 << 6)
|
||||
#define SPI_FIFO_CFG_0_TX_UNDERFLOW (1 << 5)
|
||||
#define SPI_FIFO_CFG_0_TX_OVERFLOW (1 << 4)
|
||||
#define SPI_FIFO_CFG_0_RX_CLR (1 << 3)
|
||||
#define SPI_FIFO_CFG_0_TX_CLR (1 << 2)
|
||||
#define SPI_FIFO_CFG_0_DMA_RX_EN (1 << 1)
|
||||
#define SPI_FIFO_CFG_0_DMA_TX_EN (1 << 0)
|
||||
|
||||
#define SPI_FIFO_CFG_1_RX_TH_SHIFT (24)
|
||||
#define SPI_FIFO_CFG_1_RX_TH_MASK (0x1f << SPI_FIFO_CFG_1_RX_TH_SHIFT)
|
||||
#define SPI_FIFO_CFG_1_TX_TH_SHIFT (16)
|
||||
#define SPI_FIFO_CFG_1_TX_TH_MASK (0x1f << SPI_FIFO_CFG_1_TX_TH_SHIFT)
|
||||
#define SPI_FIFO_CFG_1_RX_CNT_SHIFT (8)
|
||||
#define SPI_FIFO_CFG_1_RX_CNT_MASK (0x3f << SPI_FIFO_CFG_1_RX_CNT_SHIFT)
|
||||
#define SPI_FIFO_CFG_1_TX_CNT_MASK (0x3f)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_SPI_H */
|
||||
@@ -0,0 +1,100 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_DISABLE_OS_API is not set
|
||||
# CONFIG_NSH_DISABLE_LOSMART is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="risc-v"
|
||||
CONFIG_ARCH_ADDRENV=y
|
||||
CONFIG_ARCH_BOARD="ox64"
|
||||
CONFIG_ARCH_BOARD_BL808_OX64=y
|
||||
CONFIG_ARCH_CHIP="bl808"
|
||||
CONFIG_ARCH_CHIP_BL808=y
|
||||
CONFIG_ARCH_DATA_NPAGES=128
|
||||
CONFIG_ARCH_DATA_VBASE=0x80100000
|
||||
CONFIG_ARCH_HEAP_NPAGES=128
|
||||
CONFIG_ARCH_HEAP_VBASE=0x80200000
|
||||
CONFIG_ARCH_INTERRUPTSTACK=2048
|
||||
CONFIG_ARCH_KERNEL_STACKSIZE=3072
|
||||
CONFIG_ARCH_PGPOOL_MAPPING=y
|
||||
CONFIG_ARCH_PGPOOL_PBASE=0x50600000
|
||||
CONFIG_ARCH_PGPOOL_SIZE=4194304
|
||||
CONFIG_ARCH_PGPOOL_VBASE=0x50600000
|
||||
CONFIG_ARCH_RISCV=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARCH_TEXT_NPAGES=128
|
||||
CONFIG_ARCH_TEXT_VBASE=0x80000000
|
||||
CONFIG_ARCH_USE_MMU=y
|
||||
CONFIG_ARCH_USE_MPU=y
|
||||
CONFIG_ARCH_USE_S_MODE=y
|
||||
CONFIG_BL808_SPI0=y
|
||||
CONFIG_BL808_UART0=y
|
||||
CONFIG_BL808_UART1=y
|
||||
CONFIG_BL808_UART2=y
|
||||
CONFIG_BL808_UART3=y
|
||||
CONFIG_BOARDCTL_ROMDISK=y
|
||||
CONFIG_BOARD_LATE_INITIALIZE=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=1120
|
||||
CONFIG_BUILD_KERNEL=y
|
||||
CONFIG_DEBUG_ASSERTIONS=y
|
||||
CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y
|
||||
CONFIG_DEBUG_FEATURES=y
|
||||
CONFIG_DEBUG_FULLOPT=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DEV_ZERO=y
|
||||
CONFIG_ELF=y
|
||||
CONFIG_EXAMPLES_HELLO=m
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_ROMFS=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=3072
|
||||
CONFIG_INIT_FILEPATH="/system/bin/init"
|
||||
CONFIG_INIT_MOUNT=y
|
||||
CONFIG_INIT_MOUNT_FLAGS=0x1
|
||||
CONFIG_INIT_MOUNT_TARGET="/system/bin"
|
||||
CONFIG_INIT_STACKSIZE=3072
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_LIBC_ENVPATH=y
|
||||
CONFIG_LIBC_EXECFUNCS=y
|
||||
CONFIG_LIBC_PERROR_STDOUT=y
|
||||
CONFIG_LIBC_STRERROR=y
|
||||
CONFIG_MEMSET_64BIT=y
|
||||
CONFIG_MEMSET_OPTSPEED=y
|
||||
CONFIG_MM_PGALLOC=y
|
||||
CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_FILE_APPS=y
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PATH_INITIAL="/system/bin"
|
||||
CONFIG_RAM_SIZE=1048576
|
||||
CONFIG_RAM_START=0x50200000
|
||||
CONFIG_READLINE_CMD_HISTORY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_HAVE_PARENT=y
|
||||
CONFIG_SCHED_LPWORK=y
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_STACK_COLORATION=y
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2021
|
||||
CONFIG_SYMTAB_ORDEREDBYNAME=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_SYSTEM_NSH_PROGNAME="init"
|
||||
CONFIG_SYSTEM_SPITOOL=y
|
||||
CONFIG_TESTING_GETPRIME=y
|
||||
CONFIG_TESTING_OSTEST=y
|
||||
CONFIG_UART0_BAUD=2000000
|
||||
CONFIG_UART0_BITS=7
|
||||
CONFIG_UART1_BAUD=2000000
|
||||
CONFIG_UART1_BITS=7
|
||||
CONFIG_UART2_BAUD=2000000
|
||||
CONFIG_UART2_BITS=7
|
||||
CONFIG_UART3_BAUD=2000000
|
||||
CONFIG_UART3_BITS=7
|
||||
CONFIG_UART3_SERIAL_CONSOLE=y
|
||||
CONFIG_USEC_PER_TICK=1000
|
||||
CONFIG_USERLED=y
|
||||
CONFIG_USERLED_LOWER=y
|
||||
@@ -38,6 +38,9 @@
|
||||
#ifdef CONFIG_USERLED
|
||||
#include <nuttx/leds/userled.h>
|
||||
#endif
|
||||
#if defined(CONFIG_BL808_SPI0) || defined(CONFIG_BL808_SPI1)
|
||||
#include "bl808_spi.h"
|
||||
#endif
|
||||
#include "bl808_gpadc.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -170,6 +173,16 @@ void board_late_initialize(void)
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BL808_SPI0
|
||||
struct spi_dev_s *spi0 = bl808_spibus_initialize(0);
|
||||
spi_register(spi0, 0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BL808_SPI1
|
||||
struct spi_dev_s *spi1 = bl808_spibus_initialize(1);
|
||||
spi_register(spi1, 1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NSH_ARCHINIT
|
||||
|
||||
mount(NULL, "/proc", "procfs", 0, NULL);
|
||||
|
||||
Reference in New Issue
Block a user