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arch: arm: cxd56xx: nxstyle updates

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Fix nxstyle complains

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2020-04-03 10:54:55 +02:00
committed by Abdelatif Guettouche
parent 55907b0062
commit 06910819e5
11 changed files with 483 additions and 344 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/cxd56xx/cxd56_adc.c
+50 -30
View File
@@ -277,7 +277,8 @@ static struct cxd56adc_dev_s g_hpadc1priv =
};
#endif
static bool adc_active[CH_MAX] = {
static bool adc_active[CH_MAX] =
{
false, false, false, false, false, false
};
@@ -362,39 +363,44 @@ static int adc_start(adc_ch_t ch, uint8_t freq, FAR struct seq_s *seq,
aerr("SETFIFO failed. %d\n", ret);
return ret;
}
ret = seq_ioctl(seq, 0, SCUIOC_SETFIFOMODE, fifomode);
if (ret < 0)
{
aerr("SETFIFOMODE failed. %d\n", ret);
return ret;
}
if (wm)
{
ret = seq_ioctl(seq, 0, SCUIOC_SETWATERMARK, (unsigned long)wm);
if (ret < 0)
{
aerr("SETWATERMARK failed. %d\n", ret);
return ret;
}
}
if (filter)
{
ret = seq_ioctl(seq, 0, SCUIOC_SETFILTER, (unsigned long)filter);
if (ret < 0)
{
aerr("SETFILTER failed. %d\n", ret);
return ret;
}
}
if (notify)
{
ret = seq_ioctl(seq, 0, SCUIOC_SETNOTIFY, (unsigned long)notify);
if (ret < 0)
{
aerr("SETNOTIFY failed. %d\n", ret);
return ret;
}
}
if (wm)
{
ret = seq_ioctl(seq, 0, SCUIOC_SETWATERMARK, (unsigned long)wm);
if (ret < 0)
{
aerr("SETWATERMARK failed. %d\n", ret);
return ret;
}
}
if (filter)
{
ret = seq_ioctl(seq, 0, SCUIOC_SETFILTER, (unsigned long)filter);
if (ret < 0)
{
aerr("SETFILTER failed. %d\n", ret);
return ret;
}
}
if (notify)
{
ret = seq_ioctl(seq, 0, SCUIOC_SETNOTIFY, (unsigned long)notify);
if (ret < 0)
{
aerr("SETNOTIFY failed. %d\n", ret);
return ret;
}
}
if (ch <= CH3)
{
/* LPADC.A1 LPADC_CH : todo: GPS ch */
@@ -469,6 +475,7 @@ static int adc_start(adc_ch_t ch, uint8_t freq, FAR struct seq_s *seq,
{
val = 0x00000030;
}
#endif
putreg32(val, SCUADCIF_HPADC_AC0);
#endif
@@ -554,6 +561,7 @@ static int adc_start(adc_ch_t ch, uint8_t freq, FAR struct seq_s *seq,
(uint32_t *)SCUADCIF_HPADC1_D2;
putreg32(1, addr);
}
adc_active[ch] = true;
}
else
@@ -603,6 +611,7 @@ static int adc_stop(adc_ch_t ch, FAR struct seq_s *seq)
break;
}
}
if (is_clockdisable)
{
cxd56_lpadc_clock_disable();
@@ -646,6 +655,7 @@ static bool adc_validcheck(int cmd)
{
return true;
}
return false;
}
@@ -689,6 +699,7 @@ static int cxd56_adc_open(FAR struct file *filep)
{
return ret;
}
ainfo("open ch%d freq%d scufifo%d\n", priv->ch, priv->freq, priv->fsize);
return OK;
@@ -721,11 +732,13 @@ static int cxd56_adc_close(FAR struct file *filep)
kmm_free(priv->wm);
priv->wm = NULL;
}
if (priv->filter)
{
kmm_free(priv->filter);
priv->filter = NULL;
}
if (priv->notify)
{
kmm_free(priv->notify);
@@ -876,8 +889,8 @@ static int cxd56_adc_ioctl(FAR struct file *filep, int cmd,
* get sampling interval of ADC.
*
* Input Parameters:
* bustype - SCU_BUS_LPADC0, SCU_BUS_LPADC1, SCU_BUS_LPADC2, SCU_BUS_LPADC3,
* SCU_BUS_HPADC0, SCU_BUS_HPADC1
* bustype - SCU_BUS_LPADC0, SCU_BUS_LPADC1, SCU_BUS_LPADC2,
* SCU_BUS_LPADC3, SCU_BUS_HPADC0, SCU_BUS_HPADC1
* *interval - Sampling interval
* *adjust - Adjustment value used for timestamp calculation
*
@@ -972,6 +985,7 @@ void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust)
{
freq /= 6;
}
#endif
if (freq > 0)
{
@@ -1015,6 +1029,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc0): %d\n", ret);
return ret;
}
#endif
#if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv);
@@ -1023,6 +1038,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc1): %d\n", ret);
return ret;
}
#endif
#if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv);
@@ -1031,6 +1047,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc2): %d\n", ret);
return ret;
}
#endif
#if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv);
@@ -1039,6 +1056,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc3): %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_CXD56_HPADC0
ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv);
@@ -1047,6 +1065,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc0): %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_CXD56_HPADC1
ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv);
@@ -1055,6 +1074,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc1): %d\n", ret);
return ret;
}
#endif
return ret;
arch/arm/src/cxd56xx/cxd56_adc.h
+3 -2
View File
@@ -54,7 +54,7 @@ extern "C"
#endif
/****************************************************************************
* Public Functions
* Public Function Protoypes
****************************************************************************/
/****************************************************************************
@@ -65,7 +65,8 @@ extern "C"
****************************************************************************/
#ifdef CONFIG_CXD56_ADC
void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust);
void cxd56_adc_getinterval(int adctype, uint32_t *interval,
uint16_t *adjust);
#else
#define cxd56_adc_getinterval(adctype, interval, adjust)
#endif
arch/arm/src/cxd56xx/cxd56_backuplog.c
+2
View File
@@ -143,6 +143,7 @@ static void *get_allocated_memory(const char *name, size_t size)
up_backuplog_free(name);
}
}
return NULL;
}
@@ -163,6 +164,7 @@ static int allocate_memory(size_t size)
allocated = i;
break;
}
alloc_bits <<= 1;
}
arch/arm/src/cxd56xx/cxd56_clock.c
+61 -20
View File
@@ -35,6 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
@@ -111,7 +112,8 @@
* Private Types
****************************************************************************/
enum clock_source {
enum clock_source
{
RCOSC = 1,
RTC,
RCRTC,
@@ -139,13 +141,13 @@ struct power_domain
static void cxd56_img_clock_enable(void);
static void cxd56_img_clock_disable(void);
static void cxd56_scu_clock_ctrl(\
uint32_t block, uint32_t intr, int on);
uint32_t block, uint32_t intr, int on);
static void cxd56_scu_peri_clock_enable(\
FAR const struct scu_peripheral *p) __unused;
FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_disable(\
FAR const struct scu_peripheral *p) __unused;
FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_gating(\
FAR const struct scu_peripheral *p, int enable) __unused;
FAR const struct scu_peripheral *p, int enable) __unused;
/****************************************************************************
* Public Data
@@ -177,7 +179,8 @@ static sem_t g_clockexc = SEM_INITIALIZER(1);
* swreset : SWRESET_SCU
* crgintmask : CRG_INT_CLR0, CRG_INT_STAT_RAW0
*
* Each member values are indicated the number of bit in appropriate registers.
* Each member values are indicated the number of bit
* in appropriate registers.
*/
#if defined(CONFIG_CXD56_SPI3)
@@ -305,6 +308,7 @@ static void enable_pwd(int pdid)
do_power_control();
release_pwd_reset(domain);
}
g_digital.refs[pdid]++;
}
@@ -336,6 +340,7 @@ static void enable_apwd(int apdid)
putreg32(domain | (domain << 16), CXD56_TOPREG_ANA_PW_CTL);
do_power_control();
}
g_analog.refs[apdid]++;
}
@@ -359,6 +364,7 @@ static void disable_apwd(int apdid)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: cxd56_rcosc_enable
*
@@ -403,8 +409,8 @@ void cxd56_xosc_enable(void)
* Disable XOSC.
*
* CAUTION:
* This function is tentative. We need to consider that clock source control
* with other devices which XOSC is used.
* This function is tentative. We need to consider that
* clock source control with other devices which XOSC is used.
*
****************************************************************************/
@@ -846,7 +852,8 @@ static void cxd56_spim_clock_enable(void)
busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF,
CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_SPIM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_SPIM | CK_COM_BRG |
@@ -966,24 +973,28 @@ void cxd56_spi_clock_enable(int port)
{
cxd56_img_spi_clock_enable();
}
#endif
#if defined(CONFIG_CXD56_SPI5)
if (port == 5)
{
cxd56_img_wspi_clock_enable();
}
#endif
#if defined(CONFIG_CXD56_SPI0)
if (port == 0)
{
cxd56_spim_clock_enable();
}
#endif
#if defined(CONFIG_CXD56_SPI3)
if (port == 3)
{
cxd56_scu_peri_clock_enable(&g_scuspi);
}
#endif
}
@@ -994,24 +1005,28 @@ void cxd56_spi_clock_disable(int port)
{
cxd56_img_spi_clock_disable();
}
#endif
#if defined(CONFIG_CXD56_SPI5)
if (port == 5)
{
cxd56_img_wspi_clock_disable();
}
#endif
#if defined(CONFIG_CXD56_SPI0)
if (port == 0)
{
cxd56_spim_clock_disable();
}
#endif
#if defined(CONFIG_CXD56_SPI3)
if (port == 3)
{
cxd56_scu_peri_clock_disable(&g_scuspi);
}
#endif
}
@@ -1098,13 +1113,16 @@ void cxd56_spi_clock_gear_adjust(int port, uint32_t maxfreq)
{
divisor += 1;
}
if (divisor > maxdivisor)
{
divisor = maxdivisor;
}
gear = 0x00010000 | divisor;
putreg32(gear, addr);
}
clock_semgive(&g_clockexc);
}
@@ -1132,7 +1150,8 @@ static void cxd56_i2cm_clock_enable(void)
busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF,
CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_I2CM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_I2CM | CK_COM_BRG |
@@ -1184,18 +1203,21 @@ void cxd56_i2c_clock_enable(int port)
{
cxd56_scu_peri_clock_enable(&g_scui2c0);
}
#endif
#if defined(CONFIG_CXD56_I2C1)
if (port == 1)
{
cxd56_scu_peri_clock_enable(&g_scui2c1);
}
#endif
#if defined(CONFIG_CXD56_I2C2)
if (port == 2)
{
cxd56_i2cm_clock_enable();
}
#endif
}
@@ -1213,18 +1235,21 @@ void cxd56_i2c_clock_disable(int port)
{
cxd56_scu_peri_clock_disable(&g_scui2c0);
}
#endif
#if defined(CONFIG_CXD56_I2C1)
if (port == 1)
{
cxd56_scu_peri_clock_disable(&g_scui2c1);
}
#endif
#if defined(CONFIG_CXD56_I2C2)
if (port == 2)
{
cxd56_i2cm_clock_disable();
}
#endif
}
@@ -1242,12 +1267,14 @@ void cxd56_i2c_clock_gate_enable(int port)
{
cxd56_scu_peri_clock_gating(&g_scui2c0, 1);
}
#endif
#if defined(CONFIG_CXD56_I2C1)
if (port == 1)
{
cxd56_scu_peri_clock_gating(&g_scui2c1, 1);
}
#endif
}
@@ -1265,32 +1292,34 @@ void cxd56_i2c_clock_gate_disable(int port)
{
cxd56_scu_peri_clock_gating(&g_scui2c0, 0);
}
#endif
#if defined(CONFIG_CXD56_I2C1)
if (port == 1)
{
cxd56_scu_peri_clock_gating(&g_scui2c1, 0);
}
#endif
}
uint32_t cxd56_get_img_uart_baseclock(void)
{
uint32_t val;
int n;
int m;
uint32_t val;
int n;
int m;
val = getreg32(CXD56_CRG_GEAR_IMG_UART);
n = (val >> 16) & 1;
m = val & 0x7f;
val = getreg32(CXD56_CRG_GEAR_IMG_UART);
n = (val >> 16) & 1;
m = val & 0x7f;
if (n && m)
if (n && m)
{
return cxd56_get_appsmp_baseclock() * n / m;
return cxd56_get_appsmp_baseclock() * n / m;
}
else
{
return 0;
return 0;
}
}
@@ -1649,24 +1678,28 @@ uint32_t cxd56_get_spi_baseclock(int port)
{
return cxd56_get_img_spi_baseclock();
}
#endif
#if defined(CONFIG_CXD56_SPI5)
if (port == 5)
{
return cxd56_get_img_wspi_baseclock();
}
#endif
#if defined(CONFIG_CXD56_SPI0)
if (port == 0)
{
return cxd56_get_com_baseclock();
}
#endif
#if defined(CONFIG_CXD56_SPI3)
if (port == 3)
{
return cxd56_get_scu_baseclock();
}
#endif
return 0;
}
@@ -1678,18 +1711,21 @@ uint32_t cxd56_get_i2c_baseclock(int port)
{
return cxd56_get_scu_baseclock();
}
#endif
#if defined(CONFIG_CXD56_I2C1)
if (port == 1)
{
return cxd56_get_scu_baseclock();
}
#endif
#if defined(CONFIG_CXD56_I2C2)
if (port == 2)
{
return cxd56_get_com_baseclock();
}
#endif
return 0;
}
@@ -1753,6 +1789,7 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
return;
}
putreg32(val | block, CXD56_TOPREG_SCU_CKEN);
}
else
@@ -1763,6 +1800,7 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
return;
}
putreg32(val & ~block, CXD56_TOPREG_SCU_CKEN);
}
@@ -1771,6 +1809,7 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0);
busy_wait(1000);
}
while (retry-- && !(stat & intr));
putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
@@ -1814,7 +1853,8 @@ static void cxd56_scu_clock_enable(void)
/* Enable each blocks in SCU */
val = getreg32(CXD56_TOPREG_SCU_CKEN);
putreg32(val | SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ, CXD56_TOPREG_SCU_CKEN);
putreg32(val | SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ,
CXD56_TOPREG_SCU_CKEN);
do
{
@@ -2350,6 +2390,7 @@ int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
val |= 1 << i;
}
}
putreg32(val, CXD56_CRG_APP_TILE_CLK_GATING_ENB);
}
arch/arm/src/cxd56xx/cxd56_clock.h
+1 -1
View File
@@ -71,7 +71,7 @@ extern "C"
#endif
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
arch/arm/src/cxd56xx/cxd56_config.h
+2 -6
View File
@@ -56,8 +56,8 @@
# define HAVE_UART 1
#endif
/* Make sure all features are disabled for disabled U[S]ARTs. This simplifies
* checking later.
/* Make sure all features are disabled for disabled U[S]ARTs.
* This simplifies checking later.
*/
#ifndef CONFIG_CXD56_UART0
@@ -131,8 +131,4 @@
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CONFIG_H */
arch/arm/src/cxd56xx/cxd56_cpufifo.c
+4
View File
@@ -33,6 +33,10 @@
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
arch/arm/src/cxd56xx/cxd56_delay.c
+1
View File
@@ -112,6 +112,7 @@ void up_udelay(useconds_t microseconds)
{
}
}
loops = loops * (microseconds % 1000) / CXD56XX_LOOPSPERUSEC_ADJUST;
for (i = 0; i < loops; i++)
{
arch/arm/src/cxd56xx/cxd56_dmac.c
+344 -280
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/cxd56xx/cxd56_dmac.h
+7 -2
View File
@@ -37,6 +37,10 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include "cxd56_dmac_common.h"
@@ -185,8 +189,9 @@ void cxd56_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
* Name: cxd56_dmastop
*
* Description:
* Cancel the DMA. After cxd56_dmastop() is called, the DMA channel is reset
* and cxd56_dmasetup() must be called before cxd56_dmastart() can be called
* Cancel the DMA.
* After cxd56_dmastop() is called, the DMA channel is reset and
* cxd56_dmasetup() must be called before cxd56_dmastart() can be called
* again
*
* Assumptions:
arch/arm/src/cxd56xx/cxd56_dmac_common.h
+8 -3
View File
@@ -38,14 +38,18 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA_HANDLE provides an opaque are reference that can be used to represent a
* DMA channel.
/* DMA_HANDLE provides an opaque are reference that can be used to represent
* a DMA channel.
*/
typedef FAR void *DMA_HANDLE;
@@ -70,7 +74,8 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
* this should be changed to a uint32_t.
*/
typedef struct {
typedef struct
{
uint16_t channel_cfg;
uint8_t dest_width;
uint8_t src_width;