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https://github.com/apache/nuttx.git
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Many STM32 header files updated for F3 support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5635 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -203,12 +203,12 @@
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#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
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#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define ACD_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
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# define ACD_CR1_RES_MASK (3 << ACD_CR1_RES_SHIFT)
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# define ACD_CR1_RES_12BIT (0 << ACD_CR1_RES_SHIFT) /* 15 ADCCLK clyes */
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# define ACD_CR1_RES_10BIT (1 << ACD_CR1_RES_SHIFT) /* 13 ADCCLK clyes */
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# define ACD_CR1_RES_8BIT (2 << ACD_CR1_RES_SHIFT) /* 11 ADCCLK clyes */
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# define ACD_CR1_RES_6BIT (3 << ACD_CR1_RES_SHIFT) /* 9 ADCCLK clyes */
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# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
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# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
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# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK clyes */
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# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK clyes */
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# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK clyes */
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# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK clyes */
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# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
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#endif
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@@ -252,12 +252,12 @@
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# define ADC_CR2_JEXTSEL_T8CC4 (14 << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */
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# define ADC_CR2_JEXTSEL_EXTI (15 << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line15 */
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# define ACD_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
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# define ACD_CR2_JEXTEN_MASK (3 << ACD_CR2_JEXTEN_SHIFT)
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# define ACD_CR2_JEXTEN_NONE (0 << ACD_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
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# define ACD_CR2_JEXTEN_RISING (1 << ACD_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
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# define ACD_CR2_JEXTEN_FALLING (2 << ACD_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
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# define ACD_CR2_JEXTEN_BOTH (3 << ACD_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
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# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
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# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
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# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
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# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
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# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
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# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
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# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
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/* Bit 23: Reserved, must be kept at reset value. */
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@@ -280,12 +280,12 @@
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# define ADC_CR2_EXTSEL_T8TRGO (14 << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
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# define ADC_CR2_EXTSEL_EXTI (15 << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line11 */
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# define ACD_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
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# define ACD_CR2_EXTEN_MASK (3 << ACD_CR2_EXTEN_SHIFT)
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# define ACD_CR2_EXTEN_NONE (0 << ACD_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
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# define ACD_CR2_EXTEN_RISING (1 << ACD_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
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# define ACD_CR2_EXTEN_FALLING (2 << ACD_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
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# define ACD_CR2_EXTEN_BOTH (3 << ACD_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
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# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
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# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
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# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
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# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
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# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
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# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
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# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
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@@ -369,25 +369,25 @@
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/* ADC sample time register 2 */
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#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
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#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR1_SMP0_SHIFT)
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#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
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#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
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#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT)
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#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
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#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
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#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT)
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#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
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#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
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#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT)
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#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
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#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
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#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT)
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#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
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#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
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#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT)
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#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
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#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
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#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT)
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#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
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#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
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#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT)
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#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
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#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
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#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT)
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#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
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#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
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#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT)
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#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
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/* ADC injected channel data offset register 1-4 */
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@@ -455,7 +455,7 @@
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#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */
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#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
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#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */
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#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK)
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#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
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#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */
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#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
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#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_can.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -61,7 +61,8 @@
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/* Number of filters depends on silicon */
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#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || \
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defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
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# define CAN_NFILTERS 28
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#else
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# define CAN_NFILTERS 14
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@@ -271,7 +272,7 @@
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#define CAN_MSR_SLAKI (1 << 4) /* Bit 4: Sleep acknowledge interrupt */
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#define CAN_MSR_TXM (1 << 8) /* Bit 8: Transmit Mode */
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#define CAN_MSR_RXM (1 << 9) /* Bit 9: Receive Mode */
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#define CAN_MSR_SAMP (1 << 20) /* Bit 10: Last Sample Point */
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#define CAN_MSR_SAMP (1 << 10) /* Bit 10: Last Sample Point */
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#define CAN_MSR_RX (1 << 11) /* Bit 11: CAN Rx Signal */
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/* CAN transmit status register */
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_dac.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -86,9 +86,10 @@
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/* DAC control register */
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/* These definitions may be used for 16-bit values of either channel */
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#define DAC_CR_EN (1 << 0) /* Bit 0: DAC channel1 enable */
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#define DAC_CR_BOFF (1 << 1) /* Bit 1: DAC channel1 output buffer disable */
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#define DAC_CR_TSEL_SHIFT (3) /* Bits 3-5: DAC channel1 trigger selection */
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#define DAC_CR_EN (1 << 0) /* Bit 0: DAC channel enable */
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#define DAC_CR_BOFF (1 << 1) /* Bit 1: DAC channel output buffer disable */
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#define DAC_CR_TEN (1 << 2) /* Bit 2: DAC channel trigger enable */
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#define DAC_CR_TSEL_SHIFT (3) /* Bits 3-5: DAC channel trigger selection */
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#define DAC_CR_TSEL_MASK (7 << DAC_CR_TSEL_SHIFT)
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# define DAC_CR_TSEL_TIM6 (0 << DAC_CR_TSEL_SHIFT) /* Timer 6 TRGO event */
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#ifdef CONFIG_STM32_CONNECTIVITYLINE
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@@ -102,14 +103,14 @@
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# define DAC_CR_TSEL_TIM4 (5 << DAC_CR_TSEL_SHIFT) /* Timer 4 TRGO event */
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# define DAC_CR_TSEL_EXT9 (6 << DAC_CR_TSEL_SHIFT) /* External line9 */
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# define DAC_CR_TSEL_SW (7 << DAC_CR_TSEL_SHIFT) /* Software trigger */
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#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel1 noise/triangle wave generation */enable
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#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */enable
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#define DAC_CR_WAVE_MASK (3 << DAC_CR_WAVE_SHIFT)
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# define DAC_CR_WAVE_DISABLED (0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */
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# define DAC_CR_WAVE_NOISE (1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */
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# define DAC_CR_WAVE_TRIANGLE (2 << DAC_CR_WAVE_SHIFT) /* Triangle wave generation enabled */
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#define DAC_CR_MAMP_SHIFT (8) /* Bits 8-11: DAC channel1 mask/amplitude selector */
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#define DAC_CR_MAMP_SHIFT (8) /* Bits 8-11: DAC channel mask/amplitude selector */
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#define DAC_CR_MAMP_MASK (15 << DAC_CR_MAMP_SHIFT)
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# define DAC_CR_MAMP_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */
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# define DAC_CR_MAMP_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */
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# define DAC_CR_MAMP_AMP3 (1 << DAC_CR_MAMP_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */
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# define DAC_CR_MAMP_AMP7 (2 << DAC_CR_MAMP_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */
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# define DAC_CR_MAMP_AMP15 (3 << DAC_CR_MAMP_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */
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@@ -121,13 +122,14 @@
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# define DAC_CR_MAMP_AMP1023 (9 << DAC_CR_MAMP_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */
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# define DAC_CR_MAMP_AMP2047 (10 << DAC_CR_MAMP_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */
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# define DAC_CR_MAMP_AMP4095 (11 << DAC_CR_MAMP_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */
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#define DAC_CR_DMAEN (1 << 12) /* Bit 12: DAC channel1 DMA enable */
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#define DAC_CR_DMAUDRIE (1 << 13) /* Bit 13: DAC channel1 DMA Underrun Interrupt enable */
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#define DAC_CR_DMAEN (1 << 12) /* Bit 12: DAC channel DMA enable */
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#define DAC_CR_DMAUDRIE (1 << 13) /* Bit 13: DAC channel DMA Underrun Interrupt enable */
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/* These definitions may be used with the full, 32-bit register */
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#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel1 enable */
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#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel1 output buffer disable */
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#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel1 trigger enable */
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#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel1 trigger selection */
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#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT)
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# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */
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@@ -1,7 +1,7 @@
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32_dbgmcu.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -117,6 +117,18 @@
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# define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: SMBUS timeout mode stopped when Core is halted */
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# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
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# define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */
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#elif defined(CONFIG_STM32_STM32F30XX)
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# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
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# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
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# define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
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# define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
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# define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
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# define DBGMCU_CR_RTCSTOP (1 << 10) /* Bit 11: RTC stopped when Core is halted */
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# define DBGMCU_CR_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
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# define DBGMCU_CR_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
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# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */
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# define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: SMBUS timeout mode stopped when Core is halted */
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# define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */
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#endif
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/* Debug MCU APB2 freeze register */
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@@ -127,6 +139,12 @@
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# define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */
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# define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */
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# define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */
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#elif defined(CONFIG_STM32_STM32F30XX)
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# define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */
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# define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */
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# define DBGMCU_APB2_TIM15STOP (1 << 2) /* Bit 2: TIM15 stopped when core is halted */
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# define DBGMCU_APB2_TIM16STOP (1 << 3) /* Bit 3: TIM16 stopped when core is halted */
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# define DBGMCU_APB2_TIM17STOP (1 << 4) /* Bit 4: TIM17 stopped when core is halted */
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#endif
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/****************************************************************************************************
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_exti.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -55,6 +55,11 @@
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# define STM32_NEXTI 19
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# define STM32_EXTI_MASK 0x0007ffff
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# endif
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#eif defined(CONFIG_STM32_STM32F30XX)
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# define STM32_NEXTI1 31
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# define STM32_EXTI1_MASK 0xffffffff
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# define STM32_NEXTI2 4
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# define STM32_EXTI2_MASK 0x0000000f
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define STM32_NEXTI 23
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# define STM32_EXTI_MASK 0x007fffff
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@@ -64,6 +69,11 @@
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/* Register Offsets *****************************************************************/
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#if defined(CONFIG_STM32_STM32F30XX)
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# define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */
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# define STM32_EXTI2_OFFSET 0x0018 /* Offset to EXTI2 registers */
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#endif
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#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
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#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
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#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
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@@ -73,12 +83,39 @@
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/* Register Addresses ***************************************************************/
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#define STM32_EXTI_IMR (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET)
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#define STM32_EXTI_EMR (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET)
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#define STM32_EXTI_RTSR (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI_FTSR (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI_SWIER (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI_PR (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET)
|
||||
# define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET)
|
||||
|
||||
# define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
# define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
# define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
# define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
# define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
# define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET)
|
||||
|
||||
# define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
# define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
# define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
# define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
# define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
# define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET)
|
||||
|
||||
# define STM32_EXTI_IMR STM32_EXTI1_IMR
|
||||
# define STM32_EXTI_EMR STM32_EXTI1_EMR
|
||||
# define STM32_EXTI_RTSR STM32_EXTI1_RTSR
|
||||
# define STM32_EXTI_FTSR STM32_EXTI1_FTSR
|
||||
# define STM32_EXTI_SWIER STM32_EXTI1_SWIER
|
||||
# define STM32_EXTI_PR STM32_EXTI1_PR
|
||||
|
||||
#else
|
||||
# define STM32_EXTI_IMR (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
# define STM32_EXTI_EMR (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
# define STM32_EXTI_RTSR (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
# define STM32_EXTI_FTSR (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
# define STM32_EXTI_SWIER (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
# define STM32_EXTI_PR (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
@@ -138,4 +175,17 @@
|
||||
#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_IMR_MASK STM32_EXTI_MASK
|
||||
|
||||
/* Compatibility Definitions ********************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define STM32_NEXTI STM32_NEXTI1
|
||||
# define STM32_EXTI_MASK STM32_EXTI1_MASK
|
||||
# define STM32_EXTI_IMR STM32_EXTI1_IMR
|
||||
# define STM32_EXTI_EMR STM32_EXTI1_EMR
|
||||
# define STM32_EXTI_RTSR STM32_EXTI1_RTSR
|
||||
# define STM32_EXTI_FTSR STM32_EXTI1_FTSR
|
||||
# define STM32_EXTI_SWIER STM32_EXTI1_SWIER
|
||||
# define STM32_EXTI_PR STM32_EXTI1_PR
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H */
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_pwr.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -93,7 +93,12 @@
|
||||
# define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */
|
||||
#endif
|
||||
|
||||
#define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */
|
||||
# define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */
|
||||
#else
|
||||
# define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
# define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_wdg.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -50,85 +50,102 @@
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */
|
||||
#endif
|
||||
|
||||
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
|
||||
#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
|
||||
#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
|
||||
#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
|
||||
#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
|
||||
#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
|
||||
#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
|
||||
#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
|
||||
#endif
|
||||
|
||||
#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
|
||||
#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
|
||||
#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
|
||||
#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
|
||||
#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
|
||||
#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Key register (32-bit) */
|
||||
|
||||
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
|
||||
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
|
||||
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
|
||||
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
|
||||
|
||||
#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
|
||||
#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
|
||||
#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
|
||||
#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
|
||||
#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
|
||||
#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
|
||||
#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
|
||||
#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
|
||||
|
||||
/* Prescaler register (32-bit) */
|
||||
|
||||
#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
|
||||
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
|
||||
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
|
||||
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
|
||||
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
|
||||
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
|
||||
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
|
||||
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
|
||||
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
|
||||
#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
|
||||
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
|
||||
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
|
||||
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
|
||||
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
|
||||
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
|
||||
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
|
||||
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
|
||||
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
|
||||
|
||||
/* Reload register (32-bit) */
|
||||
|
||||
#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
|
||||
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
|
||||
#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
|
||||
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
|
||||
|
||||
#define IWDG_RLR_MAX (0xfff)
|
||||
#define IWDG_RLR_MAX (0xfff)
|
||||
|
||||
/* Status register (32-bit) */
|
||||
|
||||
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
|
||||
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
|
||||
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
|
||||
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define IWDG_SR_WVU (1 << 2) /* Bit 2: */
|
||||
#endif
|
||||
|
||||
/* Window register (32-bit) */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# define IWDG_WINR_SHIFT (0)
|
||||
# define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Control Register (32-bit) */
|
||||
|
||||
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
|
||||
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
|
||||
# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
|
||||
# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
|
||||
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
|
||||
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
|
||||
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
|
||||
# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
|
||||
# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
|
||||
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
|
||||
|
||||
/* Configuration register (32-bit) */
|
||||
|
||||
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
|
||||
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
|
||||
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
|
||||
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
|
||||
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
|
||||
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
|
||||
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
|
||||
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
|
||||
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
|
||||
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
|
||||
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
|
||||
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
|
||||
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
|
||||
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
|
||||
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
|
||||
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
|
||||
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
|
||||
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
|
||||
|
||||
/* Status register (32-bit) */
|
||||
|
||||
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
|
||||
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -63,9 +63,19 @@
|
||||
#include "stm32.h"
|
||||
#include "stm32_adc.h"
|
||||
|
||||
/* ADC "upper half" support must be enabled */
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
|
||||
/* Some ADC peripheral must be enabled */
|
||||
|
||||
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
|
||||
|
||||
/* This implementation is for the STM32 F1, F2, and F4 only */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
@@ -1541,6 +1551,6 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nch
|
||||
return dev;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */
|
||||
#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
|
||||
#endif /* CONFIG_ADC */
|
||||
|
||||
|
||||
@@ -43,7 +43,12 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_adc.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_adc.h"
|
||||
#else
|
||||
# include "chip/stm32_adc.h"
|
||||
#endif
|
||||
|
||||
#include <nuttx/analog/adc.h>
|
||||
|
||||
|
||||
@@ -113,8 +113,8 @@ void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions)
|
||||
FAR struct spawn_open_file_action_s *action =
|
||||
(FAR struct spawn_open_file_action_s *)entry;
|
||||
|
||||
svdbg(" OPEN: path=%s oflags=%04x mode=%04x fd=%d\n",
|
||||
action->path, action->oflags, action->mode, action->fd);
|
||||
dbg(" OPEN: path=%s oflags=%04x mode=%04x fd=%d\n",
|
||||
action->path, action->oflags, action->mode, action->fd);
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user