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STM32 GPIO fix; Fixes for PIC32 USB term example

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4241 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-12-30 14:54:43 +00:00
parent 5af05e03cd
commit 0332c4742b
3 changed files with 21 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32/stm32_gpio.c
+10 -10
View File
@@ -563,9 +563,17 @@ int stm32_configgpio(uint32_t cfgset)
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
/* If it is an input pin, hould it configured as an EXTI interrupt? */
/* If it is an output... set the pin to the correct initial state. */
if ((cfgset & GPIO_EXTI) != 0)
if (pinmode == GPIO_MODER_OUTPUT)
{
bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
stm32_gpiowrite(cfgset, value);
}
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
else if ((cfgset & GPIO_EXTI) != 0)
{
/* "In STM32 F1 the selection of the EXTI line source is performed through
* the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
@@ -590,14 +598,6 @@ int stm32_configgpio(uint32_t cfgset)
putreg32(regval, regaddr);
}
/* If it is an output... set the pin to the correct initial state. */
else if (pinmode == GPIO_MODER_OUTPUT)
{
bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
stm32_gpiowrite(cfgset, value);
}
irqrestore(flags);
return OK;
arch/arm/src/stm32/stm32_start.c
-3
View File
@@ -78,9 +78,6 @@
* Configure the FPU. The the MCU has an FPU, then enable full access
* to coprocessors CP10 and CP11.
*
* This is implemented as a macro because the stack has not yet been
* initialized.
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
arch/mips/src/pic32mx/pic32mx-usbdev.c
+11 -11
View File
@@ -919,7 +919,7 @@ static int pic32mx_rdcomplete(struct pic32mx_usbdev_s *priv,
* RX will be marked valid when the data phase completes.
*/
usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd);
usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
pic32mx_reqcomplete(privep, OK);
}
@@ -1141,7 +1141,7 @@ static void pic32mx_ep0stall(struct pic32mx_usbdev_s *priv)
uint16_t status = (USB_BDT_UOWN| USB_BDT_DATA0 | USB_BDT_DTS | USB_BDT_BSTALL);
regdbg("EP0 BDT OUT {%08x, %08x}\n", status, ep0->bdtout->status->addr);
regdbg("EP0 BDT OUT {%08x, %08x}\n", status, ep0->bdtout->addr);
ep0->bdtout->status = status;
}
@@ -1172,7 +1172,7 @@ static void pic32mx_eptransfer(struct pic32mx_usbdev_s *priv, uint8_t epno,
{
/* OUT: host-to-device */
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EPOUTDONE), epr);
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EPOUTDONE), status);
/* Handle read requests. First check if a read request is available to
* accept the host data.
@@ -1197,7 +1197,7 @@ static void pic32mx_eptransfer(struct pic32mx_usbdev_s *priv, uint8_t epno,
{
/* IN: device-to-host */
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EPINDONE), epr);
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EPINDONE), status);
/* Handle write requests */
@@ -1286,7 +1286,7 @@ static void pic32mx_ep0done(struct pic32mx_usbdev_s *priv,
bdtout->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl);
regdbg("EP0 BDT OUT (Next) {%08x, %08x}\n", status, ep0->btdnext->addr);
regdbg("EP0 BDT OUT (Next) {%08x, %08x}\n", status, bdtout->addr);
bdtout->status = status;
@@ -1297,7 +1297,7 @@ static void pic32mx_ep0done(struct pic32mx_usbdev_s *priv,
btdnext->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl);
regdbg("EP0 BDT OUT {%08x, %08x}\n", status, ep0->bdtout->addr);
regdbg("EP0 BDT OUT {%08x, %08x}\n", status, btdnext->addr);
btdnext->status = status;
#endif
@@ -1310,7 +1310,7 @@ static void pic32mx_ep0done(struct pic32mx_usbdev_s *priv,
ep0->bdtin->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl);
regdbg("EP0 BDT IN {%08x, %08x}\n", status, p0->bdtin->addr);
regdbg("EP0 BDT IN {%08x, %08x}\n", status, ep0->bdtin->addr);
ep0->bdtin->status = status;
}
@@ -2106,14 +2106,14 @@ static void pic32mx_ep0transfer(struct pic32mx_usbdev_s *priv, uint16_t status)
/* Handle the control OUT transfer */
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0SETUPDONE), epr);
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0SETUPDONE), bdt->status);
pic32mx_ep0setup(priv);
}
else
{
/* Handle the data OUT transfer */
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0OUTDONE), epr);
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0OUTDONE), status);
pic32mx_ep0out(priv);
}
}
@@ -2122,7 +2122,7 @@ static void pic32mx_ep0transfer(struct pic32mx_usbdev_s *priv, uint16_t status)
else /* if ((status & USB_STAT_DIR) == USB_STAT_DIR_IN) */
{
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0INDONE), epr);
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0INDONE), status);
/* Handle the IN transfer */
@@ -3493,6 +3493,7 @@ static void pic32mx_hwreset(struct pic32mx_usbdev_s *priv)
/* Initialize EP0 as a Ctrl EP */
pic32mx_putreg(PIC32MX_EP_CONTROL, PIC32MX_USB_EP0);
regdbg("PIC32MX_USB_EP0: %04x\n", getreg16(PIC32MX_USB_EP0));
/* Flush any pending transactions */
@@ -3514,7 +3515,6 @@ static void pic32mx_hwreset(struct pic32mx_usbdev_s *priv)
/* Indicate that we are now in the detached state */
priv->devstate = DEVSTATE_DETACHED;
regdbg("PIC32MX_USB_EP%d: %04x\n", epno, getreg16(PIC32MX_USB_EP(epno)));
}
/****************************************************************************