Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-04 23:03:27 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Removes STM32_BOARD_HCLK from all board.h files. It is now unneccessary. Use STM32_HCLK_FREQUENCY instead.

Browse Source
This commit is contained in:
Anthony Merlino
2021-04-06 14:11:02 -04:00
committed by Xiang Xiao
parent 8c73ea68d6
commit 028aca433c
63 changed files with 1 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/arm/stm32/axoloti/include/board.h
-1
View File
@@ -117,7 +117,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/b-g431b-esc1/include/board.h
-1
View File
@@ -109,7 +109,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* APB1 clock (PCLK1) is HCLK (170MHz) */ /* APB1 clock (PCLK1) is HCLK (170MHz) */
boards/arm/stm32/b-g474e-dpow1/include/board.h
-1
View File
@@ -109,7 +109,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* APB1 clock (PCLK1) is HCLK (170MHz) */ /* APB1 clock (PCLK1) is HCLK (170MHz) */
boards/arm/stm32/clicker2-stm32/include/board.h
-1
View File
@@ -127,7 +127,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/cloudctrl/include/board.h
-1
View File
@@ -83,7 +83,6 @@
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/fire-stm32v2/include/board.h
-1
View File
@@ -72,7 +72,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/hymini-stm32v/include/board.h
-1
View File
@@ -56,7 +56,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/maple/include/board.h
-1
View File
@@ -79,7 +79,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/mikroe-stm32f4/include/board.h
-1
View File
@@ -102,7 +102,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/nucleo-f103rb/include/board.h
-1
View File
@@ -74,7 +74,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/nucleo-f207zg/include/board.h
-1
View File
@@ -93,7 +93,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/2 (25MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (25MHz) */
boards/arm/stm32/nucleo-f302r8/include/board.h
-1
View File
@@ -74,7 +74,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/nucleo-f303re/include/board.h
-1
View File
@@ -93,7 +93,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/nucleo-f303ze/include/board.h
-1
View File
@@ -75,7 +75,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/nucleo-f334r8/include/board.h
-1
View File
@@ -74,7 +74,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/nucleo-f410rb/include/board.h
+1 -2
View File
@@ -77,7 +77,7 @@
* *
* VCO input frequency = PLL input clock frequency / PLLM, * VCO input frequency = PLL input clock frequency / PLLM,
* 2 <= PLLM <= 63 * 2 <= PLLM <= 63
* VCO output frequency = VCO input frequency × PLLN, * VCO output frequency = VCO input frequency � PLLN,
* 50 <= PLLN <= 432 * 50 <= PLLN <= 432
* PLL output clock frequency = VCO frequency / PLLP, * PLL output clock frequency = VCO frequency / PLLP,
* PLLP = 2, 4, 6, or 8 * PLLP = 2, 4, 6, or 8
@@ -110,7 +110,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/2 (50MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (50MHz) */
boards/arm/stm32/nucleo-f412zg/include/board.h
-1
View File
@@ -90,7 +90,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
boards/arm/stm32/nucleo-f429zi/include/board.h
-1
View File
@@ -100,7 +100,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
boards/arm/stm32/nucleo-f446re/include/board.h
-1
View File
@@ -118,7 +118,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (52MHz) */
boards/arm/stm32/nucleo-f4x1re/include/nucleo-f401re.h
-1
View File
@@ -119,7 +119,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (42MHz) */
boards/arm/stm32/nucleo-f4x1re/include/nucleo-f411re.h
-1
View File
@@ -116,7 +116,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ /* APB1 clock (PCLK1) is HCLK/2 (52MHz) */
boards/arm/stm32/nucleo-g431rb/include/board.h
-1
View File
@@ -109,7 +109,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* APB1 clock (PCLK1) is HCLK (170MHz) */ /* APB1 clock (PCLK1) is HCLK (170MHz) */
boards/arm/stm32/nucleo-l152re/include/board.h
-1
View File
@@ -120,7 +120,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (32MHz) */ /* APB2 clock (PCLK2) is HCLK (32MHz) */
boards/arm/stm32/olimex-stm32-e407/include/board.h
-1
View File
@@ -114,7 +114,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/olimex-stm32-h405/include/board.h
-1
View File
@@ -77,7 +77,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (30MHz) */
boards/arm/stm32/olimex-stm32-h407/include/board.h
-1
View File
@@ -114,7 +114,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/olimex-stm32-p107/include/board.h
-1
View File
@@ -65,7 +65,6 @@
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/olimex-stm32-p207/include/board.h
-1
View File
@@ -77,7 +77,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (30MHz) */
boards/arm/stm32/olimex-stm32-p407/include/board.h
-1
View File
@@ -74,7 +74,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/olimexino-stm32/include/board.h
-1
View File
@@ -73,7 +73,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/omnibusf4/include/board.h
-1
View File
@@ -117,7 +117,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/photon/include/board.h
-1
View File
@@ -117,7 +117,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (30MHz) */
boards/arm/stm32/shenzhou/include/board.h
-1
View File
@@ -67,7 +67,6 @@
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/stm3210e-eval/include/board.h
-1
View File
@@ -65,7 +65,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/stm3220g-eval/include/board.h
-1
View File
@@ -113,7 +113,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (30MHz) */
boards/arm/stm32/stm3240g-eval/include/board.h
-1
View File
@@ -114,7 +114,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/stm32_tiny/include/board.h
-1
View File
@@ -62,7 +62,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/stm32butterfly2/include/board.h
-1
View File
@@ -79,7 +79,6 @@
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* USB clock output is 47.9232MHz */ /* USB clock output is 47.9232MHz */
boards/arm/stm32/stm32f103-minimum/include/board.h
-1
View File
@@ -59,7 +59,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/stm32f334-disco/include/board.h
-1
View File
@@ -74,7 +74,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/stm32f3discovery/include/board.h
-1
View File
@@ -73,7 +73,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/stm32f411-minimum/include/board.h
-1
View File
@@ -109,7 +109,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (24MHz) */
boards/arm/stm32/stm32f411e-disco/include/board.h
-1
View File
@@ -130,7 +130,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (24MHz) */
boards/arm/stm32/stm32f429i-disco/include/board.h
-1
View File
@@ -102,7 +102,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/stm32f4discovery/include/board.h
-1
View File
@@ -103,7 +103,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
boards/arm/stm32/stm32ldiscovery/include/board.h
-1
View File
@@ -121,7 +121,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (32MHz) */ /* APB2 clock (PCLK2) is HCLK (32MHz) */
boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h
-1
View File
@@ -63,7 +63,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h
-1
View File
@@ -64,7 +64,6 @@
#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
/* APB2 clock (PCLK2) is HCLK (72MHz) */ /* APB2 clock (PCLK2) is HCLK (72MHz) */
boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h
-1
View File
@@ -71,7 +71,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
/* APB2 clock (PCLK2) is HCLK (32MHz) */ /* APB2 clock (PCLK2) is HCLK (32MHz) */
boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h
-1
View File
@@ -123,7 +123,6 @@
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK (48MHz) */ /* APB1 clock (PCLK1) is HCLK (48MHz) */

Some files were not shown because too many files have changed in this diff Show More