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lib: add support for A72 Baremetal

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Enable cache, IPI, exception and shared-memory operations on Versal A72
for Libmetal.

Additionally, as the code for A72 and A53 is almost identical, move
the common code to generic/xlnx_common/zynqmp_aarch64 and differentiate
the slight differences with macro checks.

Signed-off-by: Ben Levinsky <ben.levinsky@xilinx.com>

Acked-by: tanmay.shah@xilinx.com
This commit is contained in:
Ben Levinsky
2023-06-29 09:36:00 +02:00
committed by Arnaud Pouliquen
parent cd104fa0fd
commit 6e4b016151
9 changed files with 189 additions and 38 deletions
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lib/system/generic/xlnx_common/CMakeLists.txt
+4
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@@ -2,4 +2,8 @@ collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES irq.c)
if ("${PROJECT_MACHINE}" STREQUAL "zynqmp_a53" OR "${PROJECT_MACHINE}" STREQUAL "zynqmp_a72")
add_subdirectory(zynqmp_aarch64)
endif ("${PROJECT_MACHINE}" STREQUAL "zynqmp_a53" OR "${PROJECT_MACHINE}" STREQUAL "zynqmp_a72")
# vim: expandtab:ts=2:sw=2:smartindent
lib/system/generic/xlnx_common/zynqmp_aarch64/CMakeLists.txt
+2
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@@ -0,0 +1,2 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES sys.c)
lib/system/generic/xlnx_common/zynqmp_aarch64/sys.c
+107
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@@ -0,0 +1,107 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx_common/zynqmp_aarch64/sys.c
* @brief machine specific system primitives implementation.
*/
#include <metal/compiler.h>
#include <metal/io.h>
#include <metal/sys.h>
#include <stdint.h>
#include "xil_cache.h"
#include "xil_exception.h"
#include "xil_mmu.h"
#include "xscugic.h"
#if defined(versal)
#include "xcpu_cortexa72.h"
#else
#include "xreg_cortexa53.h"
#endif /* defined(versal) */
void sys_irq_restore_enable(unsigned int flags)
{
Xil_ExceptionEnableMask(~flags);
}
unsigned int sys_irq_save_disable(void)
{
unsigned int state = mfcpsr() & XIL_EXCEPTION_ALL;
if (state != XIL_EXCEPTION_ALL)
Xil_ExceptionDisableMask(XIL_EXCEPTION_ALL);
return state;
}
void metal_machine_cache_flush(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheFlush();
else
Xil_DCacheFlushRange((intptr_t)addr, len);
}
void metal_machine_cache_invalidate(void *addr, unsigned int len)
{
if (!addr && !len)
Xil_DCacheInvalidate();
else
Xil_DCacheInvalidateRange((intptr_t)addr, len);
}
/**
* @brief poll function until some event happens
*/
void metal_weak metal_generic_default_poll(void)
{
metal_asm volatile("wfi");
}
void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
size_t size, unsigned int flags)
{
unsigned long section_offset;
unsigned long ttb_addr;
#if defined(__aarch64__)
unsigned long ttb_size = (pa < 4 * GB) ? 2 * MB : 1 * GB;
#else
unsigned long ttb_size = 1 * MB;
#endif /* defined(__aarch64__) */
if (!flags)
return va;
/* Ensure alignment on a section boundary */
pa &= ~(ttb_size - 1UL);
/*
* Loop through entire region of memory (one MMU section at a time).
* Each section requires a TTB entry.
*/
for (section_offset = 0; section_offset < size; ) {
/* Calculate translation table entry for this memory section */
ttb_addr = (pa + section_offset);
/* Write translation table entry value to entry address */
Xil_SetTlbAttributes(ttb_addr, flags);
#if defined(__aarch64__)
/*
* recalculate if we started below 4GB and going above in
* 64bit mode
*/
if (ttb_addr >= 4 * GB)
ttb_size = 1 * GB;
#endif
section_offset += ttb_size;
}
return va;
}
lib/system/generic/xlnx_common/zynqmp_aarch64/sys.h
+47
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@@ -0,0 +1,47 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/xlnx_common/zynqmp_aarch64/sys.h
* @brief generic zynqmp_aarch64 system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
#include "xscugic.h"
#ifndef __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__
#define __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_ZYNQMP_XLNX_COMMON_AARCH64_SYS__H__ */
lib/system/generic/zynqmp_a53/CMakeLists.txt
-3
View File
@@ -1,6 +1,3 @@
collect (PROJECT_LIB_HEADERS sys.h)
collect (PROJECT_LIB_SOURCES sys.c)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
# vim: expandtab:ts=2:sw=2:smartindent
lib/system/generic/zynqmp_a53/sys.h
+5 -35
View File
@@ -9,38 +9,8 @@
* @brief generic zynqmp_a53 system primitives for libmetal.
*/
#ifndef __METAL_GENERIC_SYS__H__
#error "Include metal/sys.h instead of metal/generic/@PROJECT_MACHINE@/sys.h"
#endif
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/sys.h>
#include "xscugic.h"
#ifndef __METAL_GENERIC_ZYNQMP_A53_SYS__H__
#define __METAL_GENERIC_ZYNQMP_A53_SYS__H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef METAL_INTERNAL
#define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS
static inline void sys_irq_enable(unsigned int vector)
{
XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
static inline void sys_irq_disable(unsigned int vector)
{
XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector);
}
#endif /* METAL_INTERNAL */
#ifdef __cplusplus
}
#endif
#endif /* __METAL_GENERIC_ZYNQMP_A53_SYS__H__ */
/*
* The header file is still required as generic/sys.h expects
* "./@PROJECT_MACHINE@/sys.h" to still exist.
*/
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
lib/system/generic/zynqmp_a72/CMakeLists.txt
+3
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@@ -0,0 +1,3 @@
collect (PROJECT_LIB_HEADERS sys.h)
add_subdirectory(../xlnx_common ${CMAKE_CURRENT_BINARY_DIR}/../xlnx_common)
lib/system/generic/zynqmp_a72/sys.h
+17
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@@ -0,0 +1,17 @@
/*
* Copyright (c) 2022, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* @file generic/zynqmp_a72/sys.h
* @brief generic zynqmp_a72 system primitives for libmetal.
*/
/*
* The header file is still required as generic/sys.h expects
* "./@PROJECT_MACHINE@/sys.h" to still exist.
*/
#include <metal/system/@PROJECT_SYSTEM@/xlnx_common/zynqmp_aarch64/sys.h>
lib/utilities.h
+4
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +25,9 @@ extern "C" {
* @{
*/
#define MB (1024 * 1024UL)
#define GB (1024 * 1024 * 1024UL)
/** Marker for unused function arguments/variables. */
#define metal_unused(x) do { (x) = (x); } while (0)